Silicon p-FETs from ultrahigh density nanowire arrays

Nano Lett. 2006 Jun;6(6):1096-100. doi: 10.1021/nl052558g.

Abstract

Statistical numbers of field-effect transistors (FETs) were fabricated from a circuit of 17-nm-wide, 34-nm-pitch Si nanowires boron doped at a level of 10(18) cm-3. Top-gated 4-microm-wide Si nanowire p-FETs yielded low off-currents (approximately 10(-12) A), high on/off ratios (10(5)-10(6)), good on current values (30 microA/microm), high mobilities (approximately 100 cm2/V-s), and low subthreshold swing values (approximately 80 mV/decade between 10(-12) and 10(-10) A increasing to 200 mV/decade between 10(-10)-10(-8) A).

Publication types

  • Evaluation Study
  • Research Support, Non-U.S. Gov't
  • Research Support, U.S. Gov't, Non-P.H.S.

MeSH terms

  • Electric Impedance
  • Electric Wiring / instrumentation*
  • Electric Wiring / methods
  • Equipment Design
  • Equipment Failure Analysis
  • Materials Testing
  • Microelectrodes*
  • Nanotechnology / instrumentation*
  • Nanotechnology / methods
  • Nanotubes / chemistry*
  • Nanotubes / ultrastructure
  • Silicon / chemistry*
  • Transistors, Electronic*

Substances

  • Silicon