Reconfigurable embedded system architecture for next-generation Neural Signal Processing

Karthikeyan Balasubramanian; Iyad Obeid

doi:10.1109/IEMBS.2010.5626833

Reconfigurable embedded system architecture for next-generation Neural Signal Processing

Annu Int Conf IEEE Eng Med Biol Soc. 2010:2010:1691-4. doi: 10.1109/IEMBS.2010.5626833.

Authors

Karthikeyan Balasubramanian¹, Iyad Obeid

Affiliation

¹ Neural Instrumentation Lab, Temple University, Philadelphia, PA 19122, USA. [email protected]

PMID: 21096398
DOI: 10.1109/IEMBS.2010.5626833

Abstract

This work presents a new architectural framework for next generation Neural Signal Processing (NSP). The essential features of the NSP hardware platform include scalability, reconfigurability, real-time processing ability and data storage. This proposed framework has been implemented in a proof-of-concept NSP prototype using an embedded system architecture synthesized in a Xilinx(®)Virtex(®)5 development board. The prototype includes a threshold-based spike detector and a fuzzy logic-based spike sorter.

Publication types

Research Support, U.S. Gov't, Non-P.H.S.

MeSH terms

Action Potentials / physiology*
Animals
Computing Methodologies*
Electroencephalography / instrumentation*
Equipment Design
Equipment Failure Analysis
Humans
Neurons / physiology*
Signal Processing, Computer-Assisted / instrumentation*