CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes

Nano Lett. 2009 Jan;9(1):189-97. doi: 10.1021/nl802756u.

Abstract

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

Publication types

  • Research Support, Non-U.S. Gov't
  • Research Support, U.S. Gov't, Non-P.H.S.

MeSH terms

  • Computer-Aided Design
  • Crystallization / methods*
  • Electric Conductivity
  • Equipment Design
  • Equipment Failure Analysis
  • Macromolecular Substances / chemistry
  • Materials Testing
  • Miniaturization
  • Molecular Conformation
  • Nanotechnology / instrumentation*
  • Nanotechnology / methods
  • Nanotubes / chemistry*
  • Nanotubes / ultrastructure*
  • Particle Size
  • Reproducibility of Results
  • Semiconductors
  • Sensitivity and Specificity
  • Surface Properties
  • Transistors, Electronic*

Substances

  • Macromolecular Substances