We present the electrical characterization of wafer-scale graphene devices fabricated with an industrially-relevant, contact-first integration scheme combined with Al2O3encapsulation via atomic layer deposition. All the devices show a statistically significant reduction in the Dirac point position,Vcnp, from around +47 V to between -5 and 5 V (on 285 nm SiO2), while maintaining the mobility values. The data and methods presented are relevant for further integration of graphene devices, specifically sensors, at the back-end-of-line of a standard CMOS flow.
Keywords: atomic layer deposition; electronics; graphene.
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