Suppression of Short-Channel Effects in AlGaN/GaN HEMTs Using SiNx Stress-Engineered Technique

Nanomaterials (Basel). 2024 Nov 13;14(22):1817. doi: 10.3390/nano14221817.

Abstract

In this work, we present the novel application of SiNx stress-engineering techniques for the suppression of short-channel effects in AlGaN/GaN high-electron-mobility transistors (HEMTs), accompanied by a comprehensive analysis of the underlying mechanisms. The compressive stress SiNx passivation significantly enhances the barrier height at the heterojunction beneath the gate, maintaining it above the quasi-Fermi level even as Vds rises to 20 V. As a result, in GaN devices with a gate length of 160 nm, the devices with compressive stress SiNx passivation exhibit significantly lower drain-induced barrier lowering (DIBL) factors of 2.25 mV/V, 2.56 mV/V, 4.71 mV/V, and 3.84 mV/V corresponding to drain bias voltages of 5 V, 10 V, 15 V, and 20 V, respectively. Furthermore, as Vds increases, there is an insignificant degradation in transconductance, subthreshold swing, leakage current, or output conductance. In contrast, the devices with stress-free passivation show relatively higher DIBL factors (greater than 20 mV/V) and substantial degradation in pinch-off performance and output characteristics. These results demonstrate that the SiNx stress-engineering technique is an attractive technique to facilitate high-performance and high-reliability GaN-based HEMTs for radio frequency (RF) electronics applications.

Keywords: DIBL; GaN HEMTs; SCEs; SiNx stress engineered.

Grants and funding

This work was supported by Fabrication of Normally-Off GaN Devices based on In situ SiNx Passivation and Selective Area Growth Recessed-Gate Techniques and the Reliability Study (National Natural Science Foundation of China, grant no.: 62274082), Research on mechanism of Source/Drain ohmic contact and the related GaN p-FET (grant no.: 2023A1515030034), Research on high-reliable GaN power device and the related industrial power system (grant no.: HZQB-KCZYZ-2021052), Study on the reliability of GaN power devices (grant no.: JCYJ20220818100605012), Research on the key technology of 1200 V SiC MOSFETs (grant no.: JSGG20220831094404008), Research on novelty low-resistance Source/Drain ohmic contact for GaN p-FET (grant no.: JCYJ20220530115411025), 5G Frontier” Project (Phase III)—Micro-Nano Processing Platform (grant no.: K2023390010), and a high level of special funds (grant no.: G03034K004).