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Circuit fabrication at 17 nm half-pitch by nanoimprint lithography.
Jung GY, Johnston-Halperin E, Wu W, Yu Z, Wang SY, Tong WM, Li Z, Green JE, Sheriff BA, Boukai A, Bunimovich Y, Heath JR, Williams RS. Jung GY, et al. Among authors: wu w. Nano Lett. 2006 Mar;6(3):351-4. doi: 10.1021/nl052110f. Nano Lett. 2006. PMID: 16522021
Sub-10 nm nanoimprint lithography by wafer bowing.
Wu W, Tong WM, Bartman J, Chen Y, Walmsley R, Yu Z, Xia Q, Park I, Picciotto C, Gao J, Wang SY, Morecroft D, Yang J, Berggren KK, Williams RS. Wu W, et al. Nano Lett. 2008 Nov;8(11):3865-9. doi: 10.1021/nl802295n. Epub 2008 Oct 7. Nano Lett. 2008. PMID: 18837563
Memristor-CMOS hybrid integrated circuits for reconfigurable logic.
Xia Q, Robinett W, Cumbie MW, Banerjee N, Cardinali TJ, Yang JJ, Wu W, Li X, Tong WM, Strukov DB, Snider GS, Medeiros-Ribeiro G, Williams RS. Xia Q, et al. Among authors: wu w. Nano Lett. 2009 Oct;9(10):3640-5. doi: 10.1021/nl901874j. Nano Lett. 2009. PMID: 19722537
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