Towards higher performance and robust compilation for cgra modulo scheduling
Z Zhao, W Sheng, Q Wang, W Yin, P Ye… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Coarse-Grained Reconfigurable Architectures (CGRA) is a promising solution for accelerating
computation intensive tasks due to its good trade-off in energy efficiency and flexibility. …
computation intensive tasks due to its good trade-off in energy efficiency and flexibility. …
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm
W Sheng, L Xiao, Z Mao - Proceedings of the 46th Annual Design …, 2009 - dl.acm.org
A radiation harden technique based on gate sizing and multi-objective genetic algorithm (MOGA)
is developed to optimize the soft error tolerance of standard cell circuits. Soft error rate (…
is developed to optimize the soft error tolerance of standard cell circuits. Soft error rate (…
mrna: Enabling efficient mapping space exploration for a reconfiguration neural accelerator
Deep learning accelerators have emerged to enable energy-efficient and high-throughput
inference from edge devices such as self-driving cars and smartphones, to data centers for …
inference from edge devices such as self-driving cars and smartphones, to data centers for …
Ship detection based on fused features and rebuilt YOLOv3 networks in optical remote-sensing images
…, F Shen, L Cheng, J Jiang, G He, W Sheng… - … Journal of Remote …, 2021 - Taylor & Francis
Automatic ship detection in optical remote-sensing (ORS) images has wide applications in
civil and military fields. Research on ship detection in ORS images started late compared to …
civil and military fields. Research on ship detection in ORS images started late compared to …
Fail-slow at scale: Evidence of hardware performance faults in large production systems
…, S Sundararaman, X Lin, T Emami, W Sheng… - ACM Transactions on …, 2018 - dl.acm.org
Fail-slow hardware is an under-studied failure mode. We present a study of 114 reports of
fail-slow hardware incidents, collected from large-scale cluster deployments in 14 institutions. …
fail-slow hardware incidents, collected from large-scale cluster deployments in 14 institutions. …
Lung nodule detection in CT images using a raw patch-based convolutional neural network
Q Wang, F Shen, L Shen, J Huang, W Sheng - Journal of digital imaging, 2019 - Springer
Remarkable progress has been made in image classification and segmentation, due to the
recent study of deep convolutional neural networks (CNNs). To solve the similar problem of …
recent study of deep convolutional neural networks (CNNs). To solve the similar problem of …
Priority branches for ship detection in optical remote sensing images
Y Zhang, W Sheng, J Jiang, N Jing, Q Wang, Z Mao - Remote Sensing, 2020 - mdpi.com
Much attention is being paid to using high-performance convolutional neural networks (CNNs)
in the area of ship detection in optical remoting sensing (ORS) images. However, the …
in the area of ship detection in optical remoting sensing (ORS) images. However, the …
An efficient CNN accelerator using inter-frame data reuse of videos on FPGAs
S Li, Q Wang, J Jiang, W Sheng… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Convolutional neural networks (CNNs) have had great success when applied to computer
vision technology, and many application-specific integrated circuit (ASIC) and field-…
vision technology, and many application-specific integrated circuit (ASIC) and field-…
A new cellular-based redundant TSV structure for clustered faults
…, Z Liu, J Jiang, N Jing, W Sheng - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the
quality of through-silicon vias (TSVs) varies during the fabrication and bonding process, …
quality of through-silicon vias (TSVs) varies during the fabrication and bonding process, …
Pareto optimal temporal partition methodology for reconfigurable architectures based on multi-objective genetic algorithm
W Sheng, W He, J Jiang, Z Mao - 2012 IEEE 26th International …, 2012 - ieeexplore.ieee.org
A pare to optimal temporal partition methodology was developed for splitting and mapping
large data flow graph (DFG) to the coarse-grained reconfigurable architecture (CGRA). A multi…
large data flow graph (DFG) to the coarse-grained reconfigurable architecture (CGRA). A multi…