Reduced instruction set computer: Difference between revisions

A 32-bit version of the 801 was eventually produced in a single-chip form as the [[IBM ROMP]] in 1981, which stood for 'Research OPD [Office Products Division] Micro Processor'.<ref>{{cite book |first1=Jurij |last1=Šilc |first2=Borut |last2=Robič |first3=Theo |last3=Ungerer |title=Processor architecture: from dataflow to superscalar and beyond |year=1999 |isbn=3-540-64798-8 |pages=[https://archive.org/details/processorarchite00ilcd/page/n52 33] |publisher=Springer |url=https://archive.org/details/processorarchite00ilcd|url-access=limited}}</ref> This CPU was designed for "mini" tasks, and found use in peripheral interfaces and [[channel controller]]s on later IBM computers. It was also used as the CPU in the [[IBM RT PC]] in 1986, which turned out to be a commercial failure.<ref name=Gov239 /> Although the 801 did not see widespread use in its original form, it inspired many research projects, including ones at IBM that would eventually lead to the [[IBM POWER architecture]].<ref name=Jari40 >{{cite book |first=Jari |last=Nurmi |title=Processor design: system-on-chip computing for ASICs and FPGAs |year=2007 |isbn=978-1-4020-5529-4 |pages=[https://archive.org/details/processordesigns00nurm/page/n56 40]–43 |publisher=Springer |url=https://archive.org/details/processordesigns00nurm|url-access=limited}}</ref><ref>{{cite book |first1=Mark Donald |last1=Hill |first2=Norman Paul |last2=Jouppi |author-link2=Norman Jouppi|first3=Gurindar |last3=Sohi |title=Readings in computer architecture |year=1999 |isbn=1-55860-539-8 |pages=252–4|publisher=Gulf Professional }}</ref>

 

By the late 1970s, the 801 had become well-known in the industry. This coincided with new fabrication techniques that were allowing more complex chips to come to market. The [[Zilog Z80]] of 1976 had 8,000 transistors, whereas the 1979 [[Motorola 68000]] (68k) had 68,000. These newer designs generally used their newfound complexity to expand the instruction set to make it more orthogonal. Most, like the 68k, used [[microcode]] to do this, reading instructions and re-implementing them as a sequence of simpler internal instructions. In the 68k, a full {{frac|3}} of the transistors were used for this microcoding.<ref>{{cite magazine |magazine=Byte |date=May 1983 |title= Design Philosophy Behind Motorola's MC68000 |url=http://www.easy68k.com/paulrsm/doc/dpbm68k2.htm |first= Thomas |last=Starnes |page=Photo 1}}</ref>

 

Competition between RISC and conventional CISC approaches was also the subject of theoretical analysis in the early 1980s, leading, for example, to the [[iron law of processor performance]].

 

===Commercial breakout===

In the early 1980s, significant uncertainties surrounded the RISC concept. One concern involved the use of memory; a single instruction from a traditional processor like the Motorola 68k may be written out as perhaps a half dozen of the simpler RISC instructions. In theory, this could slow the system down as it spent more time fetching instructions from memory. But by the mid-1980s, the concepts had matured enough to be seen as commercially viable.<ref name=Gov239 >''Funding a Revolution: Government Support for Computing Research'' by Committee on Innovations in Computing and Communications 1999 {{ISBN|0-309-06278-0}} page 239</ref><ref name=mipsx />

Commercial RISC designs began to emerge in the mid-1980s. The [[ARM architecture family#ARM1|Acorn ARM1]] appeared in April 1985,<ref>{{cite journal | title = Speciation through entrepreneurial spin-off: The Acorn-ARM story | journal = Research Policy | date = March 2008 | first = Elizabeth | last = Garnsey | author2= Lorenzoni, Gianni|author3= Ferriani, Simone | volume = 37 | issue = 2 | url = http://www2.sa.unibo.it/~simone.ferriani/Download/Speciation%20through%20Entrepreneurial%20Spin-off.pdf | access-date = 2011-06-02 | quote = [...] the first silicon was run on April 26th 1985. | doi=10.1016/j.respol.2007.11.006 | pages=210–224| s2cid = 73520408 }}</ref> MIPS R2000 appeared in January 1986, followed shortly thereafter by [[Hewlett-Packard]]'s [[PA-RISC]] in some of their computers.<ref name=Gov239 /> In the meantime, the Berkeley effort had become so well known that it eventually became the name for the entire concept. In 1987 [[Sun Microsystems]] began shipping systems with the [[SPARC]] processor, directly based on the Berkeley RISC-II system.<ref name=Gov239 /><ref>{{cite book |first=Allen B. |last=Tucker |title=Computer science handbook |year=2004 |isbn=1-58488-360-X |pages=[https://archive.org/details/computersciencee00tuck/page/n1244 100]–6 |publisher=Taylor & Francis |url=https://archive.org/details/computersciencee00tuck|url-access=limited}}</ref> The US government Committee on Innovations in Computing and Communications credits the acceptance of the viability of the RISC concept to the success of the SPARC system.<ref name=Gov239 /> The success of SPARC renewed interest within IBM, which released new RISC systems by 1990 and by 1995 RISC processors were the foundation of a $15&nbsp;billion server industry.<ref name=Gov239 />

 

By the later 1980s, the new RISC designs were easily outperforming all traditional designs by a wide margin. At that point, all of the other vendors began RISC efforts of their own. Among these were the [[DEC Alpha]], [[AMD Am29000]], [[Intel i860]] and [[Intel i960|i960]], [[Motorola 88000]], [[IBM Power microprocessors|IBM POWER]], and, slightly later, the IBM/Apple/Motorola [[PowerPC]]. Many of these have since disappeared due to them often offering no competitive advantage over others of the same era. Those that remain are often used only in niche markets or as parts of other systems; of the designs from these traditional vendors, only SPARC and POWER have any significant remaining market.{{citation needed|reason=This is probably true but needs substantiating.|date=March 2023}}

 

==Characteristics and design philosophy==

{{More citations needed section|date=March 2012}}

By the beginning of the 21st century, the majority of low-end and mobile systems relied on RISC architectures.<ref>{{harvnb|Dandamudi|2005|pp=121–123}}</ref> Examples include:

* IBM's PowerPC was used in the [[GameCube]], [[Wii]], [[PlayStation 3]], [[Xbox 360]] and [[Wii U]] gaming consoles.

* The [[MIPS architecture|MIPS]] line (at one point used in many [[Silicon Graphics|SGI]] computers) was used in the [[PlayStation (console)|PlayStation]], [[PlayStation 2]], [[Nintendo 64]], [[PlayStation Portable]] game consoles, and [[residential gateway]]s like [[Linksys WRT54G series]].

* [[Hitachi, Ltd.|Hitachi]]'s [[SuperH]], originally in wide use in the [[Sega]] [[32X|Super 32X]], [[Sega Saturn|Saturn]] and [[Dreamcast]], now developed and sold by [[Renesas]] as the [[SuperH|SH4]].

* [[Atmel AVR]], used in a variety of products ranging from [[Xbox (console)|Xbox]] handheld controllers and the [[Arduino]] open-source microcontroller platform to [[BMW]] cars.

 

===Desktop and laptop computers===

* [[Hewlett-Packard]]'s [[PA-RISC]], also known as HP-PA (discontinued at the end of 2008).

* [[DEC Alpha|Alpha]], used in [[single-board computer]]s, workstations, servers and supercomputers from [[Digital Equipment Corporation]], then [[Compaq]] and finally [[Hewlett-Packard]] (HP)(discontinued as of 2007).

 

RISC architectures have become popular in [[Open-source hardware|open source processors]] and [[soft microprocessor]]s since they are relatively simple to implement, which makes them suitable for [[FPGA]] implementations and prototyping, for instance. Examples include:

 

* [[OpenRISC]], an open instruction set and micro-architecture first introduced in 2000.

* [[Libre-SOC]], an open source [[System on chip|SoC]] based on the [[Power ISA]] with extensions for video and 3D graphics.

 

==Awards==