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| image = DEC PDP-10 (from ca. 1970 named decsystem-10) mainframe computer system, 1970s (edited, white background).jpg
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| caption = Working DEC KI-10 System at Living Computers: Museum + Labs
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|website=definitions.net |quote=The PDP-10 was a mainframe computer family manufactured ... the cancellation of the PDP-10 line was announced in 1983.}}</ref> 1970s models and beyond were marketed under the DECsystem-10 name, especially as the [[TOPS-10]] operating system became widely used.{{efn|The TOPS-10 name was announced 1970}}
The PDP-10's architecture is almost identical to that of DEC's earlier [[PDP-6]], sharing the same [[36-bit]] [[Word (computer architecture)|word]] length and slightly extending the instruction set.
The PDP-10 was found in many university computing facilities and research labs during the 1970s, the most notable being [[Harvard University]]'s Aiken Computation Laboratory, [[Massachusetts Institute of Technology|MIT]]'s [[MIT Computer Science and Artificial Intelligence Laboratory#LCS and AI Lab|AI Lab]] and [[MIT Computer Science and Artificial Intelligence Laboratory#Project MAC|Project MAC]], [[Stanford University|Stanford]]'s [[Stanford AI Lab|SAIL]], [[Computer Center Corporation]] (CCC), [[ETH]] (ZIR), and [[Carnegie Mellon University]]. Its main [[operating system]]s, TOPS-10 and [[TENEX (operating system)|TENEX]], were used to build out the early [[ARPANET]]. For these reasons, the PDP-10 looms large in early [[Hacker culture|hacker folklore]].
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===KA10===
The KA10 has a maximum main memory capacity (both virtual and physical) of 256 [[kiloword]]s (equivalent to 1152 [[kilobyte]]s); the minimum main memory required is 16 kilowords. As supplied by DEC, it did not include [[paging]] hardware; [[memory management]] consists of two sets of protection and relocation registers, called ''[[base and bounds]]'' registers. This allows each half of a user's [[address space]] to be limited to a set section of [[main memory]], designated by the base physical address and size. This allows the model of separate read-only shareable code segment (normally the high segment) and [[read-write]] data/[[Stack (data structure)|stack]] segment (normally the low segment) used by [[TOPS-10]] and later adopted by [[Unix]]. Some KA10 machines, first at MIT, and later at [[BBN Technologies|Bolt, Beranek and Newman]] (BBN), were modified to add [[virtual memory]]<ref>{{cite web |url=http://bitsavers.org/pdf/bbn/pager/Technical_Details_of_the_BBN_Pager_Model_701_197007.pdf |title=Technical Details of the BBN Pager Model 701 |first1=Theodore R. |last1=Strollo |first2=Jerry D. |last2=Burchflel |first3=Raymond S. |last3=Tomlinson |author3-link=Ray Tomlinson |date=July 22, 1970 |publisher=[[BBN Technologies|Bolt, Beranek and Newman]]}}</ref><ref>{{cite web |title=A Virtual Memory System for the PDP-10 KA10 Processor
|url=https://apps.dtic.mil/sti/citations/ADA028987
|last=McNamee |first=L. P. |date=1976}}</ref> and support for [[demand paging]],<ref>{{cite journal |title=TENEX, a Paged Time Sharing System for the PDP-10
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===KL10===
[[File:PDP-10 1090.jpg|thumb|KL10-DA 1090 [[CPU]] and 6 Memory Modules]]
The original KL10 PDP-10 (also marketed as DECsystem-10) models (1080, 1088, etc.) use the original PDP-10 memory bus, with external memory modules. Module in this context meant a cabinet, dimensions roughly (WxHxD) 30 x 75 x 30 in. with a capacity of 32 to 256 kWords of [[magnetic
====Model B====
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* TU30 Magnetic Tape Transport – 75 ips (inches/second)
* TU45 Magnetic Tape Transport – 75 ips (inches/second)
A mix of up to eight of these could be supported, using [[7
The TM10 Magtape controller was available in two submodels:
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|}
There are 16 general-purpose, 36-bit registers. The right half of these registers (other than register 0) may be used for indexing. A few instructions operate on pairs of registers. The "PC Word" register is split in half; the right 18
In the original KA-10 systems, these registers are simply the first 16 words of [[main memory]]. The "fast registers" hardware option implements them as registers in the CPU, still addressable as the first 16 words of memory. Some software takes advantage of this by using the registers as an [[CPU cache|instruction cache]] by loading code into the registers and then jumping to the appropriate address; this is used, for example, in [[Maclisp]] to implement one version of the [[Garbage collection (computer science)|garbage collector]].<ref>{{cite web |url=http://www.paulgraham.com/thist.html|title=History of T|first=Olin|last=Shivers|access-date=October 25, 2019|quote=Maclisp on the -10 had used a mark&sweep GC (one version of which famously "ran in the register set," though that is another story)}}</ref> Later models all have registers in the CPU.
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Instructions are stored in 36-bit words. There are two formats, general instructions and [[input/output]] instructions.{{sfn|Programming|1970|p=13}}
In general instructions, the leftmost 9 bits, 0 to 8, contain an instruction [[opcode]]. Many of the possible 512 codes are not defined in the base model machines and are reserved for expansion like the addition of a hardware [[floating point unit]]. Following the opcode in bits 9 to 12 is the number of a register which will be used for the instruction. The input/output instructions all start with bits 0 through
In both formats, bits 13 through 35 are used to form the "effective address", E. Bits 18 through 35 contain a numerical constant address, Y. This address may be modified by adding the 18-bit value in a register, X, the register number indicated in bits 14 to 17. If these are set to zero, no indexing is used, meaning register 0 cannot be used for indexing. Bit 13, I, indicates indirection, meaning the ultimate effective address used by the instruction is not E, but the address stored in memory location E. When using indirection, the data in word E is interpreted in the same way as the layout of the instruction; bits 0 to 12 are ignored, and 13 through 35 form I, X and Y as above.
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The conditional jump operations examine register contents and jump to a given location depending on the result of the comparison. The mnemonics for these instructions all start with JUMP, JUMPA meaning "jump always" and JUMP meaning "jump never" – as a consequence of the symmetric design of the instruction set, it contains several no-ops such as JUMP. For example, JUMPN A,LOC jumps to the address LOC if the contents of register A is non-zero. There are also conditional jumps based on the processor's condition register using the JRST instruction. On the KA10 and KI10, JRST is faster than JUMPA, so the standard unconditional jump is JRST.
The conditional skip operations compare register and memory contents and skip the next instruction (which is often an unconditional jump) depending on the result of the comparison. A simple example is CAMN A,LOC which compares the contents of register A with the contents of location LOC and skips the next instruction if they are not equal. A more elaborate example is TLCE A,LOC (read "Test Left Complement, skip if Equal"), which using the contents of LOC as a mask, selects the corresponding bits in the left half of register A. If all those bits are ''E''qual to zero, skip the next instruction; and in any case, replace those bits by their
Some smaller instruction classes include the shift/rotate instructions and the procedure call instructions. Particularly notable are the stack instructions PUSH and POP, and the corresponding stack call instructions PUSHJ and POPJ. The byte instructions use a special format of indirect word to extract and store arbitrary-sized bit fields, possibly advancing a pointer to the next unit.{{efn|cf. {{section link|Byte addressing|Hybrid systems}}}}
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The PDP-10 does not use [[Memory-mapped I/O and port-mapped I/O|memory-mapped devices]], in contrast to the [[PDP-11]] and later DEC machines. A separate set of instructions is used to move data to and from devices defined by a device number in the instruction. Bits 3 to 9 contain the device number, with the 7 bits allowing a total of 128 devices. Instructions allow for the movement of data to and from devices in word-at-a-time (DATAO and DATAI) or block-at-a-time (BLKO, BLKI).{{sfn|Programming|1970|pp=87-88}}
In block mode, the value pointed to by E is a word in memory that is split in two, the
The final set of I/O instructions are used to write and read condition codes on the device, CONO and CONI.{{sfn|Programming|1970|p=86}} Additionally, CONSZ will perform a CONI, bitmask the retrieved data against the value in E, and then skip the next instruction if it is zero, used in a fashion similar to the BLK commands. Only the right 18 bits are tested in CONSZ.{{sfn|Programming|1970|p=87}}
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===Extended addressing===
In processors supporting extended addressing, the address space is divided into "sections". An 18-bit address is a "local address", containing an offset within a section, and a "global address" is 30 bits, divided into a 12-bit section number at the bottom of the
The process of calculating the effective address generates a 12-bit section number and an 18-bit offset within that segment.<ref name="referencemanual"/>{{rp|1-26–1-30}}
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|title=A Brief History of Hackerdom: The Early Hackers
|quote=MIT ... built their own operating system, the fabled .. Incompatible Timesharing System
|url=http://catb.org/esr/writings/hacker-history/hacker-history-3.html}}</ref> to run on their [[PDP-6]] (and later a modified PDP-10);
[[Tymshare]] developed [[Tymnet#Organization|TYMCOM-X]], derived from TOPS-10 but using a page-based file system like TOPS-20.<ref>{{
===Programming languages===
DEC maintained DECsystem-10 [[Fortran#FORTRAN IV|FORTRAN IV]] (F40) for the PDP-10 from 1967
MACRO-10 (assembly language macro compiler), COBOL, BASIC and AID were supported under the multi processing and swapping monitors.<ref>{{Cite web |last=Equipment |first=Digital |date=1968 |title=PDP-10 Reference Handbook |url=https://bitsavers.org/pdf/dec/pdp10/1970_PDP-10_Ref/1970PDP10Ref_Part0.pdf |website=bitsavers.org }}</ref>
In practice a number of other programming environments were available including LISP and SNOBOL at the Hatfield Polytechnic site around 1970.
== Clones ==
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The PDP-10 [[assembly language]] instructions LDB and DPB (load/deposit [[byte]]) live on as functions in the [[programming language]] [[Common Lisp]]. See [[Lisp (programming language)#References|the "References" section on the LISP article]]. The 36-bit word size of the PDP-6 and PDP-10 was influenced by the programming convenience of having 2 LISP pointers, each 18 bits, in one word.
[[Will Crowther]] created ''[[Colossal Cave Adventure|Adventure]]'', the prototypical computer adventure game, for a PDP-10. [[Don Daglow]] created the first computer [[baseball]] game (1971) and ''[[Dungeon (video game)|Dungeon]]'' (1975), the first [[role-playing video game]] on a PDP-10. [[Walter Bright]] originally created ''[[Empire (1977 video game)|Empire]]'' for the PDP-10. [[Roy Trubshaw]] and [[Richard Bartle]] created the first [[Multi-user dungeon|MUD]] on a PDP-10. ''[[Zork]]'' was written on the PDP-10. [[Infocom]] used PDP-10s for game development and testing.<ref>{{cite web |url=https://www.filfre.net/2012/01/zork-on-the-pdp-10 |title=Zork on the PDP-10 |quote=Infocom would develop Zork .. PDP-10 .. hosted .. Incompatible Timesharing System ... ARPANET ... DMG’s machine ... community .. a sort of extended beta-testing team}}</ref>
[[Bill Gates]] and [[Paul Allen]] originally wrote [[Altair BASIC]] using an [[Intel 8080]] simulator running on a PDP-10 at [[Harvard University]]. Allen repurposed the PDP-10 assembler as a [[cross assembler]] for the 8080 chip.<ref>{{Cite book |title=Idea Man: A Memoir by the Cofounder of Microsoft |last=Allen |first=Paul |publisher=Portfolio/Penguin |year=2012 |isbn=978-1-101-47645-1 |pages=74}}</ref> They founded [[Microsoft]] shortly after.
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===Sources===
{{Refbegin}}
* {{cite book
*[https://web.archive.org/web/20070831041149/https://www.computer.museum.uq.edu.au/pdf/DEC-10-XSRMA-A-D%20DECsystem10%20System%20Reference%20Manual.pdf ''DECsystem10 System Reference Manual'' (DEC, 1968, 1971, 1974)]▼
|title=DECsystem10 System Reference Manual
*[http://bitsavers.org/pdf/dec/pdp10/TOPS10_softwareNotebooks/vol05/AA-H391A-TK_DECsystem-10_DECSYSTEM-20_Processor_Reference_Jun1982.pdf ''DECsystem-10/DECSYSTEM-20 Processor Reference Manual'' (DEC, 1982)]▼
|publisher=DEC
|date=1974
▲
}}
* {{cite book
|title=DECsystem-10/DECSYSTEM-20 Processor Reference Manual
|publisher=DEC
|date=1982
▲
}}
* {{cite book
|title=Programming with the PDP-10 Instruction Set
|publisher=DEC
|date=1970
|url=http://www.bitsavers.org/pdf/dec/pdp10/1970_PDP-10_Ref/1970PDP10Ref_Part1.pdf
|ref=CITEREFProgramming1970
}}
* {{cite book
| last = Ceruzzi
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== Further reading ==
*[[C. Gordon Bell]], [[Alan Kotok]], Thomas N. Hastings, Richard Hill, "The Evolution of the DECsystem 10", ''Communications of the ACM'' '''21''':1:44 (January 1978) {{doi|10.1145/359327.359335}}, [http://research.microsoft.com/users/GBell/Computer_Engineering/00000511.htm reprint] in C. Gordon Bell, J. Craig Mudge, John E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design''
== External links ==
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