PDP-10: Difference between revisions

The PDP-10's architecture is almost identical to that of DEC's earlier [[PDP-6]], sharing the same [[36-bit]] [[Word (computer architecture)|word]] length and slightly extending the instruction set. (butThe withmain difference was a greatly improved hardware implementation). Some aspects of the [[instruction set]] are unusual, most notably the ''[[byte]]'' instructions, which operate on [[bit field]]s of any size from 1 to 36 bits inclusive, according to the general definition of a byte as ''a contiguous sequence of a fixed number of bits''.

The KA10 has a maximum main memory capacity (both virtual and physical) of 256 [[kiloword]]s (equivalent to 1152 [[kilobyte]]s); the minimum main memory required is 16 kilowords. As supplied by DEC, it did not include [[paging]] hardware; [[memory management]] consists of two sets of protection and relocation registers, called ''[[base and bounds]]'' registers. This allows each half of a user's [[address space]] to be limited to a set section of [[main memory]], designated by the base physical address and size. This allows the model of separate read-only shareable code segment (normally the high segment) and [[read-write]] data/[[Stack (data structure)|stack]] segment (normally the low segment) used by [[TOPS-10]] and later adopted by [[Unix]]. Some KA10 machines, first at MIT, and later at [[BBN Technologies|Bolt, Beranek and Newman]] (BBN), were modified to add [[virtual memory]]<ref>{{cite web |url=http://bitsavers.org/pdf/bbn/pager/Technical_Details_of_the_BBN_Pager_Model_701_197007.pdf |title=Technical Details of the BBN Pager Model 701 |first1=Theodore R. |last1=Strollo |first2=Jerry D. |last2=Burchflel |first3=Raymond S. |last3=Tomlinson |author3-link=Ray Tomlinson |date=July 22, 1970 |publisher=[[BBN Technologies|Bolt, Beranek and Newman]]}}</ref><ref>{{cite web |title=A Virtual Memory System for the PDP-10 KA10 Processor

The original KL10 PDP-10 (also marketed as DECsystem-10) models (1080, 1088, etc.) use the original PDP-10 memory bus, with external memory modules. Module in this context meant a cabinet, dimensions roughly (WxHxD) 30 x 75 x 30 in. with a capacity of 32 to 256 kWords of [[magnetic -core memory]]. The processors used in the [[DECSYSTEM-20]] (2040, 2050, 2060, 2065), commonly but incorrectly called "KL20", use internal memory, mounted in the same cabinet as the [[Central processing unit|CPU]]. The 10xx models also have different packaging; they come in the original tall PDP-10 cabinets, rather than the short ones used later on for the DECSYSTEM-20. The differences between the 10xx and 20xx models were primarily which operating system they ran, either TOPS-10 or [[TOPS-20]]. Apart from that, differences are more cosmetic than real; some 10xx systems have "20-style" internal memory and I/O, and some 20xx systems have "10-style" external memory and an I/O bus. In particular, all ARPAnet TOPS-20 systems had an I/O bus because the AN20 [[Interface Message Processor|IMP]] interface was an I/O bus device. Both could run either TOPS-10 or TOPS-20 microcode and thus the corresponding operating system.

A mix of up to eight of these could be supported, using [[7 -track tape|seven-track]] or [[9 -track tape|nine-track]] devices. The TU20 and TU30 each came in A (9-track) and B (7-track) versions, and all of the aforementioned tape drives could read/write from/to 200 [[Bits Per Inch|BPI]], 556 BPI and 800 BPI IBM-compatible tapes.

There are 16 general-purpose, 36-bit registers. The right half of these registers (other than register 0) may be used for indexing. A few instructions operate on pairs of registers. The "PC Word" register is split in half; the right 18- bits contains the [[program counter]] and the left 13- bits contains the [[status register|processor status flag]]s, with five zeros between the two sections. The condition register bits, which record the results of arithmetic operations (''e.g.'' overflow), can be accessed by only a few instructions.

In general instructions, the leftmost 9 bits, 0 to 8, contain an instruction [[opcode]]. Many of the possible 512 codes are not defined in the base model machines and are reserved for expansion like the addition of a hardware [[floating point unit]]. Following the opcode in bits 9 to 12 is the number of a register which will be used for the instruction. The input/output instructions all start with bits 0 through 32 being set to 1 (decimal value 7), bits 3 through 9 containing a device number, and 10 through 12 the instruction opcode.{{sfn|Programming|1970|p=13}}

The conditional skip operations compare register and memory contents and skip the next instruction (which is often an unconditional jump) depending on the result of the comparison. A simple example is CAMN A,LOC which compares the contents of register A with the contents of location LOC and skips the next instruction if they are not equal. A more elaborate example is TLCE A,LOC (read "Test Left Complement, skip if Equal"), which using the contents of LOC as a mask, selects the corresponding bits in the left half of register A. If all those bits are ''E''qual to zero, skip the next instruction; and in any case, replace those bits by their booleanBoolean complement.

In block mode, the value pointed to by E is a word in memory that is split in two, the upperright 18- bits (right half of the word) indicate a starting address in memory where the data is located (or written into) and the lowerleft 18 bits are a counter. The block instructions increment both values every time they are called, thereby increasing the counter as well as moving to the next location in memory. It then performs a DATAO or DATAI. Finally, it checks the counter side of the value at E, if it is non-zero, it skips the next instruction. If it is zero, it performs the next instruction, normally a JUMP back to the top of the loop.{{sfn|Programming|1970|p=88}} The BLK instructions are effectively small programs that loop over a DATA and increment instructions, but by having this implemented in the processor itself, it avoids the need to repeatedly read the series of instructions from main memory and thus performs the loop much more rapidly.{{sfn|Programming|1970|p=89}}

In processors supporting extended addressing, the address space is divided into "sections". An 18-bit address is a "local address", containing an offset within a section, and a "global address" is 30 bits, divided into a 12-bit section number at the bottom of the upperleft 18 bits and an 18-bit offset within that section in the lowerright 18 bits. A register can contain either a "local index", with an 18-bit unsigned displacement or local address in the lowerright 18 bits, or a "global index", with a 30-bit unsigned displacement or global address in the lowerright 30 bits. An indirect word can either be a "local indirect word", with its uppermost bit set, the next 12 bits reserved, and the remaining bits being an indirect bit, a 4-bit register code, and an 18-bit displacement, or a "global indirect word", with its uppermost bit clear, the next bit being an indirect bit, the next 4 bits being a register code, and the remaining 30 bits being a displacement.<ref name=referencemanual>{{cite web |title=DECsystem-10/DECSYSTEM-20 Processor Reference Manual|id=AA-H391A-TK, AD-H391A-T1|url=http://www.36bit.org/dec/manual/ad-h391a-t1.pdf |publisher=Digital Equipment Corporation |date=June 1982 |access-date=November 14, 2015 |url-status=dead |archive-url=https://web.archive.org/web/20151011152807/http://www.36bit.org/dec/manual/ad-h391a-t1.pdf |archive-date=October 11, 2015}}</ref>{{rp|1-26&ndash;1-30}}

|url=http://catb.org/esr/writings/hacker-history/hacker-history-3.html}}</ref> to run on their [[PDP-6]] (and later a modified PDP-10);<ref>{{cite web citation needed|websitedate=gunkies.org (Computer HistoryAugust Wiki)2023}}

[[Tymshare]] developed [[Tymnet#Organization|TYMCOM-X]], derived from TOPS-10 but using a page-based file system like TOPS-20.<ref>{{citeCite web |websitetitle=Gunkies.orgTymshare (Computer History Wiki)Software |url=http://gunkiesinwap.orgcom/wikipdp10/tymshare/software/TYMCOM-X |titleaccess-date=TYMCOM2023-X09-24 |website=inwap.com}}</ref>

DEC maintained DECsystem-10 [[Fortran#FORTRAN IV|FORTRAN IV]] (F40) for the PDP-10 from 1967- to 1975<ref>{{cite web |last1=Digital Equipment Corp |title=DECsystem-10 FORTRAN IV (F40) Programmers Reference Manual |url=https://github.com/PDP-10/f40/blob/master/doc/DEC-10-LFLMA-B-D%20FORTRAN%20IV%20(F40)%20Programmer's%20Reference%20Manual.pdf |website=Github |publisher=Digital Equipment Corporation |access-date=15 April 2022}}</ref>

[[Will Crowther]] created ''[[Colossal Cave Adventure|Adventure]]'', the prototypical computer adventure game, for a PDP-10. [[Don Daglow]] created the first computer [[baseball]] game (1971) and ''[[Dungeon (video game)|Dungeon]]'' (1975), the first [[role-playing video game]] on a PDP-10. [[Walter Bright]] originally created ''[[Empire (1977 video game)|Empire]]'' for the PDP-10. [[Roy Trubshaw]] and [[Richard Bartle]] created the first [[Multi-user dungeon|MUD]] on a PDP-10. ''[[Zork]]'' was written on the PDP-10. [[Infocom]] used PDP-10s for game development and testing.<ref>{{cite web |url=https://www.filfre.net/2012/01/zork-on-the-pdp-10 |title=Zork on the PDP-10 |quote=Infocom would develop Zork .. PDP-10 .. hosted .. Incompatible Timesharing System ... ARPANET ... DMG’s machine ... community .. a sort of extended beta-testing team}}</ref>

*[[C. Gordon Bell]], [[Alan Kotok]], Thomas N. Hastings, Richard Hill, "The Evolution of the DECsystem 10", ''Communications of the ACM'' '''21''':1:44 (January 1978) {{doi|10.1145/359327.359335}}, [http://research.microsoft.com/users/GBell/Computer_Engineering/00000511.htm reprint] in C. Gordon Bell, J. Craig Mudge, John E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design''] (Digital Press, 1978, {{isbn|0932376002}})