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{{short description|Intel processor family}}
{{Use American English|date=December 2022}}
{{use mdy dates|date=September 2022}}
{{About|the Intel microprocessor||Cannon Lake (disambiguation)}}
{{Infobox CPU
| name = Cannon Lake
| created = {{Start date and age|May 201815, (availability)2018}}
| produced-end = {{End date and age|February 28, 2020}}
| numcoressoldby = 2[[Intel]]
| manuf1 = Intel
| size-from = [[Intel]] [[10 nanometer|10  nm]] ([[FinFET|Tritri-Gategate]]) transistors
| clock = 3.2GHz2{{nbsp}}GHz
| l1cachenumcores = 64 KB per core2
| l2cachegpu = 256 KB per core = Factory disabled
| l3cachesock1 = 4 MB, shared = BGA 1440
| gpu pcode1 = Factory disabledCNL
| arch1brand1 = [[x86-64Intel Core|Core]]
| predecessor = Mobile: [[Coffee Lake]] (2nd optimization)<br>[[Kaby Lake Refresh]] (2nd optimization)
| instructions = [[x86-64]], [[Intel 64]]
| successor = [[Ice Lake (microprocessor)|Ice Lake]] (architecture)
| extensions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[FMA instruction set|FMA3]]
| microarch = Palm Cove
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| support status = Legacy support for iGPU
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2#Advanced Vector Extensions 2|AVX2]], [[AVX-512]], [[Intel SHA extensions|SHA]],<ref name=":0">{{cite web |title=Intel Cannonlake Added To LLVM’s Clang – AVX-512 |url=http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |first=Nathan |last=Kirsch |work=Legit Reviews |date=2016-02-21 |access-date=2016-10-23 |archive-url=https://web.archive.org/web/20161023135525/http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |archive-date=2016-10-23 |url-status=dead }}</ref> [[Trusted Execution Technology|TXT]], [[Transactional Synchronization Extensions|TSX]], [[Software Guard Extensions|SGX]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| predecessor = Desktop: [[Coffee Lake]] (2nd optimization)<br>[[Kaby Lake Refresh]] (2nd optimization)
| successor = [[Ice Lake (microprocessor)|Ice Lake]] (Architecture)
|microarch=[[Palm Cove (microarchitecture)|Palm Cove]]
}}
'''Cannon Lake''' is [[list of Intel codenames|Intel's codename]] for the 8th generation of [[Intel Core|Core]] processors based on Palm Cove, a [[10 nm process|10 nm]] [[die shrink]] of the [[Kaby Lake]] [[microarchitecture]]. As a die shrink, Palm Cove is a new ''process'' in Intel's [[Process–architecture–optimization_model|process-architecture-optimization]] execution plan as the next step in semiconductor fabrication.<ref name="wccftech">{{Cite web |last=Mujtaba |first=Hassan |date=June 6, 2014 |title=Intel's Cannonlake 10nm Microarchitecture is Due For 2016 - Compatible On Union Bay With Union Point PCH |url=http://wccftech.com/intels-cannonlake-10nm-microarchitecture-due-2016-compatible-union-bay-union-point-pch/ |work=Wccftech |language=en-US |access-date=September 24, 2014}}</ref> Cannon Lake CPUs are the first mainstream CPUs to include the [[AVX-512]] instruction set.
 
Prior to Cannon Lake's launch, Intel launched another 14&nbsp;nm process refinement with the codename [[Coffee Lake]].<ref>{{Cite news |last=Carey |first=Gabe |date=May 13, 2019 |title=Intel Coffee Lake release date, news and features |url=http://www.techradar.com/news/intel-coffee-lake-release-date-news-and-rumors |work=TechRadar |language=en-US |access-date=December 15, 2022}}</ref>
'''Cannon Lake''' (formerly '''Skymont''') is [[List of Intel codenames|Intel's codename]] for the [[10 nanometer|10-nanometer]] [[die shrink]] of the [[Kaby Lake]] [[microarchitecture]]. As a die shrink, Cannon Lake is a new process in Intel's "[[Intel Tick-Tock|Process-Architecture-Optimization]]" execution plan as the next step in semiconductor fabrication.<ref name="wccftech">{{ cite web | url=http://wccftech.com/intels-cannonlake-10nm-microarchitecture-due-2016-compatible-union-bay-union-point-pch/ | title=Intel's Cannonlake 10nm Microarchitecture is Due For 2016 - Compatible On Union Bay With Union Point PCH | work=WCCFTech | access-date=24 September 2014 | date=2014-06-06 }}</ref> Cannon Lake CPUs are the first mainstream CPUs to include the [[AVX-512]] instruction set.
 
The successor of Cannon Lake is [[Ice Lake (microarchitecture)|Ice Lake]], powered by the [[Sunny Cove (microarchitecture)|Sunny Cove microarchitecture]], which represents the ''architecture'' phase in the ''process-architecture-optimization'' model.<ref>{{Cite news |last=Bourque |first=Brad |date=January 25, 2016 |title=Intel's Kaby Lake will sneak in before the 10nm process |url=http://www.digitaltrends.com/computing/intels-lead-in-processor-tech-is-dwindling-according-to-investor-report/ |website=Digital Trends |language=en-US |access-date=February 1, 2016}}</ref><ref>{{cite news |last=Eassa |first=Ashraf |date=January 25, 2016 |title=What's the Name of Intel's Third 10-Nanometer Chip? |url=http://www.fool.com/investing/general/2016/01/18/what-is-the-name-of-intels-third-10-nanometer-chip.aspx |website=The Motley Fool |access-date=February 1, 2016 |archive-url=https://web.archive.org/web/20160518003820/http://www.fool.com/investing/general/2016/01/18/what-is-the-name-of-intels-third-10-nanometer-chip.aspx |archive-date=May 18, 2016 |url-status=dead}}</ref>
Prior to Cannon Lake's launch, Intel launched another 14&nbsp;nm process refinement with the codename [[Coffee Lake]].<ref>{{Cite news|url=http://www.techradar.com/news/intel-coffee-lake-release-date-news-and-rumors|title=Intel Coffee Lake release date, news and features|date=2017-08-09|work=Tech Radar|language=en-US}}</ref>
 
== Design history and features ==
The successor of Cannon Lake is [[Ice Lake (microarchitecture)|Ice Lake]], powered by the [[Sunny Cove (microarchitecture)|Sunny Cove microarchitecture]], which represents the "Architecture" phase in the [[Process-Architecture-Optimization model|Intel Process-Architecture-Optimization Model]].<ref>{{cite news|url=http://www.digitaltrends.com/computing/intels-lead-in-processor-tech-is-dwindling-according-to-investor-report/|title=Intel's Kaby Lake will sneak in before the 10nm process|date=25 Jan 2016|publisher=Digital Trends|access-date=2016-02-01}}</ref><ref>{{cite news|url=http://www.fool.com/investing/general/2016/01/18/what-is-the-name-of-intels-third-10-nanometer-chip.aspx|title=What's the Name of Intel's Third 10-Nanometer Chip?|date=25 Jan 2016|publisher=The Motley Fool|access-date=2016-02-01|archive-url=https://web.archive.org/web/20160518003820/http://www.fool.com/investing/general/2016/01/18/what-is-the-name-of-intels-third-10-nanometer-chip.aspx|archive-date=18 May 2016|url-status=dead}}</ref>
 
==Design history and features==
{{Infobox CPU
| name = Palm Cove
| image =
| image_size =
| alt =
| caption =
<!----------------- General Info ----------------->
| designfirm = Intel
| produced-start = May 2018
| cpuid =
| produced-end = February 28, 2020
| code =
| soldby = [[Intel]]
| designfirm = Intel
| manuf1 = Intel
| cpuid =
| code =
<!----------------- Performance ------------------>
| slowest =
| fastest =
| slow-unit =
| fast-unit =
| fsb-slowest =
| fsb-fastest =
| fsb-slow-unit =
| fsb-fast-unit =
| hypertransport-slowest =
| hypertransport-fastest =
| hypertransport-slow-unit =
| hypertransport-fast-unit =
| qpi-slowest =
| qpi-fastest =
| qpi-slow-unit =
| qpi-fast-unit =
| dmi-slowest =
| dmi-fastest =
| dmi-slow-unit =
| dmi-fast-unit =
| data-width =
| address-width =
| virtual-width =
<!-------------------- Cache --------------------->
| l1cache = 64 {{nbsp}}KB per core
| l2cache = 256 {{nbsp}}KB per core
| l3cache = 4 = 2{{nbsp}}MB, sharedper core
| arch = [[x86-64]]
| l4cache =
| instructions = x86-64, [[Intel 64]]
| llcache =
| extensions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[FMA instruction set|FMA3]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2#Advanced Vector Extensions 2|AVX2]], [[AVX-512]], [[Intel SHA extensions|SHA]],<ref name=":0">{{cite web |last=Kirsch |first=Nathan |date=February 21, 2016 |title=Intel Cannonlake Added To LLVM's Clang – AVX-512 |url=http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |work=Legit Reviews |access-date=October 23, 2016 |archive-url=https://web.archive.org/web/20161023135525/http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |archive-date=2016-10-23 |url-status=dead}}</ref> [[Trusted Execution Technology|TXT]], [[Transactional Synchronization Extensions|TSX]], [[Software Guard Extensions|SGX]], [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
<!------- Architecture and classification -------->
| predecessor = [[Skylake (microarchitecture)|Skylake]]
| application =
| successor = [[Sunny Cove (microarchitecture)|Sunny Cove]]
| size-from =
| size-to =
| arch1 = [[x86-64]]
| microarch =
| arch = [[x86-64]]
| instructions =
| extensions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[FMA instruction set|FMA3]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions1 = [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]]
| extensions2 = [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2#Advanced Vector Extensions 2|AVX2]], [[AVX-512]], [[Intel SHA extensions|SHA]],<ref>{{cite web |title=Intel Cannonlake Added To LLVM’s Clang – AVX-512 |url=http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |first=Nathan |last=Kirsch |work=Legit Reviews |date=2016-02-21 |access-date=2016-10-23 |archive-url=https://web.archive.org/web/20161023135525/http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |archive-date=2016-10-23 |url-status=dead }}</ref> [[Trusted Execution Technology|TXT]], [[Transactional Synchronization Extensions|TSX]], [[Software Guard Extensions|SGX]]
| extensions3 = [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
<!----------- Physical specifications ------------>
| transistors =
| numcores =
| gpu =
| co-processor =
| pack1 =
| sock1 =
<!--------- Products, models, variants ----------->
| core1 =
| pcode1 =
| model1 =
| brand1 =
| variant =
<!------------------ History ------------------->
| predecessor = [[Skylake (microarchitecture)|Skylake]]
| successor = [[Sunny Cove (microarchitecture)|Sunny Cove]]
}}
[[File:Intel@10nm@CannonLake@PalmCoveCores - GT2-Gen10 IGP RadeonRX540@Core i3-8121U@NUC8I3CYSM DSCx13 [email protected]|thumb|Cannon Lake processor die from an i3-8121U with Palm Cove cores]]
Cannon Lake was initially expected to be released in 2015<ref>{{Cite web |last=Shilov |first=Anton |date=February 16, 2018 |title=Intel's 10nm Briefly Appears: Dual Core Cannon Lake in Official Documents |url=https://www.anandtech.com/show/12436/intel-10nm-dualcore-cannon-lake |website=AnandTech |language=en-US |access-date=July 30, 2019}}</ref>/2016, but the release was pushed back to 2018.<ref>{{Cite news |title=Intel confirms tick-tock-shattering Kaby Lake processor as Moore's Law falters |url=https://arstechnica.com/gadgets/2015/07/intel-confirms-tick-tock-shattering-kaby-lake-processor-as-moores-law-falters/ |work=Ars Technica |language=en-US |date=July 16, 2015 |access-date=April 29, 2017}}</ref> Intel demonstrated a laptop with an unknown Cannon Lake CPU at CES 2017<ref>{{Cite web |last=Pressman |first=Aaron |date=January 5, 2017 |title=Here's How Intel Is Finally Getting Back on Track With Moore's Law |url=http://fortune.com/2017/01/05/intel-ces-2017-moore-law/ |website=Fortune |language=en-US |access-date=February 10, 2017}}</ref><ref>{{Cite news |title=Intel Kicks Off CES 2017 with VR, Automated Driving, 5G News and Experiences |url=https://newsroom.intel.com/news/brian-krzanich-2017-ces-news-conference/ |website=Intel Newsroom |language=en-US |date=January 4, 2017 |access-date=February 10, 2017}}</ref> and announced that Cannon Lake based products would be available in 2018 at the earliest.
 
At [[Consumer Electronics Show#2018|CES 2018]] Intel announced that it had started shipping mobile Cannon Lake CPUs at the end of 2017 and would ramp up production in 2018.<ref>{{Cite news |last=Cutress |first=Ian |date=January 9, 2018 |title=Intel Mentions 10nm, Briefly |url=https://www.anandtech.com/show/12271/intel-mentions-10nm-briefly |website=AnandTech |language=en-US |access-date=January 10, 2018}}</ref><ref>{{Cite news |date=January 9, 2018 |title=Intel Announces 10nm Cannon Lake Is Shipping |url=http://www.tomshardware.com/news/intel-ces-10nm-processor,36289.html |work=Tom's Hardware |language=en-US |access-date=January 10, 2018}}</ref><ref>{{Citation|last=AnandTech|title=Intel at CES 2018: 10nm [@8:35]|date=2018-01-09|url=https://www.youtube.com/watch?v=KoBfKooUDb0&t=515|access-date=2018-01-10}}</ref>
Cannon Lake was initially expected to be released in 2015<ref>{{Cite web|url=https://www.anandtech.com/show/12436/intel-10nm-dualcore-cannon-lake|title=Intel's 10nm Briefly Appears: Dual Core Cannon Lake in Official Documents|last=Shilov|first=Anton|website=www.anandtech.com|access-date=2019-07-30}}</ref>/2016, but the release was pushed back to 2018.<ref>{{Cite news|url=https://arstechnica.com/gadgets/2015/07/intel-confirms-tick-tock-shattering-kaby-lake-processor-as-moores-law-falters/|title=Intel confirms tick-tock-shattering Kaby Lake processor as Moore’s Law falters|work=Ars Technica|access-date=2017-04-29|language=en-us}}</ref> Intel demonstrated a laptop with an unknown Cannon Lake CPU at CES 2017<ref>{{Cite web|url=http://fortune.com/2017/01/05/intel-ces-2017-moore-law/|title=Here's How Intel Is Finally Getting Back on Track With Moore's Law|website=Fortune|access-date=2017-02-10}}</ref><ref>{{Cite news|url=https://newsroom.intel.com/news/brian-krzanich-2017-ces-news-conference/|title=Intel Kicks Off CES 2017 with VR, Automated Driving, 5G News and Experiences {{!}} Intel Newsroom|newspaper=Intel Newsroom|access-date=2017-02-10|language=en-US}}</ref> and announced that Cannon Lake based products would be available in 2018 at the earliest.
 
On April 26, 2018 in its report on first-quarter 2018 financial results, Intel stated it was currently shipping low-volume 10&nbsp;nm product and expects 10&nbsp;nm volume production to shift to 2019.<ref>{{Cite web |title=Intel Reports First-Quarter 2018 Financial Results |url=https://www.intc.com/investor-relations/investor-education-and-news/investor-news/press-release-details/2018/Intel-Reports-First-Quarter-2018-Financial-Results/ |website=www.intc.com |language=en-US |access-date=April 28, 2018}}</ref> In July 2018, Intel announced that volume production of Cannon Lake would be delayed yet again, to late Q2 2019.<ref>{{Cite news |last1=Novet |first1=Jordan |last2=Ell |first2=Kellie |date=July 26, 2018 |title=Intel falls on delay of future chip technology |url=https://www.cnbc.com/2018/07/26/intel-earnings-q2-2018.html |work=CNBC |language=en-US |access-date=July 29, 2018}}</ref>
At [[Consumer Electronics Show#2018|CES 2018]] Intel announced that it had started shipping mobile Cannon Lake CPUs at the end of 2017 and would ramp up production in 2018.<ref>{{Cite news|url=https://www.anandtech.com/show/12271/intel-mentions-10nm-briefly|title=Intel Mentions 10nm, Briefly|last=Cutress|first=Ian|access-date=2018-01-10}}</ref><ref>{{Cite news|url=http://www.tomshardware.com/news/intel-ces-10nm-processor,36289.html|title=Intel Announces 10nm Cannon Lake Is Shipping|date=2018-01-09|work=Tom's Hardware|access-date=2018-01-10|language=en}}</ref><ref>{{Citation|last=AnandTech|title=Intel at CES 2018: 10nm [@8:35]|date=2018-01-09|url=https://www.youtube.com/watch?v=KoBfKooUDb0&t=515|access-date=2018-01-10}}</ref>
 
The first laptop featuring a Cannon Lake CPU, namely Intel Core i3-8121U, a dual core CPU with Hyper-Threading and Turbo Boost but without an integrated GPU, was released in May 2018 in very limited quantities.<ref>{{Cite news |title=Cannon Lake stumbles into the market: The IdeaPad 330-15ICN is the first laptop with a 10-nm-CPU |url=https://www.notebookcheck.net/Cannon-Lake-stumbles-into-the-market-The-IdeaPad-330-15ICN-is-the-first-laptop-with-a-10-nm-CPU.303330.0.html |work=NotebookCheck |language=en-US |access-date=May 14, 2018}}</ref><ref>{{Cite web |title=联想IdeaPad330 八代酷睿I3-8121U游戏性能独显笔记本电脑 超薄本轻薄本办公商务学生本 标配秒杀：4G内存 500G硬盘 2G独显 W10 银色 15.6英寸【图片 价格 品牌 报价】-京东 |url=https://item.jd.com/26395831446.html |archive-url=https://web.archive.org/web/20180514184215/https://item.jd.com/26395831446.html |url-status=dead |archive-date=May 14, 2018 |language=zh |date=May 14, 2018 |access-date=May 14, 2018}}</ref>
On April 26, 2018 in its report on first-quarter 2018 financial results Intel stated it was currently shipping low-volume 10&nbsp;nm product and expects 10&nbsp;nm volume production to shift to 2019.<ref>{{Cite web|url=https://www.intc.com/investor-relations/investor-education-and-news/investor-news/press-release-details/2018/Intel-Reports-First-Quarter-2018-Financial-Results/|title=Intel Reports First-Quarter 2018 Financial Results|website=www.intc.com|language=en-US|access-date=2018-04-28}}</ref> In July 2018, Intel announced that volume production of Cannon Lake would be delayed yet again, to late Q2 2019.<ref>{{Cite news|url=https://www.cnbc.com/2018/07/26/intel-earnings-q2-2018.html|title=Intel falls on delay of future chip technology|last=Ell|first=Jordan Novet, Kellie|date=2018-07-26|work=CNBC|access-date=2018-07-29}}</ref>
 
On August 16, 2018 Intel announced two new models of [[Next Unit of Computing#Cannon Lake-U|NUCs]] would use the 10&nbsp;nm Cannon Lake-U i3-8121U CPU.<ref>{{Cite news |last=Paul |first=Ian |date=August 16, 2018 |title=Intel rolls out NUC mini-PCs with 10nm 'Cannon Lake' CPUs and AMD Radeon graphics |url=https://www.pcworld.com/article/3297974/computers/intel-nuc-10nm-cannon-lake-radeon-graphics.html |work=PCWorld |language=en-US |access-date=December 30, 2018}}</ref> These models later became more readily available at retail in late November 2018.
The first laptop featuring a Cannon Lake CPU, namely Intel Core i3-8121U, a dual core CPU with Hyper-Threading and Turbo Boost but without an integrated GPU, was released in May 2018 in very limited quantities.<ref>{{Cite news|url=https://www.notebookcheck.net/Cannon-Lake-stumbles-into-the-market-The-IdeaPad-330-15ICN-is-the-first-laptop-with-a-10-nm-CPU.303330.0.html|title=Cannon Lake stumbles into the market: The IdeaPad 330-15ICN is the first laptop with a 10-nm-CPU|work=Notebookcheck|access-date=2018-05-14|language=en}}</ref><ref>{{Cite web|url=https://item.jd.com/26395831446.html|archive-url=https://web.archive.org/web/20180514184215/https://item.jd.com/26395831446.html|url-status=dead|archive-date=2018-05-14|title=联想IdeaPad330 八代酷睿I3-8121U游戏性能独显笔记本电脑 超薄本轻薄本办公商务学生本 标配秒杀：4G内存 500G硬盘 2G独显 W10 银色 15.6英寸【图片 价格 品牌 报价】-京东|date=2018-05-14|access-date=2018-05-14}}</ref>
 
On October 28, 2019, Intel announced that it will be discontinuing the i3-8121U and the Cannon Lake-powered Crimson Canyon NUC, with orders being taken till December 27, and shipping till February 28, 2020,<ref>{{Cite news |last=Liu |first=Zhiye |date=October 31, 2019 |title=Intel discontinues Cannon Lake NUC |url=https://www.tomshardware.com/news/intel-fires-10nm-cannon-lake-nuc-into-oblivion |work=Tom's Hardware |language=en-US |access-date=November 11, 2019}}</ref><ref>{{cite web|url=https://qdms.intel.com/dm/i.aspx/83FA55FD-2ED4-4E81-B898-8826C70EEB5B/PCN117226-00.pdf|title=Product Change Notification Change Notification #: 117226 - 00|work=qdms.intel.com}}</ref> making Cannon Lake not only one of the shortest-lived microarchitectures of Intel, but also the shortest-lived 10&nbsp;nm x86 CPU microarchitecture (with only one CPU model to be released and manufactured for 1.5 years).
On August 16, 2018 Intel announced two new models of [[Next Unit of Computing#Cannon Lake-U|NUCs]] would use the 10&nbsp;nm Cannon Lake-U i3-8121U CPU.<ref>{{Cite news|url=https://www.pcworld.com/article/3297974/computers/intel-nuc-10nm-cannon-lake-radeon-graphics.html|title=Intel rolls out NUC mini-PCs with 10nm 'Cannon Lake' CPUs and AMD Radeon graphics|work=PC World|access-date=2018-12-30|language=en}}</ref> These models later became more readily available at retail in late November 2018.
 
In July 2021, Intel announced it would be removing support for Cannon Lake graphics in their [[Linux kernel]] driver, effective as of Linux 5.15, as no production Cannon Lake CPUs were shipped with graphics enabled; this removal resulted in a reduction of approximately 1,600 lines of code.<ref>{{Cite web |last=Larabel |first=Michael |date=July 24, 2021 |title=Intel To Finally Remove Cannon Lake Graphics Support From Their Linux Kernel Driver|url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-Drop-Cannon-Lake-i915 |website=Phoronix |language=en-US |access-date=October 27, 2021}}</ref><ref>{{Cite web |last=Larabel |first=Michael |date=August 11, 2021 |title=Intel Graphics Driver Queues More DG2 Code For Linux While Removing Cannon Lake |url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-Linux-5.15-DG2-CNL |website=Phoronix |language=en-US |access-date=October 27, 2021}}</ref>
On October 28, 2019, Intel announced that it will be discontinuing the i3-8121U and the Cannon Lake-powered Crimson Canyon NUC, with orders being taken till December 27, and shipping till February 28, 2020,<ref>{{Cite news|url=https://www.tomshardware.com/news/intel-fires-10nm-cannon-lake-nuc-into-oblivion|title=Intel discontinues Cannon Lake NUC|work=Tom's Hardware|access-date=2019-11-11|language=en}}</ref><ref>{{cite web|url=https://qdms.intel.com/dm/i.aspx/83FA55FD-2ED4-4E81-B898-8826C70EEB5B/PCN117226-00.pdf|title=Product Change Notification Change Notification #: 117226 - 00|work=qdms.intel.com}}</ref> making Cannon Lake not only one of the shortest-lived microarchitectures of Intel, but also the shortest-lived 10&nbsp;nm x86 CPU microarchitecture (with only one CPU model to be released and manufactured for 1.5 years).
 
In July 2021, Intel announced it would be removing support for Cannon Lake graphics in their [[Linux kernel]] driver, effective as of Linux 5.15, as no production Cannon Lake CPUs were shipped with graphics enabled; this removal resulted in a reduction of approximately 1,600 lines of code.<ref>{{Cite web|title=Intel To Finally Remove Cannon Lake Graphics Support From Their Linux Kernel Driver|last=Larabel|first=Michael|date=2021-07-24|access-date=2021-10-27|website=[[Phoronix]]|url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-Drop-Cannon-Lake-i915}}</ref><ref>{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-Linux-5.15-DG2-CNL|title=Intel Graphics Driver Queues More DG2 Code For Linux While Removing Cannon Lake|date=2021-08-11|access-date=2021-10-27|website=[[Phoronix]]|last=Larabel|first=Michael}}</ref>
 
=== Improvements ===
* Intel [[Palm Cove (microarchitecture)|Palm Cove]] CPU cores
** [[AVX-512]] instruction set extension
* Intel's first 10 nm process technology
 
== List of Cannon Lake CPUs ==
 
== Products ==
=== Mobile processors ===
==== Cannon Lake-U ====
{| class="wikitable sortable" style="text-align: center;" data-ve-attributes="{&quot;style&quot;:&quot;text-align: center;&quot;}"
Common features:
! rowspan="2" |Processor
* Socket: BGA 1440.
branding
* Memory support: [[DDR4]]-2400 or [[LPDDR4]]-2400 dual channel (maximum supported: 32 GB).
! rowspan="2" |Model
* PCIe support: 16 lanes of Gen3.
! rowspan="2" |Cores
{| class="wikitable sortable" style="text-align:center;" data-ve-attributes="{&quot;style&quot;:&quot;text-align:center;&quot;}"
(threads)
! rowspan="2" |CPU Processor <br/>branding
! rowspan="2" | Model
[[clock rate]]
! rowspan="2" |CPU [[IntelCores Turbo Boost|Turbo]]<br/>(threads)
! colspan="2" | CPU [[clock rate]]
! rowspan="2" | GPU
! rowspan="2" |L3 Smart <br/>cache
! rowspan="2" | TDP
cache
! [[cTDP]]
! rowspan="2" |TDP
! rowspan="2" | Price <br/>(USD)
![[cTDP]]
! rowspan="2" |Price
(USD)
|-
! Base
!Down
! [[Intel Turbo Boost|Turbo]]
! Down
|-
|Core i3
Line 153 ⟶ 96:
|3.2 GHz
|{{n/a}}
|4  MB
|15  W
|{{n/a}}
|?
Line 173 ⟶ 116:
[[Category:Intel microarchitectures]]
[[Category:Transactional memory]]
[[Category:X86 microarchitectures]]
Retrieved from "https://en.wikipedia.org/wiki/Cannon_Lake_(microprocessor)"