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Cannon Lake (microprocessor): Difference between revisions

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| produced-end = {{End date and age|February 28, 2020}}
| soldby = [[Intel]]
| designfirmmanuf1 = [[Intel]]
| size-from = [[Intel]] [[10 nanometer|10 nm]] ([[FinFET|tri-gate]]) transistors▼
| manuf1 = [[Intel]]▼
▲| size-from = [[Intel]] [[10 nanometer|10 nm]] ([[FinFET|tri-gate]]) transistors
| clock = 3.2{{nbsp}}GHz
| l1cache = 64{{nbsp}}KB per core
| l2cache = 256{{nbsp}}KB per core
| l3cache = 2{{nbsp}}MB per core
| arch = [[x86-64]]▼
| instructions = [[x86-64]], [[Intel 64]]
| extensions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[FMA instruction set|FMA3]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2#Advanced Vector Extensions 2|AVX2]], [[AVX-512]], [[Intel SHA extensions|SHA]],<ref name=":0">{{cite web |last=Kirsch |first=Nathan |date=February 21, 2016 |title=Intel Cannonlake Added To LLVM's Clang – AVX-512 |url=http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |work=Legit Reviews |access-date=October 23, 2016 |archive-url=https://web.archive.org/web/20161023135525/http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |archive-date=2016-10-23 |url-status=dead}}</ref> [[Trusted Execution Technology|TXT]], [[Transactional Synchronization Extensions|TSX]], [[Software Guard Extensions|SGX]], [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
| numcores = 2
| gpu = Factory disabled
| sock1 = BGA 1440
▲| arch pcode1 = [[x86-64]]CNL
| brand1 = [[Intel Core|Core]]
| predecessor = DesktopMobile: [[Coffee Lake]] (2nd optimization)<br>[[Kaby Lake Refresh]] (2nd optimization)
| successor = [[Ice Lake (microprocessor)|Ice Lake]] (architecture)
| microarch = [[Palm Cove (microarchitecture)|Palm Cove]]
| support status = Legacy support for iGPU
}}
'''Cannon Lake''' (formerly '''Skymont''') is [[list of Intel codenames|Intel's codename]] for the 8th generation of [[Intel Core|Core]] processors based on Palm Cove, a [[10 nm process|10 nm]] [[die shrink]] of the [[Kaby Lake]] [[microarchitecture]]. As a die shrink, CannonPalm LakeCove is a new ''process'' in Intel's [[Process–architecture–optimization_model|process-architecture-optimization]] execution plan as the next step in semiconductor fabrication.<ref name="wccftech">{{Cite web |last=Mujtaba |first=Hassan |date=June 6, 2014 |title=Intel's Cannonlake 10nm Microarchitecture is Due For 2016 - Compatible On Union Bay With Union Point PCH |url=http://wccftech.com/intels-cannonlake-10nm-microarchitecture-due-2016-compatible-union-bay-union-point-pch/ |work=Wccftech |language=en-US |access-date=September 24, 2014}}</ref> Cannon Lake CPUs are the first mainstream CPUs to include the [[AVX-512]] instruction set.
 
Prior to Cannon Lake's launch, Intel launched another 14&nbsp;nm process refinement with the codename [[Coffee Lake]].<ref>{{Cite news |last=Carey |first=Gabe |date=May 13, 2019 |title=Intel Coffee Lake release date, news and features |url=http://www.techradar.com/news/intel-coffee-lake-release-date-news-and-rumors |work=TechRadar |language=en-US |access-date=December 15, 2022}}</ref>
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| caption =
<!----------------- General Info ----------------->
▲| manuf1 designfirm = [[Intel]]
| produced-start = {{Start date and age|May 2018}}
| produced-end = {{End date and age|February 28, 2020}}
| soldby = [[Intel]]
| designfirm = [[Intel]]
| manuf1 = [[Intel]]
| cpuid =
| code =
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| l2cache = 256{{nbsp}}KB per core
| l3cache = 2{{nbsp}}MB per core
| l4cache =
| llcache =
<!------- Architecture and classification -------->
| application =
| size-from = [[Intel]] [[10 nanometer|10 nm]] ([[FinFET|tri-gate]])
| size-to =
| microarch =
| arch = [[x86-64]]
| instructions = x86-64, [[Intel 64]]
| extensions = [[MMX (instruction set)|MMX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]], [[FMA instruction set|FMA3]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions 2#Advanced Vector Extensions 2|AVX2]], [[AVX-512]], [[Intel SHA extensions|SHA]],<ref name=":0">{{cite web |last=Kirsch |first=Nathan |date=February 21, 2016 |title=Intel Cannonlake Added To LLVM's Clang – AVX-512 |url=http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |work=Legit Reviews |access-date=October 23, 2016 |archive-url=https://web.archive.org/web/20161023135525/http://www.legitreviews.com/intel-cannonlake-added-to-llvms-clang_179210 |archive-date=2016-10-23 |url-status=dead}}</ref> [[Trusted Execution Technology|TXT]], [[Transactional Synchronization Extensions|TSX]], [[Software Guard Extensions|SGX]], [[Intel VT-x|VT-x]], [[Intel VT-d|VT-d]]
<!----------- Physical specifications ------------>
| transistors =
| numcores =
| gpu =
| co-processor =
| pack1 =
| sock1 =
<!--------- Products, models, variants ----------->
| core1 =
| pcode1 =
| model1 =
| brand1 = [[Intel Core|Core]]
| variant =
<!------------------ History ------------------->
| predecessor = [[Skylake (microarchitecture)|Skylake]]
| successor = [[Sunny Cove (microarchitecture)|Sunny Cove]]
| support status = Legacy support for iGPU
}}
[[File:Intel@10nm@CannonLake@PalmCoveCores - GT2-Gen10 IGP RadeonRX540@Core i3-8121U@NUC8I3CYSM DSCx13 [email protected]|thumb|Cannon Lake processor die from an i3-8121U with Palm Cove cores]]
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=== Mobile processors ===
==== Cannon Lake-U ====
Common features:
* Socket: BGA 1440.
* Memory support: [[DDR4]]-2400 or [[LPDDR4]]-2400 dual channel (maximum supported: 32 GB).
* PCIe support: 16 lanes of Gen3.
{| class="wikitable sortable" style="text-align:center;" data-ve-attributes="{&quot;style&quot;:&quot;text-align:center;&quot;}"
! rowspan="2" | Processor <br/>branding
! rowspan="2" | Model
! rowspan="2" | Cores <br/>(threads)
! colspan="2" | CPU [[Clockclock rate]] (GHz)
! rowspan="2" | [[Intel Graphics Technology|GPU]]
! rowspan="2" | MemorySmart support<br/>cache
! rowspan="2" | [[CPU cache|L3 <br/>cache]]TDP
! [[cTDP]]
! rowspan="2" | [[Thermal design power|TDP]]
! rowspan="2" | ReleasePrice date<br/>(USD)
|-
! Base
! [[Intel Turbo Boost|Turbo]]
! Down
|-
| Core i3
| [https://ark.intel.com/content/www/us/en/ark/products/136863/intel-core-i3-8121u-processor-4m-cache-up-to-3-20-ghz.html 8121U]
| 2 (4)
| 2.2 GHz
| 3.2 GHz
| {{NAn/a}}
|4 MB
| [[DDR4 SDRAM|DDR4]]-2400 <br /> [[LPDDR#LPDDR4|LPDDR4]]-2400<br /><small>[[Multi-channel memory architecture#Dual-channel architecture|Dual-channel]]</small>
| 15{{&nbsp}};W▼
Up to 32GB
| 4{{nbspn/a}}MB
|-?▼
▲| 15{{nbsp}}W
| {{dts|2018|May|15|format=mdy|abbr=on}}
▲|-
|}
 
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