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{{blockquote|The goal of any instruction format should be: 1. simple decode, 2. simple decode, and 3. simple decode. Any attempts at improved code density at the expense of CPU performance should be ridiculed at every opportunity.<ref>{{cite conference |first1=Vincent |last1=Weaver |first2=Sally |last2=McKee |title=Code Density Concerns for New Architectures |url=http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf |conference=ICCD 2009}}</ref>}}
Competition between RISC and conventional CISC approaches was also the subject of theoretical analysis in the early 1980s, leading, for example, to the [[iron law of processor performance]].▼
Since 2010, a new [[open-source model|open source]] [[instruction set architecture]] (ISA), Berkeley [[RISC-V]], has been under development at the University of California, Berkeley, for research purposes and as a free alternative to proprietary ISAs. As of 2014, version 2 of the [[user space]] ISA is fixed.<ref>{{cite web|last1=Waterman|first1=Andrew|last2=Lee|first2=Yunsup|last3=Patterson|first3=David A.|last4=Asanovi|first4=Krste|title=The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.0|id=Technical Report EECS-2014-54|url=https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.html|publisher=University of California, Berkeley|access-date=1 March 2022}}</ref> The ISA is designed to be extensible from a barebones core sufficient for a small embedded processor to supercomputer and cloud computing use with standard and chip designer–defined extensions and coprocessors. It has been tested in silicon design with the ROCKET [[system on a chip|SoC]], which is also available as an open-source processor generator in the CHISEL language.▼
===Commercial breakout===
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In the early 1980s, significant uncertainties surrounded the RISC concept. One concern involved the use of memory; a single instruction from a traditional processor like the Motorola 68k may be written out as perhaps a half dozen of the simpler RISC instructions. In theory, this could slow the system down as it spent more time fetching instructions from memory. But by the mid-1980s, the concepts had matured enough to be seen as commercially viable.<ref name=Gov239 >''Funding a Revolution: Government Support for Computing Research'' by Committee on Innovations in Computing and Communications 1999 {{ISBN|0-309-06278-0}} page 239</ref><ref name=mipsx />
Commercial RISC designs began to emerge in the mid-1980s. The [[ARM architecture family#ARM1|Acorn ARM1]] appeared in April 1985,<ref>{{cite journal | title = Speciation through entrepreneurial spin-off: The Acorn-ARM story | journal = Research Policy | date = March 2008 | first = Elizabeth | last = Garnsey | author2= Lorenzoni, Gianni|author3= Ferriani, Simone | volume = 37 | issue = 2 | url = http://www2.sa.unibo.it/~simone.ferriani/Download/Speciation%20through%20Entrepreneurial%20Spin-off.pdf | access-date = 2011-06-02 | quote = [...] the first silicon was run on April 26th 1985. | doi=10.1016/j.respol.2007.11.006 | pages=210–224| s2cid = 73520408 }}</ref> MIPS R2000 appeared in January 1986, followed shortly thereafter by [[Hewlett-Packard]]'s [[PA-RISC]] in some of their computers.<ref name=Gov239 /> In the meantime, the Berkeley effort had become so well known that it eventually became the name for the entire concept. In 1987 [[Sun Microsystems]] began shipping systems with the [[SPARC]] processor, directly based on the Berkeley RISC-II system.<ref name=Gov239 /><ref>{{cite book |first=Allen B. |last=Tucker |title=Computer science handbook |year=2004 |isbn=1-58488-360-X |pages=[https://archive.org/details/computersciencee00tuck/page/n1244 100]–6 |publisher=Taylor & Francis |url=https://archive.org/details/computersciencee00tuck|url-access=limited}}</ref> The US government Committee on Innovations in Computing and Communications credits the acceptance of the viability of the RISC concept to the success of the SPARC system.<ref name=Gov239 /> The success of SPARC renewed interest within IBM, which released new RISC systems by 1990 and by 1995 RISC processors were the foundation of a $15 billion server industry.<ref name=Gov239 />
By the later 1980s, the new RISC designs were easily outperforming all traditional designs by a wide margin. At that point, all of the other vendors began RISC efforts of their own. Among these were the [[DEC Alpha]], [[AMD Am29000]], [[Intel i860]] and [[Intel i960|i960]], [[Motorola 88000]], [[IBM Power microprocessors|IBM POWER]], and, slightly later, the IBM/Apple/Motorola [[PowerPC]]. Many of these have since disappeared due to them often offering no competitive advantage over others of the same era. Those that remain are often used only in niche markets or as parts of other systems; of the designs from these traditional vendors, only SPARC and POWER have any significant remaining market.{{citation needed|reason=This is probably true but needs substantiating.|date=March 2023}}
The [[ARM architecture family|ARM architecture]] has been the most widely adopted RISC ISA,
▲Competition between RISC and conventional CISC approaches was also the subject of theoretical analysis in the early 1980s, leading, for example, to the [[iron law of processor performance]].
▲Since 2010, a new [[open-source model|open source]] [[instruction set architecture]] (ISA), [[RISC-V]], has been under development at the University of California, Berkeley, for research purposes and as a free alternative to proprietary ISAs. As of 2014, version 2 of the [[user space]] ISA is fixed.<ref>{{cite web|last1=Waterman|first1=Andrew|last2=Lee|first2=Yunsup|last3=Patterson|first3=David A.|last4=Asanovi|first4=Krste|title=The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.0|id=Technical Report EECS-2014-54|url=https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.html|publisher=University of California, Berkeley|access-date=1 March 2022}}</ref> The ISA is designed to be extensible from a barebones core sufficient for a small embedded processor to supercomputer and cloud computing use with standard and chip designer–defined extensions and coprocessors. It has been tested in silicon design with the ROCKET [[system on a chip|SoC]], which is also available as an open-source processor generator in the CHISEL language.
==Characteristics and design philosophy==
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