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Complex instruction set computer: Revision history


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  • curprev 02:3702:37, 24 September 2023RastaKins talk contribs 14,704 bytes −256 WP:BOLD 6502 cannot be considered RISC. Unlike RISC, 6502 has variable instruction length and variable timing. Most ALU operations reference memory. Dyadic results always go to a single accumulator. No ALU operations operate register to register. Pointers can't be held in registers. undo

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  • curprev 22:0122:01, 17 August 2023Guy Harris talk contribs 14,960 bytes −39 Explicitly mention the small number of registers. (The Data General Nova was a load-store architecture with only 4 registers, so it's in some ways closer to a RISC processor, but the small number of registers probably disqualifies it. "RISC" and "CISC" as terms are a bit of a mess, given the lack of any firm definitions.) Attach the {{cn}} to the claim that they have been described as RISC-like - who made that claim? undo

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  • curprev 02:1702:17, 20 June 2023Guy Harris talk contribs 14,852 bytes +38 →‎CISC and RISC terms: That edition of H&P doesn't mention the term CISC; it talks about load-store, register-memory, and memory-memory ISAs, distinguishing "CISC" ISAs such as x86 and S/3x0 (register-memory for most operations) from "CISC" ISAs such as VAX (supports all operands being register or memory for most operations). undo

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