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The Fujitsu FR-V (Fujitsu RISC-VLIW) is one of the very few processors ever able to process both a very long instruction word (VLIW) and vector processor instructions at the same time, increasing throughput with high parallel computing while increasing performance per watt and hardware efficiency. The family was presented in 1999.^[1] Its design was influenced by the VPP500/5000 models of the Fujitsu VP/2000 vector processor supercomputer line.^[2]

Featuring a 1–8 way very long instruction word (VLIW, Multiple Instruction Multiple Data (MIMD), up to 256 bit) instruction set it additionally uses a 4-way single instruction, multiple data (SIMD) vector processor core. A 32-bit RISC instruction set in the superscalar core is combined with most variants integrating a dual 16-bit media processor also in VLIW and vector architecture. Each processor core is superpipelined as well as 4-unit superscalar.

A typical integrated circuit integrates a system on a chip and further multiplies speed by integrating multiple cores. Due to the very low power requirements it is a solution even for battery-powered applications.

Variants

The family started with the FR-500, includes FR-300, FR-400, FR-450, FR-550 and FR1000 architecture 32-bit processors, can run Linux, RTLinux, VxWorks, eCos, or ITRON and is also supported by the Softune Integrated development environment and the GNU Compiler Collection^[3]^[4] or GNUPro.

It is often used for image processing or video processing with most variants including a dual 16-bit media-processor.^[5]

Technology

The 2005 presented FR1000 uses a core with 8-way 256-bit VLIW (MIMD) filling its superpipeline as well as a 4-unit superscalar architecture (Integer (ALU)-, Floating-point- and two media-processor-units), further increasing its peak performance of each core to up to 28 instructions per clock cycle. Like other VLIW-architectures 1 way is needed to load the next 256-bit instruction: 7-ways usable. Due to the used 4-way single instruction, multiple data (SIMD) vector processor-core, it counts to up to 112 data-operations per cycle and core.^[6] The included 4-way vector processor units are a 32-bit integer arithmetic logic unit and floating point unit as well as a 16-bit media-processor, which can process up to twice the operations in parallel.

The included integer- and floating-point unit enables the FR-V to execute complex tasks fully independent without need for help from a control unit; for example the Nikon Expeed needs only a slowly clocked, quite simple Fujitsu FR controller as the main control unit for all included FR-V, DSP and GPU processors and data communication and other modules. Some processors have integrated memory management unit (MMU), allowing to run virtual multitasking operating systems (also real-time operating systems) with hardware memory protection.

Applications

They are used to build the Milbeaut signal processors specialized for image processing,^[7]^[8] with the newest version additionally including an FR-V based HD video H.264 codec engine.^[9]^[10]

The Milbeaut image engines are included in the Leica S2 and Leica M (Typ 240),^[11] Nikon DSLRs (see Nikon Expeed), some Pentax K mount^[12] cameras and for the Sigma True-II processor.^[13]

References

^ Fujitsu Scientific & Technical Journal: FR500 VLIW-architecture High-performance Embedded Microprocessor by Takao Sukemura Archived 2008-08-18 at the Wayback Machine
^ 8way VLIW CPU quad-core CPU Fujitsu Laboratories (translated)
^ FR-V Built-in Functions GNU Compiler Collection
^ The Definitive Guide to GCC By William von Hagen
^ Media Processor FR-V Family SoC Mounting Peripheral Archived 2015-09-24 at the Wayback Machine Fujitsu
^ Fujitsu: FR-V single-chip multicore processor: FR1000 Archived 2015-04-02 at the Wayback Machine
^ Fujitsu Develops Multi-core Processor for High-Performance Digital Consumer Products
^ Fujitsu: Milbeaut Imaging Processors
^ Nikon: EXPEED3 (D-SLR series) Archived 2012-01-27 at the Wayback Machine
^ "Fujitsu Releases 6th Generation of Milbeaut Imaging Processors". Archived from the original on 2015-04-02. Retrieved 2012-03-01.
^ Fujitsu Microelectronics-Leica's Image Processing System Solution For High-End DSLR
^ Pentax hack: Hardware info
^ "Sigmauser: TRUE Strengths. Written by Stuart Dennison". Archived from the original on 2015-09-24. Retrieved 2012-03-14.

External links

FR Family instruction manual (PDF). Fujitsu. 2007-12-28.
Kevin Buettner; Alexandre Oliva; Richard Henderson (2008-03-01). The FR-V FDPIC ABI. Version 1.0b. Red Hat, Inc. Archived from the original on 2012-02-11. Retrieved 2008-04-25.
Alexandre Oliva; Aldy Hernandez (2004-12-10). The FR-V thread-local storage ABI. Version 1.0. Red Hat, Inc. Archived from the original on 2012-02-11. Retrieved 2008-10-18.
Atsuhiro Suga; Kunihiko Matsunami (July 2000). "Introducing the FR500 embedded microprocessor" (PDF). IEEE Micro. 20 (4): 21–27. doi:10.1109/40.865863. Archived from the original (PDF) on 2011-07-20.
FR-V multi-media (translated) Archived 2008-12-28 at the Wayback Machine

[1] Fujitsu Scientific & Technical Journal: FR500 VLIW-architecture High-performance Embedded Microprocessor by Takao Sukemura Archived 2008-08-18 at the Wayback Machine

[2] 8way VLIW CPU quad-core CPU Fujitsu Laboratories (translated)

[3] FR-V Built-in Functions GNU Compiler Collection

[4] The Definitive Guide to GCC By William von Hagen

[5] Media Processor FR-V Family SoC Mounting Peripheral Archived 2015-09-24 at the Wayback Machine Fujitsu

[6] Fujitsu: FR-V single-chip multicore processor: FR1000 Archived 2015-04-02 at the Wayback Machine

[7] Fujitsu Develops Multi-core Processor for High-Performance Digital Consumer Products

[8] Fujitsu: Milbeaut Imaging Processors

[nexp3-9] Nikon: EXPEED3 (D-SLR series) Archived 2012-01-27 at the Wayback Machine

[f6-10] "Fujitsu Releases 6th Generation of Milbeaut Imaging Processors". Archived from the original on 2015-04-02. Retrieved 2012-03-01.

[11] Fujitsu Microelectronics-Leica's Image Processing System Solution For High-End DSLR

[12] Pentax hack: Hardware info

[13] "Sigmauser: TRUE Strengths. Written by Stuart Dennison". Archived from the original on 2015-09-24. Retrieved 2012-03-14.

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+The [[Fujitsu]] '''FR-V''' (Fujitsu [[RISC]]-[[VLIW]]) is one of the very few [[central processing unit|processors]] ever able to process both a [[very long instruction word]] (VLIW) and [[vector processor]] [[Instruction set|instruction]]s at the same time, increasing [[throughput]] with high [[parallel computing]] while increasing [[performance per watt]] and  [[computer architecture|hardware]] efficiency. The family was presented in 1999.<ref>[http://www.fujitsu.com/downloads/MAG/vol36-1/paper06.pdf Fujitsu Scientific & Technical Journal: FR500 VLIW-architecture High-performance Embedded Microprocessor by Takao Sukemura] {{webarchive|url=https://web.archive.org/web/20080818033118/http://www.fujitsu.com/downloads/MAG/vol36-1/paper06.pdf |date=2008-08-18 }}</ref> Its design was influenced by the VPP500/5000 models of the [[Fujitsu VP]]/[[Fujitsu VP2000|2000]] vector processor [[Supercomputer architecture|supercomputer]] line.<ref>[http://ascii.jp/elem/000/000/346/346429/ 8way VLIW CPU quad-core CPU] Fujitsu Laboratories (translated)</ref>
-[[Image:Nikon Expeed.jpg|thumb|right|250px|[[Expeed|Nikon Expeed]], including an [[image processor|image]]/[[Video processing#Video processor|video processor]] based on FR-V architecture, and a [[Fujitsu FR]] [[microcontroller]] controlling the chip]]
+[[File:FR-V MB93475 in SONY DBZ-RX105.jpg|thumb|FR-V MB93475 in SONY DBZ-RX105 BD/HDD recorder]]
+Featuring a 1–8 way very long instruction word (VLIW, [[Multiple Instruction Multiple Data]] (MIMD), up to 256 bit) instruction set it additionally uses a 4-way [[single instruction, multiple data]] (SIMD) vector processor core. A [[32-bit]] [[RISC]] instruction set in the [[superscalar]] core is combined with most variants integrating a dual [[16-bit]] [[media processor]] also in VLIW and vector architecture. Each processor core is [[Instruction pipeline|superpipelined]] as well as 4-unit [[superscalar]].
-The [[Fujitsu]] '''FR-V''' (Fujitsu [[RISC]]-[[VLIW]]) is one of the very few [[central processing unit|processors]] ever able to process both a [[very long instruction word]] (VLIW) and [[vector processor]] [[Instruction set|instruction]]s at the same time, increasing [[throughput]] with high [[parallel computing]] while increasing [[performance per watt]] and  [[computer architecture|hardware]] efficiency. The family was presented in 1999.<ref>[http://www.fujitsu.com/downloads/MAG/vol36-1/paper06.pdf Fujitsu Scientific & Technical Journal: FR500 VLIW-architecture High-performance Embedded Microprocessor by Takao Sukemura]</ref> Its design was influenced by the VPP500/5000 models of the [[Fujitsu VP]]/[[Fujitsu VP2000|2000]] vector processor [[Supercomputer architecture|supercomputer]] line.<ref>[http://translate.google.com/translate?sl=auto&tl=en&js=n&prev=_t&hl=en&ie=ISO-8859-1&layout=2&eotf=1&u=http%3A%2F%2Fascii.jp%2Felem%2F000%2F000%2F346%2F346429%2F 8way VLIW CPU quad-core CPU] Fujitsu Laboratories (translated)</ref>
-Featuring a 1-8 way very long instruction word (VLIW, [[Multiple Instruction Multiple Data]] (MIMD), up to 256 bit) instruction set it additionally uses a 4-way [[SIMD|single instruction, multiple data]] (SIMD) vector processor core. A [[32-bit]] [[RISC]] instruction set in the [[superscalar]] core is combined with most variants integrating a dual [[16-bit]] [[media processor]] also in VLIW and vector architecture. Each processor core is [[Instruction pipeline|superpipelined]] as well as 4-unit [[superscalar]].
 A typical [[integrated circuit]] integrates a [[system on a chip]] and further multiplies speed by integrating [[multi-core processor|multiple cores]]. Due to the very low power requirements it is a solution even for battery-powered applications.
 ==Variants==
-The family started with the FR-500, includes FR-300, FR-400, FR-450, FR-550 and FR1000 architecture [[32-bit]] processors, can run [[Linux]], [[RTLinux]], [[VxWorks]], [[eCos]], [[ITRON]] or [[cryptlib]] and is also supported by the [[Softune]] [[Integrated development environment]] and the [[GNU Compiler Collection]]<ref>[http://gcc.gnu.org/onlinedocs/gcc-4.3.6/gcc/FR_002dV-Built_002din-Functions.html FR-V Built-in Functions] GNU Compiler Collection</ref><ref>[http://books.google.de/books?id=wQ6r3UTivJgC&pg=PA425&lpg=PA425&dq=Fujitsu+FR-V&source=bl&ots=EKXpQscDFw&sig=kzNdGc8CTRFkcQYb0PY9vtUMd8g&hl=en&sa=X&ei=FGDaUNu0LMni4QSe64CwBQ&redir_esc=y The Definitive Guide to GCC By William von Hagen]</ref> or GNUPro.
+The family started with the FR-500, includes FR-300, FR-400, FR-450, FR-550 and FR1000 architecture [[32-bit]] processors, can run [[Linux]], [[RTLinux]], [[VxWorks]], [[eCos]], or [[ITRON]] and is also supported by the [[Softune]] [[Integrated development environment]] and the [[GNU Compiler Collection]]<ref>[https://gcc.gnu.org/onlinedocs/gcc-4.3.6/gcc/FR_002dV-Built_002din-Functions.html FR-V Built-in Functions] GNU Compiler Collection</ref><ref>[https://books.google.com/books?id=wQ6r3UTivJgC&pg=PA425 The Definitive Guide to GCC By William von Hagen]</ref> or GNUPro.
-It is often used for [[image processor|image processing]] or [[Video scaler#Video processor|video processing]] with most variants including a dual [[16-bit]] media-processor.<ref>[http://www.fujitsu.com/downloads/EDG/binary/pdf/find/23-2e/2.pdf Media Processor FR-V Family SoC Mounting Peripheral] Fujitsu</ref>
+It is often used for [[image processor|image processing]] or [[Video scaler#Video processor|video processing]] with most variants including a dual [[16-bit]] media-processor.<ref>[http://www.fujitsu.com/downloads/EDG/binary/pdf/find/23-2e/2.pdf Media Processor FR-V Family SoC Mounting Peripheral] {{Webarchive|url=https://web.archive.org/web/20150924020505/http://www.fujitsu.com/downloads/EDG/binary/pdf/find/23-2e/2.pdf |date=2015-09-24 }} Fujitsu</ref>
 ==Technology==
-The 2005 presented FR1000 uses a core with 8-way 256-bit [[VLIW]] ([[MIMD]]) filling its [[Instruction pipeline|superpipeline]] as well as a 4-unit [[superscalar]] architecture ([[Arithmetic logic unit|Integer (ALU)]]-, [[Floating-point unit|Floating-point]]- and two media-processor-units), further increasing its [[Algorithm efficiency|peak performance]] of each core to up to 28 [[Instructions per cycle|instructions per clock cycle]]. Like other VLIW-architectures 1 way is needed to load the next 256-bit instruction: 7-ways usable. Due to the used 4-way [[SIMD|single instruction, multiple data]] (SIMD) [[vector processor]]-core, it counts to up to 112 [[Vector processor#Description|data-operations per cycle]] and core.<ref>[http://www.fujitsu.com/downloads/MAG/vol42-2/paper03.pdf Fujitsu: FR-V single-chip multicore processor: FR1000]</ref> The included 4-way vector processor units are a [[32-bit]] [[integer]] [[arithmetic logic unit]] and [[floating point unit]] as well as a [[16-bit]] media-processor, which can process up to twice the operations in parallel.
+The 2005 presented FR1000 uses a core with 8-way 256-bit [[VLIW]] ([[Multiple instruction, multiple data|MIMD]]) filling its [[Instruction pipeline|superpipeline]] as well as a 4-unit [[superscalar]] architecture ([[Arithmetic logic unit|Integer (ALU)]]-, [[Floating-point unit|Floating-point]]- and two media-processor-units), further increasing its [[Algorithm efficiency|peak performance]] of each core to up to 28 [[Instructions per cycle|instructions per clock cycle]]. Like other VLIW-architectures 1 way is needed to load the next 256-bit instruction: 7-ways usable. Due to the used 4-way [[single instruction, multiple data]] (SIMD) [[vector processor]]-core, it counts to up to 112 [[Vector processor#Description|data-operations per cycle]] and core.<ref>[http://www.fujitsu.com/downloads/MAG/vol42-2/paper03.pdf Fujitsu: FR-V single-chip multicore processor: FR1000] {{webarchive|url=https://web.archive.org/web/20150402150434/http://www.fujitsu.com/downloads/MAG/vol42-2/paper03.pdf |date=2015-04-02 }}</ref> The included 4-way vector processor units are a [[32-bit]] [[integer]] [[arithmetic logic unit]] and [[floating point unit]] as well as a [[16-bit]] media-processor, which can process up to twice the operations in parallel.
-The included integer- and floating-point unit enables the FR-V to execute complex tasks fully independent without need for help from a [[Electronic control unit|control unit]]; for example the [[Expeed|Nikon EXPEED]] needs only a slowly clocked, quite simple [[Fujitsu FR]] controller as the main control unit for all included FR-V, [[Digital signal processor|DSP]] and [[GPU]] processors and [[data communication]] and other modules. Some processors have integrated [[memory management unit]] (MMU), allowing to run [[Virtual memory|virtual]] [[multitasking]] [[operating system]]s (also [[real-time operating system]]s) with hardware [[memory protection]].
+The included integer- and floating-point unit enables the FR-V to execute complex tasks fully independent without need for help from a [[Electronic control unit|control unit]]; for example the [[Expeed|Nikon Expeed]] needs only a slowly clocked, quite simple [[Fujitsu FR]] controller as the main control unit for all included FR-V, [[Digital signal processor|DSP]] and [[GPU]] processors and [[data communication]] and other modules. Some processors have integrated [[memory management unit]] (MMU), allowing to run [[Virtual memory|virtual]] [[Computer multitasking|multitasking]] [[operating system]]s (also [[real-time operating system]]s) with hardware [[memory protection]].
 ==Applications==
-They are used to build the [[Milbeaut]] [[signal processor]]s specialized for [[image processor|image processing]],<ref>[http://www.fujitsu.com/global/news/pr/archives/month/2005/20050207-01.html Fujitsu Develops Multi-core Processor for High-Performance Digital Consumer Products]</ref><ref>[http://www.fujitsu.com/global/services/microelectronics/product/assp/milbeaut/ Fujitsu: Milbeaut Imaging Processors]</ref> with the newest version additionally including an FR-V based [[High-definition video|HD video]] [[H.264]] codec engine.<ref name=nexp3 >[http://www.nikonusa.com/Learn-And-Explore/Photography-Glossary/A/1/EXPEED3-D-SLR-series.html Nikon: EXPEED3 (D-SLR series)]</ref><ref name=f6 >[http://jp.fujitsu.com/group/fsl/en/release/20110208.html Fujitsu Releases 6th Generation of Milbeaut Imaging Processors]</ref>
+They are used to build the [[Milbeaut]] [[signal processor]]s specialized for image processing,<ref>[http://www.fujitsu.com/global/news/pr/archives/month/2005/20050207-01.html Fujitsu Develops Multi-core Processor for High-Performance Digital Consumer Products]</ref><ref>[http://www.fujitsu.com/global/services/microelectronics/product/assp/milbeaut/ Fujitsu: Milbeaut Imaging Processors]</ref> with the newest version additionally including an FR-V based [[High-definition video|HD video]] [[H.264]] codec engine.<ref name=nexp3>[http://www.nikonusa.com/Learn-And-Explore/Photography-Glossary/A/1/EXPEED3-D-SLR-series.html Nikon: EXPEED3 (D-SLR series)] {{webarchive|url=https://web.archive.org/web/20120127002321/http://www.nikonusa.com/Learn-And-Explore/Photography-Glossary/A/1/EXPEED3-D-SLR-series.html |date=2012-01-27 }}</ref><ref name=f6 >{{Cite web |url=http://jp.fujitsu.com/group/fsl/en/release/20110208.html |title=Fujitsu Releases 6th Generation of Milbeaut Imaging Processors |access-date=2012-03-01 |archive-date=2015-04-02 |archive-url=https://web.archive.org/web/20150402154414/http://jp.fujitsu.com/group/fsl/en/release/20110208.html |url-status=dead }}</ref>
-The Milbeaut image engines are included in the [[Leica M (camera)|Leica S2]] and [[Leica M]],<ref>[http://www.fujitsu.com/hk/news/pr/20080926.html Fujitsu Microelectronics-Leica's Image Processing System Solution For High-End DSLR]</ref> [[Nikon DSLR]]s (see [[Expeed|Nikon EXPEED]]), some [[Pentax K mount]]<ref>[http://www.pentax-hack.info/documents/hardware.html Pentax hack: Hardware info]</ref> cameras and for the [[Sigma Corporation|Sigma]] True-II processor.<ref>[http://www.sigmauser.co.uk/index.php?option=com_content&view=article&id=405:true-strengths&catid=26 Sigmauser: TRUE Strengths. Written by Stuart Dennison]</ref>
+The Milbeaut image engines are included in the [[Leica S2]] and [[Leica M (Typ 240)]],<ref>[http://www.fujitsu.com/hk/news/pr/20080926.html Fujitsu Microelectronics-Leica's Image Processing System Solution For High-End DSLR]</ref> [[Nikon DSLR]]s (see Nikon Expeed), some [[Pentax K mount]]<ref>[http://www.pentax-hack.info/documents/hardware.html Pentax hack: Hardware info]</ref> cameras and for the [[Sigma Corporation|Sigma]] True-II processor.<ref>{{Cite web |url=http://www.sigmauser.co.uk/index.php?option=com_content&view=article&id=405:true-strengths&catid=26 |title=Sigmauser: TRUE Strengths. Written by Stuart Dennison |access-date=2012-03-14 |archive-date=2015-09-24 |archive-url=https://web.archive.org/web/20150924101748/http://www.sigmauser.co.uk/index.php?option=com_content&view=article&id=405:true-strengths&catid=26 |url-status=dead }}</ref>
 ==See also==
+* [[Color image pipeline]]
-{|
+* [[Application-specific integrated circuit|ASIC]]
-|- valign=top
+* [[Parallel computing]]
-|
-* [[SIMD|SIMD computing]]
+* [[SPARClite]]
-* [[Softune]]
-* [http://translate.google.com/translate?hl=en&ie=UTF8&prev=_t&sl=auto&tl=en&u=http://ja.wikipedia.org/wiki/FR-V FR-V (translated)]
-|
-*[[Color image pipeline]]
-*[[Image processor]]
-*[[Application-specific integrated circuit|ASIC]]
-|
-*[[Parallel computing]]
-*[[Sparclite]]
-*[[Expeed|Nikon Expeed]]
-|}
 ==References==
-{{reflist|30em}}
+{{reflist}}
 == External links ==
-* {{Cite manual
+* {{Cite book
  |      title = FR Family instruction manual
  |       date = 2007-12-28
  |  publisher = Fujitsu
- |        url = http://edevice.fujitsu.com/fj/MANUAL/MANUALp/en-pdf/CM71-00101-5E.pdf
+ |        url = http://www.fujitsu.com/downloads/CN/fss/services/mcu/32bit/progfr-cm71-00101-5e.pdf
- }}
-* {{Cite manual
- |      title = The FR-V FDPIC ABI
- |     author = Kevin Buettner, Alexandre Oliva, Richard Henderson
- |       date = 2008-03-01
- |    version = Version 1.0b
- |  publisher = Red Hat, Inc
- |        url = http://www.lsd.ic.unicamp.br/~oliva/writeups/FR-V/FDPIC-ABI.txt
- }}
-* {{Cite manual
- |      title =  The FR-V thread-local storage ABI
- |     author = Alexandre Oliva, Aldy Hernandez
- |       date = 2004-12-10
- |    version = Version 1.0
- |  publisher = Red Hat, Inc
- |        url = http://www.lsd.ic.unicamp.br/~oliva/writeups/FR-V/FDPIC-ABI-TLS.txt
  }}
+* {{Cite book |title=The FR-V FDPIC ABI |author1=Kevin Buettner |author2=Alexandre Oliva |author3=Richard Henderson |date=2008-03-01 |version=Version 1.0b |publisher=Red Hat, Inc |url=http://www.lsd.ic.unicamp.br/~oliva/writeups/FR-V/FDPIC-ABI.txt |access-date=2008-04-25 |archive-url=https://web.archive.org/web/20120211173940/http://www.lsd.ic.unicamp.br/~oliva/writeups/FR-V/FDPIC-ABI.txt |archive-date=2012-02-11 |url-status=dead }}
+* {{Cite book |title=The FR-V thread-local storage ABI |author1=Alexandre Oliva |author2=Aldy Hernandez |date=2004-12-10 |version=Version 1.0 |publisher=Red Hat, Inc |url=http://www.lsd.ic.unicamp.br/~oliva/writeups/FR-V/FDPIC-ABI-TLS.txt |access-date=2008-10-18 |archive-url=https://web.archive.org/web/20120211173947/http://www.lsd.ic.unicamp.br/~oliva/writeups/FR-V/FDPIC-ABI-TLS.txt |archive-date=2012-02-11 |url-status=dead }}
 * {{cite journal
- |      title = Introducing the FR500 embedded microprocessor
+ |title=Introducing the FR500 embedded microprocessor
- |     author = Atsuhiro Suga, Kunihiko Matsunami
+ |author1=Atsuhiro Suga
+ |author2=Kunihiko Matsunami
- |    journal = IEEE Micro
+ |journal=IEEE Micro
  |date=July 2000
- |     volume = 20
+ |volume=20
- |      issue = 4
+ |issue=4
- |      pages = 21&ndash;27
+ |pages=21–27
- |        doi = 10.1109/40.865863
+ |doi=10.1109/40.865863
- |        url = http://www.ece.umd.edu/class/enee759m.S2002/papers/suga2000-micro20-4.pdf
+ |url=http://www.ece.umd.edu/class/enee759m.S2002/papers/suga2000-micro20-4.pdf
+ |url-status=dead
- }}
+ |archiveurl=https://web.archive.org/web/20110720090106/http://www.ece.umd.edu/class/enee759m.S2002/papers/suga2000-micro20-4.pdf
-*[http://translate.googleusercontent.com/translate_c?depth=1&hl=en&ie=UTF8&prev=_t&rurl=translate.google.com&sl=auto&tl=en&u=http://jp.fujitsu.com/microelectronics/products/assp/frv/&usg=ALkJrhi5oFscFLeGWHstJ3b-6n3AEVpHiQ FR-V multi-media (translated)]
+ |archivedate=2011-07-20
+}}
+* [http://jp.fujitsu.com/microelectronics/products/assp/frv/ FR-V multi-media (translated)] {{Webarchive|url=https://web.archive.org/web/20081228145259/http://jp.fujitsu.com/microelectronics/products/assp/frv/ |date=2008-12-28 }}
 {{Microcontrollers}}
+[[Category:Digital signal processors]]
+[[Category:Fujitsu microprocessors]]
 [[Category:Parallel computing]]
 [[Category:SIMD computing]]
-[[Category:Digital signal processors]]
+[[Category:Very long instruction word computing]]
-[[Category:Fujitsu microprocessors]]