Jump to content

ARM Cortex-A15: Difference between revisions

From Wikipedia, the free encyclopedia
Browse history interactively
← Previous editNext edit →
Content deleted Content added
VisualWikitext
No edit summary
Marsavian (talk | contribs)
48 edits
Have added 3 links (2 from ARM !) which prove LPAE is 40-bit only.
Line 42: Line 42:


Key features of the Cortex-A15 core are:
Key features of the Cortex-A15 core are:
* 64-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM (1TB needs 40 bits).{{Dubious|LPAE|date=May 2011}}
* 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM.<ref>http://www.eetimes.com/electronics-news/4206387/ARM7-40bit-virtualization</ref><ref name="ARM: Add support for the Large Physical Address Extensions">http://lwn.net/Articles/444559/</ref>
* 15-stage pipeline, with [[out-of-order execution|out-of-order]] [[speculative execution|speculative issue]] [[superscalar]] execution pipeline.
* 15 stage integer / 17-25 stage floating point pipeline, with [[out-of-order execution|out-of-order]] [[speculative execution|speculative issue]] 3-way [[superscalar]] execution pipeline.<ref>http://www.arm.com/files/pdf/AT-Exploring_the_Design_of_the_Cortex-A15.pdf</ref>
* 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (an AMBA-4 coherent interconnect). ARM provides specifications but the foundries individually design ARM chips, and AMBA-4 scales beyond 2 clusters.
* 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (an AMBA-4 coherent interconnect). ARM provides specifications but the foundries individually design ARM chips, and AMBA-4 scales beyond 2 clusters.
* DSP and [[ARM architecture#Advanced SIMD (NEON)|NEON]] [[SIMD]] extensions onboard (per core).
* DSP and [[ARM architecture#Advanced SIMD (NEON)|NEON]] [[SIMD]] extensions onboard (per core).

Revision as of 17:36, 23 June 2011

ARM Cortex-A15 MPCore
General information
Launchedin production late 2011,[1] to market late 2012[2]
Designed byARM
Performance
Max. CPU clock rate1000 MHz  to 2500 MHz 
Cache
L1 cache64 kB (32 kB I-Cache, 32 kB D-Cache) per core
L2 cacheup to 4 MB[3] per cluster
L3 cachenone
Architecture and classification
Technology node32 nm/28 nm initially[4] to 20 nm roadmap[4]
Instruction setARMv7
Physical specifications
Cores
  • 1-4 per cluster, 1-2 clusters per physical chip[5]

The ARM Cortex-A15 MPCore is a multicore ARM architecture processor providing an out-of-order superscalar pipeline ARM v7 instruction set running at up to 2.5 GHz.[6] ARM has confirmed that the Cortex A15 core is 40 percent faster than the Cortex-A9 core, all things equal.[7] The first A15 designs have already been taped out, but products based on the chip are not expected in the market until 2012.[1]

Eigenschaften

Key features of the Cortex-A15 core are:

  • 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM.[8][9]
  • 15 stage integer / 17-25 stage floating point pipeline, with out-of-order speculative issue 3-way superscalar execution pipeline.[10]
  • 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (an AMBA-4 coherent interconnect). ARM provides specifications but the foundries individually design ARM chips, and AMBA-4 scales beyond 2 clusters.
  • DSP and NEON SIMD extensions onboard (per core).
  • VFPv4 Floating Point Unit onboard (per core).
  • Hardware virtualization support.
  • Thumb-2 instruction set encoding reduces the size of programs with little impact on performance.
  • TrustZone security extensions.
  • Jazelle DBX support for Java execution.
  • Jazelle RCT for JIT complilation.
  • Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution.
  • 32kB data + 32kB instruction L1 cache per core.
  • Integrated low-latency level-2 cache controller, up to 4 MB per cluster.

Implementations

Implementations are only expected to sample in 2011, and none are expected to market before 2012 or 2013.

Press announcements of forthcoming implementations:

  • Texas Instruments OMAP 5 SoCs[11]
  • ST-Ericsson Nova A9600[12]
  • Nvidia a future Tegra chip[13] (the "Wayne" design for 2012[14])

Other licensees expected to produce an A15 design at some point are LG[15][16] and Samsung. [17] Although Apple is a major ARM licensee with already substantial developed ARM-based product lines (the iPad, iPhone, and iPods), no announcements have yet been made about a continuation in the form of a future cortex A15-based Apple design.

See also

References

  1. ^ a b TI Reveals OMAP 5: The First ARM Cortex A15 SoC
  2. ^ ARM Expects First Cortex-A15 Devices in Late 2012
  3. ^ Cortex-A15 Processor — Product description
  4. ^ a b ARM Unveils Cortex-A15 MPCore Processor to Dramatically Accelerate Capabilities of Mobile, Consumer and Infrastructure Applications — in the Supporting Technology section
  5. ^ CoreLink Network Interconnect for AMBA AXI
  6. ^ ARM Cortex-A15 - ARM Processor
  7. ^ Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9
  8. ^ http://www.eetimes.com/electronics-news/4206387/ARM7-40bit-virtualization
  9. ^ http://lwn.net/Articles/444559/
  10. ^ http://www.arm.com/files/pdf/AT-Exploring_the_Design_of_the_Cortex-A15.pdf
  11. ^ http://www.ti.com/ww/en/omap/omap5/omap5-platform.html?DCMP=OMAP5&HQS=Other+PR+wbu_omap5_pr_v
  12. ^ http://www.stericsson.com/press_releases/NovaThor.jsp
  13. ^ http://pressroom.nvidia.com/easyir/customrel.do?easyirid=A0D622CE9F579F09&version=live&releasejsp=release_157&xhtml=true&prid=705184
  14. ^ 28nm implies cortex a15
  15. ^ http://www.arm.com/about/newsroom/lg-electronics-licenses-arm-processor-technology-to-drive-platform-strategy-in-home-and-mobile-markets.php
  16. ^ http://www.itproportal.com/2011/04/26/why-lg-getting-arm-cortex-a15-license-big-deal/
  17. ^ http://blogs.strategyanalytics.com/HCT/post/2011/02/08/Market-share-concerns-remain-for-TI-despite-the-impressive-OMAP-5.aspx
Retrieved from "https://en.wikipedia.org/w/index.php?title=ARM_Cortex-A15&oldid=435835160"