System bus model
 | It has been suggested that this article be merged into Von Neumann architecture. (Discuss) Proposed since October 2010. |
| It has been suggested that this article be merged into System bus. (Discuss) Proposed since May 2011. |
The system bus model is a streamlined version of the von Neumann model of computer architecture.[1] Its main feature is that it interconnects the processor, memory, and I/O subsystems (the three individual subunits which the model divides the computer into) by a single bus, the system bus; which is composed of three buses each dedicated to a particular function: the data bus, address bus, and control bus.[2] The data bus is used for the transfer of data between subunits; while the address bus is used to transmit information to determine where the data should be sent.[2] The control bus is used to provide information as to how data is to be sent.[2] The system bus model also deviates from the von Neumann model by combining the arithmetic logic unit (ALU) and the central processing unit (CPU) into a single unit.[2]
References
- ^ Linda Null; Julia Lobur (2006). The essentials of computer organization and architecture (2 ed.). Jones & Bartlett Learning. ISBN 9780763737696.
- ^ a b c d Murdocca, Miles J. (2000). Principles of Computer Architecture. Prentice-Hall. p. 5. ISBN 0-201-43664-7.
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