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Sunway (processor)

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This is an old revision of this page, as edited by Comp.arch (talk | contribs) at 21:45, 6 July 2016 (Dongarra actually lists some (high-level) details on the [micro]arch (and instruction set, wide vector instructions (I guess new), bitness might a typo.. in addition to RISC, but not opcodes etc.). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Sunway, or ShenWei, (Chinese:申威), is a series of microprocessors developed by Jiāngnán Computing Lab (江南计算技术研究所) in Wuxi, China. Details of the architecture are still sparse.

History of Sunway processors

The Sunway series of microprocessors was developed primarily for the use of the military of the People's Republic of China. It is expressed on online forums that the original microarchitecture is believed to be inspired by DEC Alpha.[1][2] The SW-3 in particular is felt to be based on the Alpha 21164.[3]

Jack Dongarra states about the follow-on SW26010, the "Shenwei-64 Instruction Set (this is NOT related to the DEC Alpha instruction set)" (and doesn't say it's a new instruction set from the three previous generations he names);[4][5] although precise details of the instruction set are not known.

Sunway SW-1

  • First generation, 2006
  • Single-core
  • 900 MHz

Sunway SW-2

  • Second generation, 2008
  • Dual-core
  • 1400 MHz
  • SMIC 130 nm process
  • 70–100 W

Sunway SW-3 / SW1600

  • Third generation, 2010
  • 16-core, 64-bit RISC[6]
  • 975–1200 MHz[6]
  • 65 nm process
  • 140.8 GFLOPS @ 1.1 GHz
  • Max memory capacity: 16 GB
  • Peak memory bandwidth: 68 GB/s
  • Quad-channel 128-bit DDR3
  • Four-issue superscalar
  • Two integer and two floating-point execution units
  • 7-stage integer pipeline and 10-stage floating-point pipeline
  • 43-bit virtual address and 40-bit physical address
  • Up to 8 TB virtual memory and 1 TB of physical memory supported
  • L1 cache: 8 KB instruction cache and 8 KB data cache[6]
  • L2 cache: 96 KB[6]
  • 128-bit system bus

Sunway SW26010

See also: SW26010
  • Fourth generation, 2016
  • 64-bit RISC processor
  • Manycore architecture, with 4 CPU clusters on a chip, each comprising 64 lightweight compute CPUs with an additional management CPU, linked by a network-on-a-chip[7]

See also

References

  1. ^ hswz (2009-05-04). "Jiangnan Computing Lab's Civilian CPU Debut - SW-1". bbs.lemote.com. Retrieved 2011-10-31.
  2. ^ "LinkedIn profile: Chen Gang". LinkedIn.
  3. ^ Hung-Sheng Tsao (2011-10-29). "SW1600 and Alpha 21164". LaoTsao's Weblog. Retrieved 2011-10-29.
  4. ^ Dongarra, Jack (2016-06-20). "Report on the Sunway TaihuLight System" (PDF). www.netlib.org. Retrieved 2016-06-20.
  5. ^ Hemsoth, Nicole (20 June 2016). "A Look Inside China's Chart-Topping New Supercomputer". The Next Platform. Retrieved 4 July 2016.
  6. ^ a b c d Novakovic, Nebojsa (2011-12-26). "Chinese high end CPUs are now in the game – details: Part 2, Alpha". VR-Zone. Retrieved 2016-06-22.
  7. ^ Fu, H H; Liao, JF; Yang, J Z (2016). "The Sunway TaihuLight Supercomputer: System and Applications". Sci. China Inf. Sci. doi:10.1007/s11432-016-5588-7. Retrieved 2016-06-22. {{cite journal}}: Unknown parameter |displayauthors= ignored (|display-authors= suggested) (help)
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