“Balaji was DFT lead for the main project I worked on at Intel. He has excellent knowledge of the whole DFT process, from scan/MBIST insertion through to test pattern generation and validation. His years of experience with the Tessent flow helped me out with several issues and kept the DFT team off the critical path of the design. He is very approachable and pleasure to work with.”
Über uns
- Experienced DFT Engineer/lead/Manager with demonstrable experience from RTL design to…
Activity
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With the advent of new technologies, like backside power in advanced process nodes, making fault isolation extremely challenging, this new Tessent…
With the advent of new technologies, like backside power in advanced process nodes, making fault isolation extremely challenging, this new Tessent…
Liked by Balajiraja Ravinarayanan
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Still hand placing macros? Discover how Aprisa's AI-driven macro placement technology helped @Maxlinear reduce designer effort while producing…
Still hand placing macros? Discover how Aprisa's AI-driven macro placement technology helped @Maxlinear reduce designer effort while producing…
Liked by Balajiraja Ravinarayanan
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Learn about Layout Aware Diagnosis Flow using Tessent ATPG in this presentation by Intel Corporation and Siemens EDA, delivered at the U2U Europe…
Learn about Layout Aware Diagnosis Flow using Tessent ATPG in this presentation by Intel Corporation and Siemens EDA, delivered at the U2U Europe…
Liked by Balajiraja Ravinarayanan
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Publications
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A Unified Memory BIST Diagnostics and Failure Analysis Flow
SNUG SIlicon Valley 2022
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A SystemVerilog interface based external MBIST solution for Intel AI designs suitable for Intel and TSMC processes
Design & Test Technology Conference (DTTC), Intel Corporation
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From Architecture to Silicon: A Unified MBIST Diagnostics and Failure Analysis Flow for Intel VPU Products
Design & Test Technology Conference (DTTC), Intel Corporation
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Hierarchical Nested-Ring MBIST Architecture for Intel VPU products
Synopsys User Group (SNUG) Europe 2020
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Poster on "Accelerating Array Fault Diagnosis using Validated Logical-to-Physical Mapping"
International Test Conference India 2022
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RTL Design Validation Using Static Connectivity Checks
SNUG WORLD 2021
Honors & Awards
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IEEE Senior member
IEEE
Recommendations received
3 people have recommended Balajiraja
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