Designing FPGA-Based Mealy FSMs with Two Levels of Logic
A Barkalov, L Titarenko… - 2019 8th International …, 2019 - ieeexplore.ieee.org
A Barkalov, L Titarenko, K Mielcarek
2019 8th International Conference on Modern Circuits and Systems …, 2019•ieeexplore.ieee.orgA method is proposed for decreasing hardware in FPGA-based Mealy FSMs. The method is
based on transforming state codes into class codes. The class codes are generated by the
second level of FSM circuit An example of synthesis is given. The results of investigations
are shown.
based on transforming state codes into class codes. The class codes are generated by the
second level of FSM circuit An example of synthesis is given. The results of investigations
are shown.
A method is proposed for decreasing hardware in FPGA-based Mealy FSMs. The method is based on transforming state codes into class codes. The class codes are generated by the second level of FSM circuit An example of synthesis is given. The results of investigations are shown.
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