Designing HFPGA-based FSMs with counters
A Barkalov, L Titarenko… - 2017 MIXDES-24th …, 2017 - ieeexplore.ieee.org
2017 MIXDES-24th International Conference" Mixed Design of …, 2017•ieeexplore.ieee.org
A method is proposed for hardware reduction of HFPGA-based Moore FMS's logic circuit.
The method is based on replacement of state register by state counter. The counter can be
increased during both conditional and unconditional transitions. There is an example of
application of proposed method.
The method is based on replacement of state register by state counter. The counter can be
increased during both conditional and unconditional transitions. There is an example of
application of proposed method.
A method is proposed for hardware reduction of HFPGA-based Moore FMS's logic circuit. The method is based on replacement of state register by state counter. The counter can be increased during both conditional and unconditional transitions. There is an example of application of proposed method.
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