Neville D'Souza

Neville D'Souza

Austin, Texas, United States
522 followers 500+ connections

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- Digital and Mixed Signal Design Verification using advanced constrained-random…

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    Apfel

    Austin, Texas

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    Austin, Texas Area

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    Raleigh-Durham, North Carolina Area

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    Vereinigte Arabische Emirate

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  • North Carolina State University Graphic

    North Carolina State University

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    Courses:
    Architecture of Parallel Computers.
    VLSI Design
    Digital ASIC Design
    Digital Electronics
    Embedded Systems Design
    IC Technology and Fabrication

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    Project:
    Low Power FPGA Design July 2010 –May 2011
    Designed every single Basic Logic Element and Configurable Logic Block for Low Power FPGA Block.
    Design on Transistor level and also ideal sizing of all the transistors was done for minimum Power Consumption.
    Implemented Gated Clock Technique for minimizing Power Consumption.
    Tested design on 130nm, 90nm, 65nm VLSI technologies.
    Presented National Level Technical paper on "LOW POWER FPGA DESIGN".

Publications

  • Low power FPGA design

    o Main focus was to lower down the power consumption to its minimum.

    o Started with design of single Basic Logic Element and Configurable logic Blocks on

    transistor level.

    o Ideal sizing of all the transistors was done for minimum power consumption and also

    incorporated low power technique like Gated Clock.

    Other authors

Projects

  • Verification of LC3 Microcontroller using SystemVerilog:

    Designed a fully reusable, layered test bench in SystemVerilog with fully constrained random inputs and enabled coverage feedback to verify the functionality of an LC3 Microcontroller on Questa.

    Other creators

  • Chip Design and Implementation for Histogram Equalization

    Designed and implemented the hardware description model of a chip for the purpose of performing histogram equalization in Verilog.

    Other creators

  • 64 bit Subthreshold Synchronous SRAM

    Designed and implemented schematic and layout of 64 bit SRAM.
    Potentially isolated storage node during read cycle to improve read SNM while conveniently scaling down supply voltage for sub- threshold operation region.
    Operating voltage:200mV

  • Implementation of a Trace Driven SMP Simulator

    Cache policies: Write back and write allocate policy, and LRU replacement policy for all cases. Developed code to maintain coherence across one level of cache across multiprocessors using MSI, MESI & MOESI protocols.

  • MOSFET Front End Process Design


    Designed and simulated a p-channel MOSFET process flow to include trench isolation, channel, source/drain and gate design. The specifications for the MOSFET was taken from 2003 edition of the ITRS roadmap for the 100 nm technology node (DRAM ½ pitch) for year 2003.

  • Low Power FPGA Design

    Designed every single Basic Logic Element and Configurable Logic Block for Low Power FPGA Block.
    Design on Transistor level and also ideal sizing of all the transistors was done for minimum Power Consumption.
    Implemented Gated Clock Technique for minimizing Power Consumption.
    Tested design on 130nm, 90nm, 65nm VLSI technologies.
    Presented National Level Technical paper on "LOW POWER FPGA DESIGN".

Languages

  • Hindi

    Full professional proficiency

  • Konkani

    Limited working proficiency

  • Marathi

    Full professional proficiency

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