Amc 7812 B
Amc 7812 B
Amc 7812 B
www.ti.com
FEATURES
DESCRIPTION
2345
Single-Ended/
Differential
ADC-REF-IN/CMP
Reference
(2.5V)
REF-OUT
REF-DAC
Trigger
DAC0-OUT
DAC-0
ADC
DAC1-OUT
DAC2-OUT
D1+
GPIO-5
D1-
GPIO-4
D2+
GPIO-7
DAC3-OUT
Control/Limits/Status
Registers
DAC4-OUT
DAC5-OUTDAC6-OUT
TEMP/GPIO
Single-Ended
APPLICATIONS
AMC7812B
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
GPIO
D2-
DAC7-OUTDAC8-OUT
Local
Temperature
Sensor
Remote
Temperature
Sensor
Driver
DAC9-OUTDAC10-OUT
DAC11-OUT
GPIO-6
DAC-11
GPIO-3
GPIO Controller
GPIO-0
LOAD-DAC
ALARM
Out-of-Range
Alarms
DACs Clear Logic
DAC-CLR-0
DAC-CLR-1
RESET
AGND3
AGND4
AGND1
AGND2
AVDD2
AVCC
AVDD1
A2
CS/A0
SDO/A1
SDI/SDA
SPI/I2C
IOVDD
CNVT
DVDD
DGND
SCLK/SCL
Control
Logic
DAV
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Incorporated.
SPI, QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
UNIT
AVDD to GND
0.3 to +6
DVDD to GND
0.3 to +6
IOVDD to GND
0.3 to +6
AVCC to GND
0.3 to +18
DVDD to DGND
0.3 to +6
0.3 to +6
40 to +125
40 to +150
+150
2.5
kV
1.0
kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
THERMAL INFORMATION
AMC7812B
THERMAL METRIC (1)
RGC (QFN)
PAP (HTQFP)
64 PINS
64 PINS
JA
24.1
33.7
JCtop
8.1
9.5
JB
3.2
9.0
JT
0.1
0.3
JB
3.3
8.9
JCbot
0.6
0.2
(1)
UNITS
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
AMC7812B
www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = 40C to +105C, AVDD = DVDD = 4.5 V to 5.5 V, AVCC = +15 V, AGND = DGND = 0 V, IOVDD = 2.7 V to 5.5 V,
internal 2.5-V reference, and the DAC output span = 0 V to 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC PERFORMANCE
DAC DC ACCURACY
Resolution
INL
Relative accuracy
DNL
Differential nonlinearity
TUE
Offset error
12
1
LSB
1.25
LSBs
LSB
10
mV
30
mV
mV
mV
0.3
Gain error
Bits
ppm/C
0.025
0.15
%FSR
0.15
0.3
%FSR
ppm/C
12.5
Load current
1.5
V/s
30
mA
+10
mA
10
mA
RL = infinite
10
Code 800h
Power-on overshoot
mA
nF
0.3
5
mV
0.15
nV-s
0.15
nV-s
81
nV/Hz
VPP
(1)
(2)
VREF = 2.5 V
2.6
170
V
A
The output voltage must not be greater than AVCC. See the DAC Output section for further details.
Sampled during initial release to ensure compliance; not subject to production testing.
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
2.495
2.5
2.505
UNIT
INTERNAL REFERENCE
Output voltage
Output impedance
Reference temperature coefficient
TA = 40C to +125C
10
TA = +25C, f = 1 kHz
f = 0.1 Hz to 10 Hz
0.4
25
ppm/C
mA
260
nV/Hz
13
VPP
ADC PERFORMANCE
ADC DC ACCURACY (for AVDD = 5 V)
Resolution
12
Bits
INL
Integral nonlinearity
TA = 40C to +125C
0.5
LSB
DNL
Differential nonlinearity
TA = 40C to +125C
0.5
LSB
LSB
Single-Ended Mode
Offset error
Offset error match
Gain error
0.4
External reference
LSB
5
0.4
LSB
LSB
Differential Mode
Gain error
LSB
LSB
0.5
LSB
LSB
LSB
0.5
At dc, 0 V to (2 VREF) mode
LSB
67
dB
500
kSPS
167
kSPS
SAMPLING DYNAMICS
Conversion rate
Conversion time (3)
Throughput rate
32
s
500
kSPS
(3)
VREF
2 VREF
VREF
+VREF
2 VREF
2 VREF
TA = 40C to +125C
GND 0.2
0 V to VREF mode
AVDD + 0.2
118
0 V to (2 VREF) mode
73
V
pF
pF
10
(3)
(4)
TA = 40C to +125C
Input current
VREF = 2.5 V
1.2
AVDD
145
V
A
Sampled during initial release to ensure compliance; not subject to production testing.
VIN+ or VIN must remain within GND 0.2 V and AVDD + 0.2 V; see the Analog Inputs section.
Submit Documentation Feedback
AMC7812B
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = +25C
mV
+125
2.5
1.5
40
AVDD = 5 V, TA = 40C to +125C
1.25
AVDD = 5 V, TA = 0C to +100C
Resolution
Per LSB
Conversion rate
0.125
15
ms
Resolution
40
AVDD = 5 V, TA = 0C to +100C,
TD = 40C to +150C
AVDD = 5 V, TA = 40C to +100C,
TD = 40C to +150C
Per LSB
+150
1.5
0.125
72
93
100
ms
33
44
47
ms
IOVDD = +5 V
2.1
0.3 + IOVDD
2.2
0.3 + IOVDD
IOVDD = +5 V
0.3
0.8
0.3
0.7
0.4
0.4
VOL
10
pF
IOVDD = +5 V
2.1
0.3 + IOVDD
2.2
0.3 + IOVDD
IOVDD = +5 V
0.3
0.8
0.3
0.7
pF
Input current
Input capacitance
VOH
VOL
(5)
(6)
(7)
(8)
IOVDD = +5 V, sourcing 3 mA
4.8
2.9
V
V
IOVDD = +5 V, sinking 3 mA
0.4
0.4
High-impedance leakage
10
pF
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOVDD = +5 V
2.1
0.3 + IOVDD
2.2
0.3 + IOVDD
IOVDD = +5 V
0.3
0.8
0.3
0.7
Input current
Input capacitance
VOL
pF
IOVDD = +5 V, sinking 3 mA
0.4
0.4
High-impedance leakage
10
pF
100
250
70
100
250
TIMING REQUIREMENTS
Power-on delay
Reset delay
20
ns
20
ns
POWER-SUPPLY REQUIREMENTS
AVDD
AIDD
+2.7
7.9
AVCC
12.5
mA
1.6
IVCC
+4.5
AVCC, no load, DACs at code 800h
Power dissipation
+5.5
95
mA
+18
6.5
mA
120
mW
DVDD
+2.7
+5.5
IOVDD
+2.7
+5.5
Specified performance
40
+105
Operating range
40
+125
TEMPERATURE RANGE
(9)
No DAC load, all DACs at 800h and both ADCs at the fastest auto conversion rate.
AMC7812B
www.ti.com
Single-Ended
Single-Ended/
Differential
ADC-REF-IN/CMP
AMC7812B
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
Reference
(2.5V)
REF-OUT
REF-DAC
Trigger
DAC0-OUT
DAC-0
ADC
DAC1-OUT
DAC2-OUT
D1+
GPIO-5
DAC3-OUT
Control/Limits/Status
Registers
DAC4-OUT
TEMP/GPIO
DAC5-OUTDAC6-OUT
D1-
GPIO-4
D2+
GPIO-7
GPIO
D2-
DAC7-OUTDAC8-OUT
Local
Temperature
Sensor
Remote
Temperature
Sensor
Driver
DAC9-OUTDAC10-OUT
DAC11-OUT
GPIO-6
DAC-11
GPIO-3
GPIO Controller
GPIO-0
LOAD-DAC
ALARM
Out-of-Range
Alarms
DACs Clear Logic
DAC-CLR-0
DAC-CLR-1
RESET
AGND4
AGND3
AGND2
AGND1
AVDD2
AVDD1
AVCC
A2
SDO/A1
CS/A0
SDI/SDA
SCLK/SCL
IOVDD
CNVT
DGND
DVDD
SPI/I2C
Control
Logic
DAV
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
PIN CONFIGURATIONS
DAC7-OUT
DAC6-OUT
AVDD2
AVDD1
52
51
50
49
AGND1
DAC8-OUT
54
53
AVCC1
AGND2
56
55
REF-DAC
REF-OUT
58
57
DAC10-OUT
DAC9-OUT
60
59
ALARM
DAC11-OUT
62
61
DGND2
DAC-CLR-1
64
63
RGC PACKAGE
QFN-64
(TOP VIEW)
41
CH8
CS/A0
40
CH7
SDO/A1
10
39
CH6
A2
11
38
CH5
SPI/I2C
12
37
CH4
GPIO-0
13
36
CH3
GPIO-1
14
35
CH2
GPIO-2
15
34
CH1
GPIO-3
16
33
CH0
ADC-GND
ADC-REF-IN/CMP
D1-/GPIO-4
D1+/GPIO-5
D2-/GPIO-6
D2+/GPIO-7
DAC1-OUT
DAC0-OUT
AVCC2
DAC2-OUT
AGND3
31
32
CH9
DVDD
29
42
30
27
CH10
IOVDD
28
43
25
26
CH11
DGND
23
44
24
21
CH12
SCLK/SCL
22
45
AGND4
19
CH13
SDI/SDA
20
46
DAC4-OUT
DAC3-OUT
CH14
CNVT
17
CH15
47
18
48
DAC5-OUT
DAV
DAC-CLR-0
RESET
DAC7-OUT
DAC6-OUT
AVDD2
AVDD1
52
51
50
49
AGND1
DAC8-OUT
54
53
AVCC1
AGND2
56
55
REF-DAC
REF-OUT
58
57
DAC10-OUT
DAC9-OUT
60
59
ALARM
DAC11-OUT
62
61
DGND2
DAC-CLR-1
64
63
PAP PACKAGE
HTQFP-64
(TOP VIEW)
12
37
CH4
GPIO-0
13
36
CH3
GPIO-1
14
35
CH2
GPIO-2
15
34
CH1
GPIO-3
16
33
CH0
31
CH5
SPI/I2C
32
38
ADC-GND
11
ADC-REF-IN/CMP
CH6
A2
29
39
30
10
D1-/GPIO-4
CH7
SDO/A1
D1+/GPIO-5
40
27
28
CH8
CS/A0
D2-/GPIO-6
41
D2+/GPIO-7
25
CH9
DVDD
26
42
DAC1-OUT
DAC0-OUT
CH10
IOVDD
23
43
24
AVCC2
CH11
DGND
DAC2-OUT
44
21
22
CH12
SCLK/SCL
AGND4
45
AGND3
19
CH13
SDI/SDA
20
46
DAC4-OUT
DAC3-OUT
CH14
CNVT
17
CH15
47
18
48
DAC5-OUT
DAV
DAC-CLR-0
RESET
AMC7812B
www.ti.com
PIN DESCRIPTIONS
NAME
NO.
A2
11
Slave address selection A2 for I2C when the SPI/I2C pin is low.
DESCRIPTION
ADC-GND
32
ADC-REF-IN/CMP
31
External ADC reference input when external VREF is used to drive the ADC. A compensation capacitor connection
(connect a 4.7-F capacitor between this pin and AGND) when internal VREF is used to drive the ADC.
AGND1
54
Analog ground
AGND2
55
Analog ground
AGND3
22
Analog ground
AGND4
21
Analog ground
ALARM
62
Global alarm. Open-drain output. An external 10-k, pull-up resistor is required. This pin goes low (active) when one
(or more) analog channels are out of range.
AVCC1
56
Positive analog power for DAC6-OUT, DAC7-OUT, DAC8-OUT, DAC9-OUT, DAC10-OUT, and DAC11-OUT, must be tied
to AVCC2
AVCC2
23
Positive analog power for DAC0-OUT, DAC1-OUT, DAC2-OUT, DAC3-OUT, DAC4-OUT, and DAC5-OUT, must be tied to
AVCC1
AVDD1
49
AVDD2
50
CH0 to CH15
33-48
Analog inputs of channel 0 to 15. CH4 to CH15 are single-ended. CH0, CH1, CH2, and CH3 can be programmed as
differential or single-ended.
CNVT
External conversion trigger, active low. The falling edge initiates the sampling and conversion of the ADC.
CS/A0
Chip-select signal for SPI when the SPI/I2C pin is high. Slave address selection A0 for I2C when the SPI/I2C pin is low.
D1/GPIO4
29
Remote sensor D1 negative input when D1 is enabled; GPIO-6 when D1 is disabled. Pull-up resistor required for output.
D1+/GPIO-5
30
Remote sensor D1 positive input when D1 is enabled; GPIO-7 when D1 is disabled. Pull-up resistor required for output.
D2/GPIO-6
27
Remote sensor D2 negative input when D2 is enabled; GPIO-6 when D2 is disabled. Pull-up resistor required for output.
D2+/GPIO-7
28
Remote sensor D2 positive input when D2 is enabled; GPIO-7 when D2 is disabled. Pull-up resistor required for output.
DAC0-OUT
26
DAC1-OUT
25
DAC2-OUT
24
DAC3-OUT
20
DAC4-OUT
19
DAC5-OUT
18
DAC6-OUT
51
DAC7-OUT
52
DAC8-OUT
53
DAC9-OUT
59
DAC10-OUT
60
DAC11-OUT
61
17
DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter a clear
state, the DAC latch is loaded with a predefined code, and the output is set to the corresponding level. However, the DACdata register does not change. When the DAC goes back to normal operation, the DAC latch is loaded with the previous
data from the DAC-data register and the output returns to the previous level, regardless of the status of the SLDAC-n bit.
When this pin is high, the DACs are in normal operation.
DAC-CLR-1
63
DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-1 pin enter a clear
state, the DAC latch is loaded with a predefined code, and the output is set to the corresponding level. However, the DACdata register does not change. When the DAC goes back to normal operation, the DAC latch is loaded with the previous
data from the DAC-data register and the output returns to the previous level, regardless of the status of the SLDAC-n bit.
When this pin is high, the DACs are in normal operation.
DAV
Data available indicator, active low output. In direct mode, the DAV pin goes low (active) when the conversion ends. In
auto mode, a 1-s pulse (active low) appears on this pin when a conversion cycle completes (see the Primary ADC
Operation and Registers sections for details). DAV stays high when deactivated.
DAC-CLR-0
DGND
Digital ground
DGND2
64
Digital ground
DVDD
Digital power supply (+3 V to +5 V). Must be the same value as AVDD.
GPIO-0
13
GPIO-1
14
GPIO-2
15
GPIO-3
16
General-purpose digital inputs and outputs. These pins are bidirectional open-drain, digital input and output pins, and
require an external pull-up resistor. See the General Purpose Input/Output Pins section for more details.
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
10
NAME
NO.
IOVDD
DESCRIPTION
REF-DAC
58
REF-OUT
57
RESET
Reset input, active low. A logic low on this pin causes the device to perform a hardware reset.
SCLK/SCL
Serial clock input of the main serial interface. This pin functions as the SPI clock when the SPI/I2C pin is high. This pin
functions as the I2C clock when the SPI/I2C pin is low.
SDI/SDA
Serial interface data. This pin functions as SDI for the serial peripheral interface (SPI) when the SPI/I2C pin (pin 12) is
high. This pin functions as SDA for the I2C interface when the SPI/I2C pin is low.
SDO/A1
10
SDO for SPI when the SPI/I2C pin is high. Slave address selection A1 for I2C when the SPI/I2C pin is low.
SPI/I2C
12
Interface selection pin; digital input. When this pin is tied to IOVDD, the SPI is enabled and the I2C interface is disabled.
When this pin is tied to ground, the SPI is disabled and the I2C interface is enabled.
AMC7812B
www.ti.com
Sr
SDA
tSU, STA
tSU, DAT
tBUF
tHD, STA
tHD, DAT
tLOW
SCL
tSU, STO
tHIGH
tHD,STA
tR
tF
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
= Resistor Pull-Up
Figure 1. Timing for Standard and Fast Mode Devices on the I2C Bus
TIMING CHARACTERISTICS: SDA and SCL for Standard and Fast Modes (1)
At 40C to +105C, AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, and IOVDD = 2.7 V to 5.5 V, unless otherwise
noted.
STANDARD MODE
PARAMETER
fSCL
(2)
MAX
MIN
MAX
UNIT
kHz
100
400
tLOW
4.7
1.3
tHIGH
4.0
0.6
tSU, STA
4.7
0.6
tHD,
4.0
0.6
250
100
ns
3.45
0.9
4.0
0.6
300
ns
(3)
STA
tSU, DAT
tHD,
DAT
FAST MODE
MIN
tSU, STO
tR
tF
tBUF
CB
tSP
(1)
(2)
(3)
300
ns
4.7
300 20 + 0.1 CB
1.3
400
400
pF
K.A.
K.A.
50
ns
11
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
Sr
Sr
tFDA
tRDA
SDA
tHD, DAT
tSU, STA
tHD, STA
tSU, STO
tSU, DAT
SCL
tFCL
tRCL1(1)
tHIGH
tLOW
tRCL1(1)
tRCL
tLOW
tHIGH
(1)
First rising edge of the SCL signal after Sr and after each acknowledge bit.
Figure 2. Timing for High-Speed (Hs) Mode Devices on the I2C Bus
CB = 400 pF
MIN
MAX
MIN
MAX
UNIT
3.4
1.7
MHz
fSCL (2)
tSU, STA
160
160
ns
tHD,
160
160
ns
tLOW
160
320
ns
tHIGH
60
120
ns
tSU, DAT
10
10
ns
tHD,
70
150
ns
STA
DAT
tRCL
10
40
20
80
ns
tRCL1
10
80
20
160
ns
tFCL
10
40
20
80
ns
tRDA
10
80
20
160
ns
tFDA
10
80
20
160
ns
tSU, STO
160
160
ns
10
100
400
pF
10
10
ns
CB
tSP
(1)
(2)
(3)
12
(3)
AMC7812B
www.ti.com
t10
t4
CS
t1
t7
t3
SCLK
t2
tR
tF
t5
SDI
t6
Bit 23
Bit 0
Bit 1
-- Dont Care
Bit 23 = MSB
t7
t4
CS
t1
SCLK
t3
t2
tF
t5
t6
Bit 22
Bit 23
SDI
tR
Bit 0
Bit 23
Read Command
Bit 22
t9
SDO
Bit 1
Bit 0
Any Command
Bit 23
Bit 22
Bit 1
Bit 0
t4
CS
t1
SCLK
t3
t2
tF
t5
SDI
t7
t6
Bit 23 (A)
tR
(Command to B)
(Command to A)
Bit 0 (A)
Bit 23 (B)
Bit 0 (B)
t9
Bit 23 (A)
SDO
Bit 0 (A)
13
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
MIN
MAX
UNIT
50
MHz
25
MHz
t1
20
ns
t2
ns
t3
ns
t4
ns
t5
ns
t6
ns
t7
10
ns
t8
30
ns
t9
t10
(1)
(2)
14
20
ns
ns
AMC7812B
www.ti.com
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
INL (LSB)
DNL (LSB)
0
0.2
0.4
0.2
0.4
0.6
0.6
TA = 40C
Gain = 2
VREF = 2.5V, Internal
0.8
1
512
1024
1536
2048
Code
2560
3072
3584
TA = 40C
Gain = 2
VREF = 2.5V, Internal
0.8
1
4096
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0.2
0.4
2560
3072
3584
4096
0
0.2
512
1024
1536
2048
Code
2560
3072
3584
TA = +25C
Gain = 2
VREF = 2.5V, Internal
0.8
1
4096
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0.2
0.4
512
1024
1536
2048
Code
2560
3072
3584
4096
INL (LSB)
DNL (LSB)
2048
Code
0.6
TA = +25C
Gain = 2
VREF = 2.5V, Internal
0.8
0
0.2
0.4
0.6
TA = +105C
Gain = 2
VREF = 2.5V, Internal
0.8
1
1536
0.4
0.6
1024
INL (LSB)
DNL (LSB)
512
512
1024
1536
2048
Code
2560
3072
3584
4096
0.6
TA = +105C
Gain = 2
VREF = 2.5V, Internal
0.8
1
512
1024
1536
2048
Code
2560
3072
3584
4096
15
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
INL (LSB)
DNL (LSB)
0
0.2
0.4
0.2
0.4
0.6
0.6
TA = +25C
Gain = 5
VREF = 2.5V, Internal
0.8
1
512
1024
1536
2048
Code
2560
3072
3584
TA = +25C
Gain = 5
VREF = 2.5V, Internal
0.8
1
4096
1
0.8
0.6
0.6
INL (LSB)
DNL (LSB)
1536
0
DNL Min
0.4
3072
3584
4096
INL Max
0.2
0
0.2
0.6
Gain = 2
VREF = 2.5V, Internal
0.8
1
40
25
10
20
35
50
65
80
95
INL Min
0.8
1
40
110
25
10
Gain = 2
VREF = 2.5V, Internal
20
TA (C )
0.8
0.8
0.6
0.6
INL (LSB)
0
0.2
DNL Min
Gain = 5
VREF = 2.5V, Internal
0.8
10
95
110
INL Max
0.2
0
0.2
INL Min
0.6
25
80
0.4
0.6
1
40
65
0.4
DNL Max
0.2
0.4
50
0.4
35
TA (C )
DNL (LSB)
2560
0.4
0.6
20
35
50
65
80
95
110
Gain = 5
VREF = 2.5V, Internal
0.8
1
40
TA (C )
25
10
20
35
50
65
80
95
110
TA (C )
16
2048
Code
0.4
DNL Max
0.2
0.2
1024
0.8
0.4
512
AMC7812B
www.ti.com
1
Ch0
Ch1
Ch2
Ch3
0.8
Ch8
Ch9
Ch10
Ch11
0.6
0.4
0.4
0.2
0.2
0
0.2
0.4
0.2
512
1024
1536
2048
Code
2560
3072
3584
TA = +25C
Gain = 2
VREF = 2.5V, Internal
0.8
1
4096
512
1024
1536
2048
Code
2560
3072
3584
4096
50
60
TA = +25C
Gain = 2
10884 Channels
TA = +25C
Gain = 5
10368 Channels
50
Population (%)
40
30
20
10
40
30
20
0.3
0.22
0.26
0.18
0.1
0.14
0.02
0.06
-0.02
-0.1
0.15
0.3
Gain = 5
VREF = 2.5V, Internal
0.2
Gain Error (%FSR)
0.1
0.05
0
0.05
0.1
0.15
40
-0.06
-0.14
-0.22
-0.18
-0.3
0.15
0.11
0.13
0.09
0.05
0.07
0.01
0.03
-0.01
-0.03
-0.05
-0.07
-0.11
-0.09
-0.13
-0.15
10
-0.26
Population (%)
Ch9
Ch10
Ch11
Ch6
Ch7
Ch8
0.6
TA = +25C
Gain = 2
VREF = 2.5V, Internal
0.8
Ch3
Ch4
Ch5
0.4
0.6
Ch0
Ch1
Ch2
0.8
INL (LSB)
DNL (LSB)
0.6
Ch4
Ch5
Ch6
Ch7
Gain = 2
VREF = 2.5V, Internal
25
10
20
35
50
65
80
95
110
0.1
0
0.1
0.2
0.3
40
25
TA (C )
10
20
35
50
65
80
95
110
TA (C )
17
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
0.3
0.1
0.2
Gain Error (%FSR)
0.05
0
0.05
0.1
0
0.1
TA = +25C
Gain = 2
VREF = 2.5V, Internal
0.1
0.15
4.5
7.5
10.5 12
AVCC (V)
13.5
15
16.5
TA = +25C
Gain = 5
VREF = 2.5V, Internal
0.2
0.3
18
12
13
16
17
18
35
1.4
1.6
1.2
0.8
0.4
0.2
-0.2
-0.4
-0.6
-1
0.6
0.5
0.3
0.4
-0.2
0.2
0.1
5
-0.1
-0.3
10
-0.4
10
-0.8
15
-1.4
15
20
-1.6
Population (%)
25
20
-0.5
TA = +25C
Gain = 5
VREF = 2.5V, Internal
Code = 020h
10884 Channels
30
0.6
TA = +25C
Gain = 2
VREF = 2.5V, Internal
Code = 020h
2220 Channels
-0.6
Population (%)
25
15
35
30
14
AVCC (V)
-1.2
1.5
4
3
Offset Error (mV)
1
0.5
0
0.5
2
1
0
1
2
1
Gain = 2
VREF = 2.5V, Internal
Code = 020h
1.5
2
40
25
10
20
35
50
65
80
95
110
Gain = 5
VREF = 2.5V, Internal
Code = 020h
4
5
40
TA (C )
10
20
35
50
65
80
95
110
TA (C )
18
25
AMC7812B
www.ti.com
3
Offset Error (mV)
2
1
0
1
TA = +25C
Gain = 2
VREF = 2.5V, Internal
Code = 020h
2
3
4.5
7.5
10.5
12
13.5
15
16.5
1
TA = +25C
Gain = 5
VREF = 2.5V, Internal
Code = 020h
18
12
13
14
AVCC (V)
17
18
5
TA = +25C
AVCC = 15V
Gain = 2
VREF = 2.5V, Internal
Code = 800h
2.7
FFFh
FF0h
FE0h
FC0h
F80h
4.95
Voltage Output (V)
2.8
Voltage Output (V)
16
2.9
2.6
2.5
2.4
2.3
2.2
4.9
4.85
4.8
TA = +25C
AVCC = 5V
Gain = 2
VREF = 2.5V, Internal
4.75
2.1
2
40
30
20
10
10
20
30
4.7
40
ILOAD (mA)
10
12
4.9
080h
040h
020h
010h
000h
300
4.7
4.5
IVCC (mA)
250
200
150
50
350
100
6
ILOAD (mA)
15
AVCC (V)
TA = +25C
AVCC = 15V
Gain = 2
VREF = 2.5V, Internal
0
12 11 10 9
4.3
4.1
3.9
TA = +25C
Gain = 2
VREF = 2V, External
Code = 800h
3.7
3.5
7
3.3
4.5
ILOAD (mA)
7.5
10.5
12
13.5
15
16.5
18
AVCC (V)
19
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
6.1
5.5
5.8
5.1
IVCC (mA)
4.7
4.4
4.5
4
4
All DAC Channels
TA = +25C
Gain = 2
VREF = 2.5V, Internal
3.7
3.4
3
512
1024
1536
2048
Code
2560
3072
3584
3
40
4096
25
10
20
50
65
80
95
110
60
1400
TA = +25C
30 Units
50
TA = +25C
Gain = 2
VREF = 2.5V, Internal
1200
1000
Noise (nV/ Hz)
40
30
20
800
600
400
6.5
6.1
6.3
5.9
5.5
5.7
5.1
5.3
4.9
4.5
4.7
4.1
4.3
3.9
3.5
200
3.7
10
10
100
1k
10k
Frequency (Hz)
AICC (mA)
100k
1M
20
10
5
0
5
16
TA = +25C
Gain = 2
VREF = 2.5V, Internal
RL= 2K, CL = 250pF
DAC Out SS
DAC Out LS
CS
1.5
1
Small Signal (LSB)
TA = +25C
Gain = 2
VREF = 2.5V, Internal
Code = 800h
15
VNOISE (V)
35
TA (C )
Population (%)
Gain = 2
VREF = 2.5V, Internal
Code = 800h
3.5
0.5
14
12
10
0.5
1.5
IVCC (mA)
5.4
10
15
2
20
12
16
20
12
Time (s)
Time (s)
20
AMC7812B
www.ti.com
16
1.5
Small Signal (LSB)
1
0.5
14
12
10
0.5
1.5
12
TA = +25C
Gain = 2
VREF = 2.5V, Internal
RL= 2K, CL = 250pF
DAC Out SS
DAC Out LS
CS
Time (s)
21
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
INL (LSB)
DNL (LSB)
0
0.2
0.4
0.8
1
0.4
TA = +25C
0V to VREF Mode
VREF = 2.5V, Internal
SingleEnded Mode
0.6
512
1024
1536
2048
Code
2560
3072
3584
0
0.2
TA = +25C
0V to VREF Mode
VREF = 2.5V, Internal
SingleEnded Mode
0.6
0.8
1
4096
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0.2
0.4
0.8
1
512
1024
1536
2048
Code
2560
3072
3584
0.6
0.4
0.4
0.2
0.2
INL (LSB)
DNL (LSB)
0.8
0.6
0.8
1
512
1024
1536
2048
Code
2560
3072
3584
4096
512
1024
1536
2048
Code
2560
3072
3584
4096
0
0.2
0.4
TA = +25C
0V to VREF Mode
VREF = 2.5V, Internal
Differential Mode
0.6
0.8
1
22
4096
0.8
TA = +25C
0V to VREF Mode
VREF = 2.5V, Internal
Differential Mode
3584
TA = +25C
0V to (2 VREF) Mode
VREF = 2.5V, Internal
SingleEnded Mode
0.8
0.6
3072
0.4
2560
0.2
0.2
2048
Code
0.6
4096
1536
0.4
TA = +25C
0V to (2 VREF) Mode
VREF = 2.5V, Internal
SingleEnded Mode
0.6
1024
INL (LSB)
DNL (LSB)
512
512
1024
1536
2048
Code
2560
3072
3584
4096
AMC7812B
www.ti.com
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
INL (LSB)
DNL (LSB)
0
0.2
0.4
0.8
1
512
1024
1536
2048
Code
2560
3072
3584
0.2
0.4
TA = +25C
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Differential Mode
0.6
TA = +25C
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Differential Mode
0.6
0.8
1
4096
1
0.8
0.6
0.6
1536
0.2
0
0.2
0.4
3584
4096
0
0.2
20
35
50
65
80
95
DNL Min
0V to (2 VREF) Mode
VREF = 2.5V, Internal
SingleEnded Mode
0.6
0V to VREF Mode
VREF = 2.5V, Internal
SingleEnded Mode
1
40 25 10
0.8
1
40 25 10
110 125
20
TA (C )
0.8
0.8
80
95
110 125
DNL Max
0.4
DNL (LSB)
0.4
0.2
0
0.2
0.2
0
0.2
0.4
DNL Min
0.6
0V to VREF Mode
VREF = 2.5V, Internal
Differential Mode
0.8
20
65
0.6
DNL Max
50
1
40 25 10
35
TA (C )
DNL (LSB)
3072
0.2
0.4
DNL Min
0.8
0.4
2560
0.4
DNL (LSB)
0.4
0.6
2048
Code
DNL Max
DNL Max
DNL (LSB)
1024
0.8
0.6
512
35
50
65
80
95
110 125
DNL Min
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Differential Mode
0.6
0.8
1
40 25 10
TA (C )
20
35
50
65
80
95
110 125
TA (C )
23
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
0.8
0.8
0.6
INL Max
0.4
0.4
0.2
0.2
INL (LSB)
INL (LSB)
0.6
0V to (2 VREF) Mode
VREF = 2.5V, Internal
SingleEnded Mode
0
0.2
0.4
INL Max
0
0.2
0.4
0.6
0.8
1
40 25 10
20
35
50
65
80
95
INL Min
0.6
0V to VREF Mode
VREF = 2.5V, Internal
SingleEnded Mode
INL Min
0.8
1
40 25 10
110 125
20
TA (C )
1
0.8
0.6
INL (LSB)
INL (LSB)
0
0.2
0.4
INL Min
0
0.2
INL Min
0.6
0V to VREF Mode
VREF = 2.5V, Internal
Differential Mode
0.8
20
35
50
65
80
95
0.8
1
40 25 10
110 125
20
TA (C )
3
2.5
1.5
1.5
Gain Error (LSB)
1
0.5
0
0.5
1
65
80
95
110 125
1
0.5
0
0.5
1
1.5
1.5
TA = +25C
VREF = 2.5V, Internal
SingleEnded Mode
0V to VREF Mode
0V to (2 VREF) Mode
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0V to VREF Mode
0V to (2 VREF) Mode
2.5
3
40 25 10
AVDD (V)
20
35
65
80
95
110 125
TA (C )
24
50
2.5
3
2.7
35
TA (C )
2.5
110 125
0.2
0.4
95
0.4
0.2
80
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Differential Mode
INL Max
0.6
INL Max
1
40 25 10
65
0.8
0.6
50
TA (C )
0.4
35
AMC7812B
www.ti.com
5
4
0V to VREF Mode
0V to (2 VREF) Mode
972 Units
Population (%)
1
0
1
2
10
5
40 25 10
20
35
50
65
80
95
110 125
480
482
484
486
488
490
492
494
496
498
500
502
504
506
508
510
512
514
516
518
520
TA (dB)
540
540
530
530
Conversion Frequency (kHz)
520
510
500
490
480
520
510
500
490
480
470
470
TA = +25C
460
2.7
3.1
3.5
3.9
4.3
4.7
5.1
460
40 25 10
5.5
20
AVDD (V)
35
50
65
80
95
110 125
TA (C )
12
11
11
AIDD (mA)
AIDD (mA)
10
9
8
10
7
8
6
TA = +25C
5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
7
40 25 10
AVDD (V)
20
35
50
65
80
95
110 125
TA (C )
25
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
TA = +25C
864 Units
7
40
AIDD (mA))
12
500
11.5
400
11
200
300
Frequency (kHz)
10.5
100
10
26
10
9.5
Single Channel
all DACs at code 800h
8.5
20
7.5
30
6.5
Population (%)
AIDD (mA)
AMC7812B
www.ti.com
2.501
10 Units
2.503
Voltage Output (V)
2.5005
2.501
2.499
2.5
2.4995
2.497
TA = +25C
2.495
40 25 10
20
35
50
65
80
95
2.499
2.7
110 125
3.1
3.5
3.9
TA (C )
4.3
4.7
5.1
5.5
AVDD (V)
2.505
TA = -40C to +105C
30 Units
40
Population (%)
2.503
2.501
2.499
30
20
10
2.497
25
20
15
10
10
-5
2
0
2
ILOAD (mA)
-10
-15
-25
-20
TA = +25C
2.495
10
1000
20
TA = +25C
Gain = 2
VREF = 2.5V, Internal
800
TA = +25C
15
VNOISE (V)
10
600
400
5
0
5
10
200
15
0
100
1k
10k
Frequency (Hz)
100k
1M
20
12
16
20
Time (s)
27
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
10 Units
QFN Package
2
1.5
1
0.5
0
0.5
1
1.5
2
2.5
40 25 10
20
35
50
65
80
95
1.5
1
0.5
0
0.5
1
1.5
2
20
35
50
65
80
95
110 125
TA (C )
G001
2.5
2.5
Remote Temperature Error (C)
16 units
TQFP Package
2
Local Temperature Error (C)
10 Units
QFN Package
Auto Conversion Mode Disabled
2.5
40 25 10
110 125
TA (C )
1.5
1
0.5
0
0.5
1
1.5
2
2.5
40 25 10
20
35 50
TA (C)
65
80
95
110 125
2.0
1.5
16 units
TQFP Package
Auto Conversion Mode Disabled
1.0
0.5
0.0
0.5
1.0
1.5
2.0
2.5
40 25 10
20
G000
35 50
TA (C)
65
80
95
110 125
G000
1.6
1.4
IOVDD (mA)
1.2
1
IOVDD = 2.7V
IOVDD = 5V
0.8
0.6
0.4
0.2
0
0.5
1.5
2
2.5
3
3.5
Logic Input Voltage (V)
4.5
28
AMC7812B
www.ti.com
THEORY OF OPERATION
ADC OVERVIEW
The AMC7812B has two analog-to-digital converters (ADCs): a primary ADC and a secondary ADC. The primary
ADC features a 16-channel multiplexer, an on-chip track-and-hold, and a successive approximation register
(SAR) ADC based on a capacitive digital-to-analog converter (DAC). This ADC runs at 500 kSPS and converts
the analog channel inputs, CH0 to CH15. The analog input range for the device can be selected as 0 V to VREF
or 0 V to (2 VREF). The analog input can be configured for either single-ended or differential signals. The device
has an on-chip 2.5-V reference that can be disabled when an external reference is preferred. If the internal ADC
reference is to be used elsewhere in the system, the output must first be buffered. The various monitored and
uncommitted input signals are multiplexed into the ADC. The secondary ADC is a part of the temperaturesensing function that converts the analog temperature signals.
ANALOG INPUTS
The device has 16 uncommitted analog inputs; 12 of these inputs (CH4 to CH15) are single-ended. The inputs
for CH0 to CH3 can be configured as four single-ended inputs or two fully-differential channels, depending on the
setup of the ADC channel registers, ADC Channel Register 0 and ADC Channel Register 1. See the Registers
section for details. Figure 80 shows the device equivalent input circuit. The (peak) input current through the
analog inputs depends on the sample rate, input voltage, and source impedance. The current into the device
charges the internal capacitor array during the sample period. After this capacitance is fully charged, there is no
further input current. The source of the analog input voltage must be able to charge the input capacitance to a
12-bit settling level within the acquisition time. When the converter goes into hold mode, the input impedance is
greater than 1 G.
AVDD
50W
40W
40pF
CH0
AVDD
50W
CH3
AVDD
50W
CH4
AVDD
50W
CH15
50W
40W
40pF
ADC-GND
29
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
VDM
2
VCOMMON
VIN+
VIN+
V1
VDM
2
VIN-
VINV2
(a)
(b)
30
AMC7812B
www.ti.com
Conversion Mode
Two types of ADC conversions are available: direct mode and auto mode. The conversion mode (CMODE) bit of
the AMC configuration 0 register specifies the conversion mode.
In direct mode, each analog channel within the specified group is converted a single time. After the last channel
is converted, the ADC enters an idle state and waits for a new trigger.
Auto mode is a continuous operation. In auto mode, each analog channel within the specified group is converted
sequentially and repeatedly.
The flow chart of the ADC conversion sequence in Figure 82 shows the conversion process.
Start
(Reset)
Wait for
ADC Trigger
First
Conversion
Yes
New
Trigger Occurred
or CMODE
Changed?
No
Stop Current
Conversion
Yes
Has
Input Channel
Register been
Rewritten?
No
Yes
Has
Input Threshold
Register been
Rewritten?
No
Yes
Is this the
Last
Conversion?
No
Yes
Direct
Mode?
Convert
Next Channel
No
31
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
Single-Ended
Single-Ended/
Differential
The host can access all 16, double-buffered ADC data registers, as shown in Figure 83. The conversion result
from the analog input with channel address n (where n = 0 to 15) is stored in the ADC-n-data register. When the
conversion of an individual channel completes, the data are immediately transferred into the corresponding ADCn temporary (TMPRY) register, the first stage of the data buffer. When the conversion of the last channel
completes, all data in the ADC-n TMPRY registers are simultaneously transferred into the corresponding ADC-ndata registers, the second stage of the data buffer. However, if a data transfer is in progress between any ADCn-data register and the AMC shift register, no ADC-n-data registers are updated until the data transfer is
complete. The conversion result from channel address n is stored in the ADC-n-data register. For example, the
result from channel 0 is stored in the ADC-0-data register, and the result from channel 3 is stored in the ADC-3data register.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
Out-of-Limit
Alarm
ADC
ADC-0
Temporary
ADC-0
Data
ADC-7
Temporary
ADC-7
Data
ADC-15
Temporary
ADC-15
Data
To Shift
Register
Input
Range
Selection
ICONV
(Internal
Trigger)
OR
CONVERT
(External Trigger)
DAVF Bit
DAV Pin
32
AMC7812B
www.ti.com
CONV-RATE-0
tACQ
(s)
0.375
2.375
tCONV
(s)
NAP
ENABLED
THROUGHPUT
(Single-Channel Auto Mode)
1.625
No
1.625
Yes
250 kSPS
6.375
1.625
Yes
125 kSPS
14.375
1.625
Yes
62.5 kSPS
33
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
a) External Trigger, Direct Mode:
CNVT
Set ICONV
bit to 1
First
Internal
Trigger
Read Data
Set ICONV
bit to 1
Second
Internal
Trigger
DATA
SDI
First
Trigger
Read Data
Second
Trigger
Third
Trigger
DATA
DAV
DAV
Second Conversion of
the Channels Specified in
the ADC Channel Register
First Conversion of
the Channels Specified in
the ADC Channel Register
Second Conversion of
the Channels Specified in
the ADC Channel Register
First Conversion of
the Channels Specified in
the ADC Channel Register
Third Conversion of
the Channels Specified in
the ADC Channel Register
CNVT
First
Trigger
SS
Set ICONV
bit to 1
Internal
Trigger
1ms
DAV
SDI
1m s
First Conversion of
the Channels Specified in
the ADC Channel Register
DAV
First Conversion of
the Channels Specified in
the ADC Channel Register
Second Conversion
Third Conversion
Second Conversion of
the Channels Specified in
the ADC Channel Register
Third Conversion of
the Channels Specified in
the ADC Channel Register
34
AMC7812B
www.ti.com
( )
where:
k is Boltzmann's constant,
q is the charge of the carrier,
T is the absolute temperature in Kelvin (K), and
is the ideality of the transistor as a sensor.
(1)
IHIGH
ILOW
SW2
SW1
Mux
Local
Temperature
Registers
Second ADC
and Signal
Processing
Diode
Temperature
Sensor
ILOW
SW1
Remote
Temperature
Registers
IHIGH
SW2
D+
Mux
D-
Second ADC
and Signal
Processing
VBIAS
35
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
The device has three temperature sensors: two remote (D1 and D2) and one on-chip (LT). If any sensor is not
used, it can be disabled by clearing the corresponding enable bit (bits D2EN, D1EN, and LTEN of the
temperature configuration register). When disabled, the sensors are not converted. The device continuously
monitors the selected temperature sensors in the background, leaving the user free to perform conversions on
the other channels. When one monitor cycle finishes, a signal passes to the control logic to automatically initiate
a new conversion.
The analog sensing signal is preprocessed by a low-pass filter and signal-conditioning circuitry, and then
digitized by the ADC. The resulting digital signal is further processed by the digital filter and processing unit. The
final result is stored in the LT-temperature-data register, the D1-temperature-data register, and the D2temperature-data register, respectively. The format of the final result is in twos complement, as shown in Table 2.
Note that the device measures the temperature from 40C to +150C.
Table 2. Temperature Data Format
36
TEMPERATURE (C)
DIGITAL CODE
+255.875
011111111111
+150
010010110000
+100
001100100000
+50
000110010000
+25
000011001000
+1
000000001000
000000000000
111111111000
25
111100111000
50
111001110000
100
110011100000
150
101101010000
256
100000000000
AMC7812B
www.ti.com
DECIMAL
EFF
0111 1111
7F
127
1.747977
0000 1010
0A
10
1.042759
0000 1000
08
1.035616
0000 0110
06
1.028571
0000 0100
04
1.021622
0000 0010
02
1.014765
0000 0001
01
1.011371
0000 0000
00
1.008
1111 1111
FF
1.004651
1111 1110
FE
1.001325
1111 1100
FC
0.994737
1111 1010
FA
0.988235
1111 1000
F8
0.981818
1111 0110
F6
10
0.975484
1000 0000
80
128
0.706542
BINARY
heff =
1.008 300
300 - NADJUST
NADJUST = 300 -
(2)
300 1.008
heff
where:
(3)
37
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
Filtering
Figure 88(a) and Figure 88(b) show the connection of recommended NPN or PNP transistors, respectively.
Remote junction temperature sensors are usually implemented in a noisy environment. Noise is most often
created by fast digital signals, and can corrupt measurements. The AMC7812B has a built-in 65-kHz filter on the
D+ and D inputs to minimize the effects of noise. However, a bypass capacitor placed differentially across the
inputs of the remote temperature sensor can make the application more robust against unwanted coupled
signals. If filtering is required, the capacitance between D+ and D should be limited to 330 pF or less for
optimum measurement performance. This capacitance includes any cable capacitance between the remote
temperature sensor and the device.
2N3906
2N3904
D+
D+
D-
D-
(a) NPN
(b) PNP
PROGRAMMABLE
DELAY RANGE (s)
15
0.48 to 3.84
One remote sensor is active and RC = 0, local sensor and one remote sensor are disabled
or in power-down
44
1.40 to 11.2
One remote sensor is active and RC = 1, local sensor and one remote sensor are disabled
or in power-down
93
2.97 to 23.8
One remote sensor and local sensor are active and RC = 0, one remote sensor is disabled
or in power-down
59
1.89 to 15.1
One remote sensor and local sensor are active and RC = 1, one remote sensor is disabled
or in power-down
108
3.45 to 27.65
Two remote sensors are active and RC = 0, local sensor is disabled or in power-down
88
2.81 to 22.5
Two remote sensors are active and RC = 1, local sensor is disabled or in power-down
186
5.95 to 47.6
103
3.92 to 26.38
201
6.43 to 51.45
TEMPERATURE SENSOR
38
AMC7812B
www.ti.com
REFERENCE OPERATION
This section describes the operation of the internal and external references.
Internal Reference
The device includes a 2.5-V internal reference. The internal reference is externally available at the REF-OUT pin.
A 100-pF to 10-nF capacitor is recommended between the reference output and GND for noise filtering. The
internal reference is a bipolar transistor-based, precision band-gap voltage reference. The output current is
limited by design to approximately 100 mA.
The internal reference drives all temperature sensors. When connecting the REF-OUT pin to the REF-DAC pin,
the internal reference functions as the DAC reference.
The ADC-REF-IN/CMP pin has a dual function. When an external reference is connected to this pin, the external
reference is used as the ADC reference. When a compensation capacitor (4.7 F, typical) is connected between
this pin and AGND, the internal reference is used as the ADC reference. When using an external reference to
drive the ADC, the ADC-REF-INT bit in AMC configuration register 0 must be cleared ('0') to turn off the ADC
reference buffer. When using the internal reference to drive the ADC, the ADC-REF-INT bit in AMC configuration
register 0 must be set to '1' to turn on the ADC reference buffer.
External Reference
Figure 89 shows how the external reference is used as the DAC reference when applied on the DAC-REF pin,
and as the ADC reference when applied on the ADC-REF pin. Figure 90 shows the use of the internal reference.
CH0
CH1
CH0
CH1
ADC
ADC
CH14
CH15
Ext.
Ref.
CH14
CH15
ADC-REF-IN/CMP
ADC-REF-IN/CMP
Control Logic: Bit
ADC-REF-INT = 0
REF-OUT
Reference
(2.5V)
Control Logic:
Bit PREF = 0
DAC-0
REF-DAC
REF-OUT
Reference
(2.5V)
Control Logic:
Bit PREF = 1
Ext.
Ref.
DAC0-OUT
C > 470nF
(Minimize
Inductance
to Pin)
DAC-0
REF-DAC
DAC0-OUT
39
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
DAC OPERATION
The device contains 12 DACs that provide digital control with 12 bits of resolution using an internal or external
reference. The DAC core is a 12-bit string DAC and output buffer. The DAC drives the output buffer to provide an
output voltage. Refer to the DAC configuration register for details. Figure 91 shows a function block diagram of
the DAC architecture. The DAC latch stores the code that determines the output voltage from the DAC string.
The code is transferred from the DAC-n-data register to the DAC latch when the internal DAC-load signal is
generated.
DAC
Data
Register
DAC
Latch
12-Bit
Resistor
String
VOUT
DAC Load(1)
Gain Logic
Gain Bits
(1)
Gain
Internal DAC load is generated by writing '1' to the ILDAC bit in synchronous mode. In asynchronous mode, the DAC
latch is transparent.
To Output
Amplifier
AMC7812B
www.ti.com
DAC Output
The output range is programmable from 0 V to (2 VREF) or from 0 V to (5 VREF), depending on the gain bits in
the DAC gain register. The maximum output is AVCC. The output buffer amplifier is capable of generating rail-torail voltages on its output, giving an output range of 0 V to AVCC. The source and sink capabilities of the output
amplifier can be seen in the Typical Characteristics. The slew rate is 1.5 V/s with a typical 1/4 to 3/4 scale
settling time of 3 s with the output unloaded.
Double-Buffered DAC Data Registers
There are 12 double-buffered DAC data registers. Each DAC has an internal latch preceded by a DAC data
register. Data are initially written to an individual DAC-n-data register and then transferred to the corresponding
DAC-n latch. When the DAC-n latch is updated, the output of DAC-n changes to the newly set value. When the
host reads the register memory map location labeled DAC-n-data, the value held in the DAC-n latch is returned
(not the value held in the input DAC-n-data register).
Full-Scale Output Range
The full-scale output range of each DAC is set by the product of the value of the reference voltage times the gain
of the DAC output buffer (VREF gain). The gain bits of the DAC gain register set the output range of the
individual DAC-n. The full-scale output range of each DAC is limited by the analog power supply. The maximum
output from the DAC must not be greater than AVCC, and the minimum output must not be less than AGND.
DAC Output After Power-On Reset
After power-on, the DAC output buffer is in power-down mode. The output buffer is in a Hi-Z state and the DACxOUT (where x = 0 to 11) output pin connects to the analog ground through an internal 10-k resistor. After
power-on or a hardware reset, all DAC-n-data registers, DAC-n latches, and the DAC output are set to default
values (000h).
Load DAC Latch
See Figure 91 for the structure of the DAC register and DAC latch. The contents of the DAC-n latch determine
the output level of the DAC-n pin. After writing to the DAC-n-data register, the DAC latch can be loaded either in
asynchronous or synchronous mode.
In asynchronous mode (SLDAC-n bit = '0'), data are loaded into the DAC-n latch immediately after the write
operation. In synchronous mode (SLDAC-n bit = '1'), the DAC latch updates when the synchronous DAC loading
signal occurs. Setting the ILDAC bit in AMC configuration register 0 generates the loading signal.
41
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
Don't care
OPERATION
Update DAC-n individually. The DAC-n latch and DAC-n output are immediately
updated after writing to the DAC-n-data register.
Simultaneously update all DACs by internal trigger. Writing '1' to the ILDAC bit
generates an internal load DAC trigger signal that updates the DAC-n latches and
DAC-n outputs with the contents of the corresponding DAC-n-data register.
When the SLDA-n bit is set to '1', synchronous mode is selected. The value of the DAC-n-data register is
transferred to the DAC-n latch only after an active DAC synchronous loading signal (ILDAC) occurs, which
immediately updates the DAC-n output. Under synchronous loading operation, writing data into a DAC-n-data
register changes only the value in that register, but not the content of DAC-n latch nor the output of DAC-n, until
the synchronous load signal occurs.
The DAC synchronous load is triggered by writing '1' to the ILDAC bit in AMC configuration register 0. When this
DAC synchronous load signal occurs, all DACs with the SLDA-n bit set to '1' are simultaneously updated with the
value of the corresponding DAC-n-data register. By setting the SLDA-n bit properly, several DACs can be
updated at the same time. For example, to update DAC0 and DAC1 synchronously, set bits SLDA-0 and SLDA-1
to '1' first, and then write the proper values into the DAC-0-data and DAC-1-data registers, respectively. After this
presetting, set the ILDAC bit to '1' to simultaneously load DAC0 and DAC1. The outputs of DAC0 and DAC1
change at the same time.
The device updates the DAC latch only if the latch was accessed from the last time ILDAC was issued, thereby
eliminating any unnecessary glitches. Any DAC channels that are not accessed are not reloaded again. When
the DAC latch is updated, the corresponding output changes to the new level immediately.
NOTE
When DACs are cleared by an external DAC-CLR-n or by the internal CLR bit, the DAC
latch is loaded with the predefined value of the DAC-n-CLR-setting register and the output
is set to the corresponding level immediately, regardless of the SLDA-n bit value.
However, the DAC data register does not change.
42
AMC7812B
www.ti.com
Clear DACs
DAC-n can be cleared with hardware or software, as shown in Figure 93. When DAC-n goes to a clear state, it is
immediately loaded with predefined code in the DAC-n-CLR-setting register, and the output is set to the
corresponding level to shut down the external LDMOS device. However, the DAC-n-data register does not
change. When the DAC goes back to normal operation, DAC-n is immediately loaded with the previous data from
the DAC-n-data register and the output of DACn-OUT is set back to the previous level to restore LDMOS to the
status before shutdown, regardless of the SLDAC-n bit status.
DAC
Data Register
DAC
Latch
0
DAC
1
DAC
CLR-Setting
Register
DAC-CLR-n Pin
CLR-n Bit in HW-DAC-CLR-n Register
CLR-n Bit in SW-DAC-CLR-n Register
ACLR-n Bit
Alarm Source
43
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
Alarm Operation
The device continuously monitors all analog inputs and temperatures in normal operation. When any input is out
of the specified range, an alarm triggers. When an alarm state occurs, the corresponding individual alarm bit in
the status register is set ('1'). The global alarm bit (GALR) in AMC configuration register 0 is the OR of individual
alarms, see Figure 94. When the ALARM-LATCH-DIS bit in the alarm control register is cleared ('0'), the alarm is
latched. The global alarm bit (GALR) maintains '1' until the corresponding error conditions subside and the alarm
status is read. The alarm bits are referred to as being latched because they remain set until read by software.
This design ensures that out-of-limit events cannot be missed if the software is polling the device periodically. All
bits are cleared when reading the status register, and all bits are reasserted if the out-of limit condition still exists
on the next monitoring cycle, unless otherwise noted.
CH0-ALR
Alarm
Status
Bits
GALR Bit
THERM-ALR
44
AMC7812B
www.ti.com
CHn-ALR Bit
Low-Threshold-n
Register
(lower bound)
High-ALR Bit
Temperature Data
(D1, D2, LT)
Low-ALR Bit
Low-Threshold
(lower bound)
45
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
ALARM pin
The ALARM pin is a global alarm indicator. ALARM is an open-drain pin, as Figure 97 illustrates; an external
pull-up resistor is required. When the pin is activated, it goes low. When the pin is inactive, it is in Hi-Z status.
The ALARM pin functions as an interrupt to the host so that it may query the status register to determine the
alarm source. Any alarm event (including analog inputs, temperatures, diode status, and device thermal
condition) activates the pin if the alarm is not masked (the corresponding EALR bit in the alarm control register is
'1'). When the alarm pin is masked (EN-ALARM bit is '0'), the occurrence of the event sets the corresponding
status bit in status register to '1', but does not activate the ALARM pin.
CH0-ALR Bit
ALARM
EALR-CH0 Bit
G1
D2-FAIL-ALR Bit
EALR-D2-FAIL Bit
THERM-ALR Bit
EN-ALARM Bit
46
AMC7812B
www.ti.com
Hysteresis
The device continuously monitors the analog input channels and temperatures. If any alarms are out of range
and the alarm is enabled, the alarm bit is set ('1'). However, the alarm condition is cleared only when the
conversion result returns to a value of at least hys below the value of the high threshold register, or hys above
the value of low threshold register. The hysteresis registers store the value for each analog input (CH0, CH1,
CH2, and CH3) and temperature (D1, D2, and LT). hys is the value of hysteresis that is programmable: 0 LSB to
127 LSB for analog inputs, and 0C to +31C for temperatures. For the THERM-ALR bit, the hysteresis is fixed at
8C. The hysteresis behavior is shown in Figure 98.
High Threshold
Hysteresis
Input
Hysteresis
Low Threshold
CH-FALR-CT-1
CH-FALR-CT-0
N CONSECUTIVE SAMPLES
BEFORE ALARM IS SET
16 (default)
32
64
128
256
Table 7. Consecutive Sample Number for False Alarm Protection for Temperature Channels
TEMP-FALR-CT-1
TEMP-FALR-CT-0
4 (default)
47
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
GPIO-n
GPIO-n Bit
(when writing)
ENABLE
GPIO-n Bit
(when reading)
HARDWARE RESET
Pulling the RESET pin low performs a hardware reset. When the RESET pin is low, the device enters a reset
state and all registers are set to the default values (including the power-down register). Therefore, all function
blocks (except the internal temperature sensor) are in power-down mode. On the RESET rising edge, the device
returns to the normal operating mode. After returning to this mode, all registers remain set to the default value
until a new value is written. Note that after reset, the power-down register must be properly written in order to
activate the device. Hardware reset should only be issued when DVDD reaches the minimum specification of 2.7
V or above.
SOFTWARE RESET
Software reset returns all register settings to their default values and can be performed by writing to the software
reset register. In the case of I2C communication, any value written to this register results in a reset condition. In
the case of SPI communications, only writing the specific value of 6600h to this register resets the device. See
the Registers section for details. During reset, all communication is blocked. After issuing the reset, wait at least
30 s before attempting to resume communication.
48
AMC7812B
www.ti.com
POWER-SUPPLY SEQUENCE
The preferred (not required) order for applying power is IOVDD, DVDD/AVDD, and then AVCC. All registers
initialize to the default values after these supplies are established. Communication with the device is valid after a
250-s maximum power-on reset delay. The default state of all analog blocks is off as determined by the powerdown register (6Bh). Before writing to this register, a hardware reset should be issued to ensure specified device
operation. Device communication is valid after a maximum 250-s reset delay from the RESET rising edge. If
DVDD falls below 2.7 V, the minimum supply value of DVDD, either issue a hardware or power-on reset in order
to resume proper operation.
To avoid activating the device ESD protection diodes, do not apply the GPIO-4, GPIO-5, GPIO-6, and GPIO-7
inputs before the AVDD is established. Also, if using the external reference configuration of the ADC, do not
apply ADC-REF-IN/CMP before AVDD.
A1
A2
SLAVE ADDRESS
GND
GND
GND
1100001
GND
GND
IOVDD
0101100
GND
IOVDD
GND
1100100
GND
IOVDD
IOVDD
0101110
IOVDD
GND
GND
1100010
IOVDD
GND
IOVDD
0101101
IOVDD
IOVDD
GND
1100101
IOVDD
IOVDD
IOVDD
0101111
49
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
F/S-Mode Protocol
The master initiates the data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high; see Figure 2. All I2C-compatible devices must recognize a
start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read or write direction bit
(R/W) on the SDA line. During all transmissions, the master ensures that data are valid. A valid data condition
requires that the SDA line is stable during the entire high period of the clock pulse (see Figure 2). All devices
recognize the address sent by the master and compare the address to their internal fixed addresses. Only the
slave device with a matching address generates an acknowledge (see Figure 2) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. When this acknowledge is detected, the master recognizes
that a communication link is established with a slave.
The master generates further SCL cycles to either transmit data to the slave (R/W bit is '1') or receive data from
the slave (R/W bit is '0'). In either case, the receiver must acknowledge the data sent by the transmitter.
Therefore, an acknowledge signal can either be generated by the master or by the slave, depending on which
one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue
as long as necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low-tohigh while the SCL line is high (see Figure 2). This action releases the bus and stops the communication link
with the addressed slave. All I2C-compatible devices must recognize the stop condition. When a stop condition is
received, all devices recognize that the bus is released and wait for a start condition followed by a matching
address.
Hs-Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing Hs master code 00001xxx. This
transmission is made in F/S mode at no more than 400 kbps. No device is allowed to acknowledge the Hs
master code, but all devices must recognize the Hs master code and switch their internal setting to support 3.4
Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as for F/S mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends Hs mode and switches all internal settings of the slave
devices to support F/S mode. Note that instead of using a stop condition, repeated start conditions are used to
secure the bus in Hs mode.
Address Pointer
The AMC7812B address pointer register is an 8-bit register. Each register has an address and, when accessed,
the address pointer points to the register address. All AMC7812B registers are 16 bits, consisting of a high byte
(D[15:8]) and a low byte (D[7:0]). The high byte is always accessed first, and the low byte accessed second.
When the register is accessed, the entire register is frozen until the operation on the low byte is complete. During
a write operation, the new content does not take effect until the low byte is written. In read operation, the whole
register value is frozen until the low byte is read.
The address pointer does not change after the current register is accessed. To change the pointer, the master
issues a slave address byte with the R/W bit low, followed by the pointer register byte; no additional data are
required.
Timeout Function
The device resets the serial interface if either SCL or SDA are held low for 32.8 ms (typical) between a START
and STOP condition. If the device is holding the bus low, the device releases the bus and waits for a START
condition. To avoid activating the timeout function, a communication speed of at least 1 kHz for the SCL
operating frequency must be maintained.
50
AMC7812B
www.ti.com
Figure 100 shows a diagram of this protocol. Steps for this protocol are:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends a register address.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master sends a data byte of the high byte of the register (D[15:8]).
7. The AMC7812B asserts an acknowledge signal on SDA.
8. The master sends a data byte of the low byte of the register (D[7:0]).
9. The AMC7812B asserts an acknowledge signal on SDA.
10. The master asserts a stop condition to end the transaction.
S
Device
Slave Address
Register Pointer
(Register Address)
High Byte to
Device Register
Low Byte to
Device Register
A = Acknowledge
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
51
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
A complete word must be written to a register (high byte and low byte) for proper operation, as shown in
Figure 101. Steps for this process are:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends the first register address.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master sends the high byte of the data word to the first register.
7. The AMC7812B asserts an acknowledge signal on SDA.
8. The master sends the low byte of the data word to the first register.
9. The AMC7812B asserts an acknowledge signal on SDA.
10. The master sends a second register address.
11. The AMC7812B asserts an acknowledge signal on SDA.
12. The master then sends the high byte of the data word to the second register.
13. The AMC7812B asserts an acknowledge on SDA.
14. The master sends the low byte of the data word to the second register.
15. The AMC7812B asserts an acknowledge signal on SDA.
16. The master and the AMC7812B repeat steps 4 to 15 until the last data are transferred.
17. The master then asserts a stop condition to end the transaction.
S
Device
Slave Address
Register Pointer
(1st Register Address)
Register Pointer
(2nd Register Address)
Register Pointer
(Last Register Address)
A = Acknowledge
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
52
AMC7812B
www.ti.com
Figure 102 shows a diagram of this protocol. Steps for this protocol are:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends a register address.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master device asserts a restart condition.
7. The master then sends the 7-bit AMC7812B slave address followed by a '1' for the direction bit, indicating a
read operation.
8. The AMC7812B asserts an acknowledge signal on SDA.
9. The AMC7812B then sends the high byte of the register (D[15:8]).
10. The master asserts an acknowledge signal on SDA.
11. The AMC7812B sends the low byte of the register (D[7:0]).
12. The master asserts a not acknowledge signal on SDA.
13. The master then asserts a stop condition to end the transaction.
S
Device
Slave Address
Register Pointer
(Register Address)
Device
Slave Address
Sr
A = Acknowledge
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
53
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
Reading the Same Register Multiple Times (Figure 103 and Figure 104)
Figure 103 and Figure 104 illustrate the process for this protocol. Steps for this protocol are:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends a register address.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master device asserts a restart condition.
7. The master then sends the 7-bit AMC7812B slave address followed by a '1' for the direction bit, indicating a
read operation.
8. The AMC7812B asserts an acknowledge signal on SDA.
9. The AMC7812B then sends the high byte of the register (D[15:8]).
10. The master asserts an acknowledge signal on SDA.
11. The AMC7812B sends the low byte of the register (D[7:0]).
12. The master asserts an acknowledge signal on SDA.
13. The AMC7812B and the master repeat steps 9 to 12 until the low byte of last reading is transferred.
14. After receiving the low byte of the last register, the master asserts a not acknowledge signal on SDA.
15. The master then asserts a stop condition to end the transaction.
S
Device
Slave Address
Register Pointer
(Register Address)
Sr
Device
Slave Address
A = Acknowledge
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
54
AMC7812B
www.ti.com
Device
Slave Address
Device
Slave Address
Device
Slave Address
Register Pointer
(1st Register Address)
High Byte of
1st Register
Register Pointer
(2nd Register Address)
High Byte of
2nd Register
Register Pointer
(Last Register Address)
Sr
Device
Slave Address
Low Byte of
1st Register
Sr
Device
Slave Address
Low Byte of
2nd Register
Sr
Device
Slave Address
A = Acknowledge
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
Figure 104. Read Multiple Registers Using the Reading Single Word from Any Register Method
55
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
Read frame 1
Read frame 2
Bit 23
I/O
BIT 23 (MSB)
BIT22:BIT16
BIT15:BIT0
SDI
0 (R/W)
Addr[6:0]
Data to be written
SDO
SDI
1 (R/W)
Addr[6:0]
Don't care
SDO
SDI
1 (R/W)
Addr[6:0]
Don't care
SDO
Bits[22:16]
Bits[15:0]
56
AMC7812B
www.ti.com
Standalone Operation
SDO
SDI
SCLK
CS
In standalone mode, as shown in Figure 105, each device has its own SPI bus. The serial clock can be
continuous or gated. The first CS falling edge starts the operation cycle. Exactly 24 falling clock edges must be
applied before CS is brought high again. If CS is brought high before the 24th falling SCLK edge, or if more than
24 SCLK falling edges are applied before CS is brought high, then the input data are incorrect. The device input
register is updated from the shift register on the CS rising edge, and data are automatically transferred to the
addressed registers as well. In order for another serial transfer to occur, CS must be brought low again.
Figure 106 and Figure 107 show write and read operations in standalone mode.
CS
SDI
W0
SDO
W1
XX
W3
W2
XX
XX
XX
SDI
SDO
R0
R1
D0
XX
R2
D1
Any Command
R3
D3
D2
57
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
Daisy-Chain Operation
For systems that contain several AMC7812Bs, the SDO pin can be used to daisy-chain multiple devices
together. This daisy-chain feature is useful in reducing the number of serial interface lines. The first CS falling
edge starts the operation cycle. SCLK is continuously applied to the input shift register when CS is low.
If more than 24 clock pulses are applied, data ripple out of the shift register and appear on the SDO line. These
data are clocked out on the SCLK rising edge and are valid on the falling edge. By connecting the SDO output of
the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed. Each
device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N,
where N is the total number of AMC7812Bs in the daisy chain. When the serial transfer to all devices is
complete, CS is taken high. This action transfers data from the SPI shifter registers to the internal register of
each AMC7812B in the daisy-chain and prevents any further data from being clocked in. The serial clock can be
continuous or gated. A continuous SCLK source can only be used if CS is held low for the correct number of
clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and
CS must be taken high after the final clock in order to latch the data. Figure 108 to Figure 111 illustrate the daisychain operation.
B
SDI
SDI-C
SDO-C
SDI-B
SDO-B
SDO-A
SDI-A
SDO
CS
SCLK
CS
Cycle 1
Cycle 2
Cycle 3
SDI-C
RA0
RB0
RC0
RA1
RB1
RC1
RA2
RB2
RC2
RA3
RB3
RC3
SDO-C
XX
RA0
RB0
CD0
RA1
RB1
CD1
RA2
RB2
CD2
RA3
RB3
SDI-B
XX
RA0
RB0
CD0
RA1
RB1
CD1
RA2
RB2
CD2
RA3
RB3
SDO-B
XX
XX
RA0
BD0
CD0
RA1
BD1
CD1
RA2
BD2
CD2
RA3
SDI-A
XX
XX
RA0
BD0
CD0
RA1
BD1
CD1
RA2
BD2
CD2
RA3
SDO-A
XX
XX
XX
AD0
BD0
CD0
AD1
BD1
CD1
AD2
BD2
CD2
58
AMC7812B
www.ti.com
Cycle 0
CS
Cycle 1
Cycle 2
Cycle 3
SDI-C
RA0
WB0
RC0
RA1
WB1
WC1
RA2
RB2
RC2
RA3
RB3
RC3
SDO-C
XX
RA0
WB0
CD0
RA1
WB1
XX
RA2
RB2
CD2
RA3
RB3
SDI-B
XX
RA0
WB0
CD0
RA1
WB1
XX
RA2
RB2
CD2
RA3
RB3
SDO-B
XX
XX
RA0
XX
CD0
RA1
XX
XX
RA2
BD2
CD2
RA3
SDI-A
XX
XX
RA0
XX
CD0
RA1
XX
XX
RA2
BD2
CD2
RA3
SDO-A
XX
XX
XX
AD0
XX
CD0
AD1
XX
XX
AD2
BD2
CD2
Figure 110. Mixed Operation: Reading Devices A and C, and Writing to Device B; then Reading A, and
Writing to B and C; then Reading A, B, and C Twice
Cycle 0
CS
Cycle 1
Cycle 2
Cycle 3
SDI-C
WA0
WB0
RC0
WA1
WB1
RC1
WA2
WB2
RC2
WA3
WB3
RC3
SDO-C
XX
WA0
WB0
CD0
WA1
WB1
CD1
WA2
WB2
CD2
WA3
WB3
SDI-B
XX
WA0
WB0
CD0
WA1
WB1
CD1
WA2
WB2
CD2
WA3
WB3
SDO-B
XX
XX
WA0
XX
CD0
WA1
XX
CD1
WA2
XX
CD2
WA3
SDI-A
XX
XX
WA0
XX
CD0
WA1
XX
CD1
WA2
XX
CD2
WA3
SDO-A
XX
XX
XX
XX
XX
CD0
XX
XX
CD1
XX
XX
CD2
59
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
REGISTERS
REGISTER MAP
The AMC7812B has several 16-bit registers that consist of a high byte (8 MSBs) and a low byte (8 LSBs). An 8bit register pointer points to the proper register. The pointer does not change after an operation. Table 10 lists
the registers for the AMC7812B. Note that the default values are for SPI operation; see the Register Descriptions
section for I2C default values.
Table 10. Register Map
ADDRESS
(HEX)
R/W
DEFAULT
(HEX)
00
0000
01
02
0A
R/W
0B
(1)
60
ADDRESS
(HEX)
R/W
DEFAULT
(HEX)
LT-temperature-data
45
R/W
0000
DAC-6-CLR-setting
0000
D1-temperature-data
46
R/W
0000
DAC-7-CLR-setting
0000
D2-temperature-data
47
R/W
0000
DAC-8-CLR-setting
003C (1)
Temperature configuration
48
R/W
0000
DAC-9-CLR-setting
R/W
0007 (1)
49
R/W
0000
DAC-10-CLR-setting
21
R/W
0000 (1)
4A
R/W
0000
DAC-11-CLR-setting
22
R/W
0000 (1)
4B
R/W
00FF
GPIO
23
0000
ADC-0-data
4C
R/W
2000
AMC configuration 0
24
0000
ADC-1-data
4D
R/W
0070
AMC configuration 1
25
0000
ADC-2-data
4E
R/W
0000
Alarm control
26
0000
ADC-3-data
4F
0000
Status
27
0000
ADC-4-data
50
R/W
0000
ADC channel 0
28
0000
ADC-5-data
51
R/W
0000
ADC channel 1
29
0000
ADC-6-data
52
R/W
FFFF
ADC gain
2A
0000
ADC-7-data
53
R/W
0004
AUTO-DAC-CLR-SOURCE
REGISTER
REGISTER
2B
0000
ADC-8-data
54
R/W
0000
AUTO-DAC-CLR-EN
2C
0000
ADC-9-data
55
R/W
0000
SW-DAC-CLR
2D
0000
ADC-10-data
56
R/W
0000
HW-DAC-CLR-EN-0
2E
0000
ADC-11-data
57
R/W
0000
HW-DAC-CLR-EN-1
2F
0000
ADC-12-data
58
R/W
0000
DAC configuration
30
0000
ADC-13-data
59
R/W
0000
DAC gain
31
0000
ADC-14-data
5A
R/W
0FFF
Input-0-high-threshold
32
0000
ADC-15-data
5B
R/W
0000
Input-0-low-threshold
33
R/W
0000
DAC-0-data
5C
R/W
0FFF
Input-1-high-threshold
34
R/W
0000
DAC-1-data
5D
R/W
0000
Input-1-low-threshold
35
R/W
0000
DAC-2-data
5E
R/W
0FFF
Input-2-high-threshold
36
R/W
0000
DAC-3-data
5F
R/W
0000
Input-2-low-threshold
37
R/W
0000
DAC-4-data
60
R/W
0FFF
Input-3-high-threshold
38
R/W
0000
DAC-5-data
61
R/W
0000
Input-3-low-threshold
39
R/W
0000
DAC-6-data
62
R/W
07FF
LT-high-threshold
3A
R/W
0000
DAC-7-data
63
R/W
0800
LT-low-threshold
3B
R/W
0000
DAC-8-data
64
R/W
07FF
D1-high-threshold
3C
R/W
0000
DAC-9-data
65
R/W
0800
D1-low-threshold
3D
R/W
0000
DAC-10-data
66
R/W
07FF
D2-high-threshold
3E
R/W
0000
DAC-11-data
67
R/W
0800
D2-low-threshold
3F
R/W
0000
DAC-0-CLR-setting
68
R/W
0810
Hysteresis-0
40
R/W
0000
DAC-1-CLR-setting
69
R/W
0810
Hysteresis-1
41
R/W
0000
DAC-2-CLR-setting
6A
R/W
2108
Hysteresis-2
42
R/W
0000
DAC-3-CLR-setting
6B
R/W
0000
Power-down
43
R/W
0000
DAC-4-CLR-setting
6C
1221
Device ID
44
R/W
0000
DAC-5-CLR-setting
7C
R/W
K.A.
Software reset
AMC7812B
www.ti.com
REGISTER DESCRIPTIONS
Temperature Data Registers (Read-Only)
In twos complement format, 0.125C/LSB.
LT-Temperature-Data Register (Address = 00h, Default 0000h, 0C)
Store the local temperature sensor reading in twos complement data format.
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
LT-11
LT-5
LT-4
LT-3
LT-2
LT-1
LT-0
LT-10
LT-9
LT-8
LT-7
LT-6
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
D1-11
D1-5
D1-4
D1-3
D1-2
D1-1
D1-0
D1-10
D1-9
D1-8
D1-7
D1-6
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
D2-11
D2-5
D2-4
D2-3
D2-2
D2-1
D2-0
D2-10
D2-9
D2-8
D2-7
D2-6
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
D2EN
D1EN
LTEN
RC
When using the I2C interface, the following bit configuration must be used; default = 3CFFh.
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
D2EN
D1EN
LTEN
RC
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
DEFAULT
R/W
DESCRIPTION
D2EN
R/W
D1EN
R/W
LTEN
R/W
RC
R/W
61
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
R2
R1
R0
When using the I2C interface, the following bit configuration must be used; default = 07FFh.
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
R2
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
R1
R0
R1
R0
CONVERSION TIME
128x minimum
64x minimum
32x minimum
16x minimum
8x minimum
4x minimum
2x minimum
15
One remote sensor is active and RC is '0', local sensor and one remote sensor are disabled or in power-down.
44
One remote sensor is active and RC is '1', local sensor and one remote sensor are disabled or in power-down.
93
One remote sensor and local sensor are active and RC is '0', one remote sensor is disabled or in power-down.
59
One remote sensor and local sensor are active and RC is '1', one remote sensor is disabled or in power-down.
108
Two remote sensors are active and RC is '0', local sensor is disabled or in power-down.
88
Two remote sensors are active and RC is '1', local sensor is disabled or in power-down.
186
103
201
62
AMC7812B
www.ti.com
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
NADJUST
When using the I2C, the following bit configuration must be used; default = 00FFh.
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
NADJUST
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
The NADJUST value for ideality correction is stored as shown in Table 14. EFF is the actual ideality of the
transistor being used. Refer to the Ideality Factor section for further details.
Table 14. NADJUST and EFF Values
NADJUST
BINARY
HEX
DECIMAL
EFF
0111 1111
7F
127
1.747977
0000 1010
0A
10
1.042759
0000 1000
08
1.035616
0000 0110
06
1.028571
0000 0100
04
1.021622
0000 0010
02
1.014765
0000 0001
01
1.011371
0000 0000
00
1.008 (default)
1111 1111
FF
1.004651
1111 1110
FE
1.001325
1111 1100
FC
0.994737
1111 1010
FA
0.988235
1111 1000
F8
0.981818
1111 0110
F6
10
0.975484
1000 0000
80
128
0.706542
63
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
Bits[11:0]
A11
A10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ADC data.
Four ADC data registers are available. The ADC-n-data registers (where n = 0 to 15) store the conversion results
of the corresponding analog channel-n, as shown in Table 15.
Table 15. ADC Data Register Definitions
64
INPUT CHANNEL
INPUT TYPE
CONVERSION RESULT
STORED IN
FORMAT
Channel 0
Single-ended
ADC-0-data register
Straight binary
Channel 1
Single-ended
ADC-1-data register
Straight binary
Channel 2
Single-ended
ADC-2-data register
Straight binary
Channel 3
Single-ended
ADC-3-data register
Straight binary
CH0+ or CH1
Differential
ADC-0-data register
Twos complement
CH2+ or CH3
Differential
ADC-2-data register
Twos complement
Channel 4
Single-ended
ADC-4-data register
Straight binary
Channel 5
Single-ended
ADC-5-data register
Straight binary
Channel 6
Single-ended
ADC-6-data register
Straight binary
Channel 7
Single-ended
ADC-7-data register
Straight binary
Channel 8
Single-ended
ADC-8-data register
Straight binary
Channel 9
Single-ended
ADC-9-data register
Straight binary
Channel 10
Single-ended
ADC-10-data register
Straight binary
Channel 11
Single-ended
ADC-11-data register
Straight binary
Channel 12
Single-ended
ADC-12-data register
Straight binary
Channel 13
Single-ended
ADC-13-data register
Straight binary
Channel 14
Single-ended
ADC-14-data register
Straight binary
Channel 15
Single-ended
ADC-15-data register
Straight binary
AMC7812B
www.ti.com
Bits[11:0]
D11
D10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC data.
DCLR
11
DCLR
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
DCLR
9
DCLR
8
DCLR
7
DCLR
6
DCLR
5
DCLR
4
DCLR
3
DCLR
2
DCLR
1
DCLR
0
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
For write operations, the GPIO pin operates as an output. Writing a '0' sets the GPIO-n pin to logic low. An
external pull-up resistor is required when using the GPIO pin as an output. Writing a '1' to the GPIO-n bit sets the
GPIO-n pin to high impedance.
For read operations, the GPIO pin operates as an input. Read the GPIO-n bit to receive the status of the GPIO-n
pin. Reading a '0' indicates that the GPIO-n pin is low; reading a '1' indicates that the GPIO-n pin is high.
After power-on reset, or any forced hardware or software reset, the GPIO-n bit is set to '1' and is in a highimpedance state.
When D1 is enabled, GPIO-4 and GPIO-5 are ignored.
When D2 is enabled, GPIO-6 and GPIO-7 are ignored.
65
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
NAME
DEFAULT
R/W
DESCRIPTION
15
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
14
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
ADC conversion mode bit. This bit selects between the two operating conversion modes
(direct or auto).
0 = Direct mode. The analog inputs specified in the ADC channel registers are converted
sequentially (see the ADC channel registers) one time. When one set of conversions are
complete, the ADC is idle and waits for a new trigger.
1 = Auto mode. The analog inputs specified in the AMC channel registers are converted
sequentially and repeatedly (see the ADC channel registers). When one set of conversions
are complete, the ADC multiplexer returns to the first channel and repeats the process.
Repetitive conversions continue until the CMODE bit is cleared ('0').
13
CMODE
R/W
12
ICONV
R/W
R/W
11
ILDAC
ADC-REF-INT
R/W
EN-ALARM
R/W
0 = The internal reference buffer is off and the external reference drives the ADC.
1 = The internal buffer is on and the internal reference drives the ADC. Note that a
compensation capacitor is required.
Enable ALARM pin bit.
0 = The ALARM pin is disabled
1 = The ALARM pin is enabled
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
ADC Data available flag bit. For direct mode only. Always cleared (set to '0') in Auto mode.
66
0 = The ADC conversion is in progress (data are not ready) or the ADC is in auto mode.
1 = The ADC conversions are complete and new data are available.
In direct mode, the DAVF bit sets the DAV pin. DAV goes low when DAVF is '1', and goes
high when DAVF is '0'.
In auto mode, DAVF is always cleared to '0'. However, a 1-s pulse (active low) appears
on the DAV pin when the last input specified in the ADC channel registers is converted.
DAVF is cleared to '0' in one of three ways: by reading the ADC data register, by starting a
new ADC conversion, or by writing '0' to this bit. Reading the status register does not clear
this bit.
DAVF
GALR
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
AMC7812B
www.ti.com
NAME
DEFAULT
R/W
DESCRIPTION
15
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
14
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
13
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
12
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
11
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
10
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
CONV-RATE-1
R/W
CONV-RATE-0
R/W
CH-FALR- CT-2
R/W
False alarm protection bit for CH0 to CH3. See Table 19.
CH-FALR- CT-1
R/W
False alarm protection bit for CH0 to CH3. See Table 19.
CH-FALR- CT-0
R/W
False alarm protection bit for CH0 to CH3. See Table 19.
TEMP-FALR- CT-1
R/W
False alarm protection bit for temperature monitor. See Table 20.
TEMP-FALR- CT-0
R/W
False alarm protection bit for temperature monitor. See Table 20.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
CONV-RATE-0
CH-FALR-CT-1
CH-FALR-CT-0
N CONSECUTIVE SAMPLES
BEFORE ALARM IS SET
32
64
128
256
TEMP-FALR-CT-0
4 (default)
67
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
NAME
DEFAULT
R/W
15
DESCRIPTION
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
CH0 and (CH0+, CH1) alarm enable bit.
14
EALR-CH0
R/W
0 = The alarm is masked. When the input of CH0 or (CH0+, CH1) is out of range, the
ALARM pin does not go low, but the CH0-ALR bit is set.
1 = The alarm is enabled, the CH0-ALR bit is set, and the ALARM pin goes low (if enabled)
when the input of CH0 or (CH0+, CH1) is out of range.
CH1 alarm enable bit.
13
EALR-CH1
R/W
0 = The alarm is masked. When the input of CH1 is out of range, the ALARM pin does not
go low, but the CH1-ALR bit is set.
1 = The alarm is enabled, the CH1-ALR bit is set, and the ALARM pin goes low (if enabled)
when the input of CH1 is out of range.
CH2 and (CH2+, CH3) alarm enable bit.
12
EALR-CH2
R/W
0 = The alarm is masked. When the input of CH2 or (CH2+, CH3) is out of range, the
ALARM pin does not go low, but the CH2-ALR bit is set.
1 = The alarm is enabled, the CH2-ALR bit is set, and the ALARM pin goes low (if enabled)
when the input of CH2 or (CH2+, CH3) is out of range.
CH3 alarm enable bit.
11
EALR-CH3
R/W
0 = The alarm is masked. When the input of CH3 is out of range, the ALARM pin does not
go low, but the CH3-ALR bit is set.
1 = The alarm is enabled, the CH3-ALR bit is set, and the ALARM pin goes low (if enabled)
when the input of CH3 is out of range.
Local sensor low alarm enable bit.
10
EALR-LT-Low
R/W
0 = The LT-Low alarm is masked. When LT is below the specified range, the ALARM pin
does not go low, but the LT-Low-ALR bit is set.
1 = The LT-Low alarm is enabled. When LT is below the specified range, the LT-Low-ALR
bit is set ('1') and the ALARM pin goes low (if enabled).
Local sensor high alarm enable bit.
EALR-LT-High
R/W
0 = The LT-High alarm is masked. When LT is above the specified range, the ALARM pin
does not go low, but the LT-High-ALR bit is set.
1 = The LT-High alarm is enabled. When LT is above the specified range, the LT-High-ALR
bit is set ('1') and the ALARM pin goes low (if enabled).
D1 low alarm enable bit.
EALR-D1-Low
R/W
0 = The D1-Low alarm is masked. When D1 is below the specified range, the ALARM pin
does not go low, but the D1-Low-ALR bit is set.
1 = The D1-Low alarm is enabled. When D1 is below the specified range, the D1-Low-ALR
bit is set ('1'), and the ALARM pin goes low (if enabled).
D1 high alarm enable bit.
EALR-D1-High
R/W
0 = The D1-High alarm is masked. When D1 is above the specified range, the ALARM pin
does not go low, but the D1-High-ALR bit is set.
1 = The D1-High alarm is enabled. When D1 is above the specified range, the D1-HighALR bit is set ('1'), and the ALARM pin goes low (if enabled).
D2 low alarm enable bit.
EALR-D2-Low
R/W
0 = The D2-Low alarm is masked. When D2 is below the specified range, the ALARM pin
does not go low, but the D2-Low-ALR bit is set.
1 = The D2-Low alarm is enabled. When D2 is below the specified range, the D2-Low-ALR
bit is set ('1'), and the ALARM pin goes low (if enabled).
D2 high alarm enable bit.
68
EALR-D2-High
R/W
0 = The D2-High alarm is masked. When D2 is above the specified range, the ALARM pin
does not go low, but the D2-High-ALR bit is set.
1 = The D2-High alarm is enabled. When D2 is above the specified range, the D2-HighALR bit is set ('1'), and the ALARM pin goes low (if enabled).
AMC7812B
www.ti.com
NAME
DEFAULT
R/W
DESCRIPTION
D1 fail alarm enable bit.
EALR-D1-FAIL
R/W
0 = The D1-FAIL alarm is masked. When D1 fails, the ALARM pin does not go low, but the
D1-FAIL-ALR bit is set.
1 = The D1-Fail alarm is enabled. When D1 fails, the D1-FAIL-ALR bit is set ('1'), the
ALARM pin goes low (if enabled).
D2 fail alarm enable bit.
EALR-D2-FAIL
R/W
0 = The D2-FAIL alarm is masked. When D2 fails, the ALARM pin does not go low, but the
D2-FAIL-ALR bit is set.
1 = The D2-Fail alarm is enabled. When D2 fails, the D2-FAIL-ALR bit is set ('1'), the
ALARM pin goes low (if enabled).
Alarm latch disable bit.
0 = The status register bits are latched. When an alarm occurs, the corresponding alarm bit
is set ('1'). The alarm bit remains '1' until the error condition subsides and the status
register is read. Before reading, the alarm bit is not cleared ('0') even if the alarm condition
disappears.
1 = The status register bits are not latched. When the alarm condition subsides, the alarm
bits are cleared regardless of whether the status register is read or not.
ALARMLATCH-DIS
R/W
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
69
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
NAME
DEFAULT
R/W
15
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
DESCRIPTION
14
CH0-ALR
13
CH1-ALR
12
CH2-ALR
11
CH3-ALR
10
LT-Low-ALR
LT-High-ALR
D1-Low-ALR
D1-High -ALR
70
D2-Low-ALR
AMC7812B
www.ti.com
NAME
DEFAULT
R/W
DESCRIPTION
Remote temperature reading of D2 when greater than the range flag.
D2-High -ALR
D1-FAIL-ALR
D2-FAIL-ALR
THERM-ALR
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
71
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
SE0
BIT 12
DF
(CH0+,
CH1)
SE1
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
DF
(CH2+,
CH3)
SE4
SE5
SE6
SE7
SE8
SE9
SE10
SE11
SE12
BIT 11 BIT 10
SE2
SE3
These bits specify the external analog auxiliary input channels (CH0 to CH12) to be converted. The specified
channels are accessed sequentially in order from bit 14 to bit 0. The input is converted when the corresponding
bit is set ('1').
Bit 15
Reserved
Writing to this bit causes no change. Reading this bit returns '0'.
SE0 to SE12
External single-ended analog input for CHn. The result is stored in ADC-n-data register in straight binary format.
Bit 12
DF (CH0+, CH1)
External analog differential input pair, CH0 and CH1, with CH0 as positive and CH1 as negative. The difference
of (CH0 CH1) is converted and the result is stored in the ADC-0-data register in twos complement format.
Bit 9
DF(CH2+, CH3-)
External analog differential input pair, CH2 and CH3, with CH2 as positive and CH3 as negative. The difference
of (CH2 CH3) is converted and the result is stored in the ADC-2-data register in twos complement format.
BIT 13
BIT 12
CH0 and CH1 are both accessed as single-ended inputs. Bit 12 is ignored.
DESCRIPTION
CH0, CH1, and differential pair CH0+, CH1 are not accessed.
BIT 10
BIT 9
CH2 and CH3 are both accessed as single-ended inputs. Bit 9 is ignored.
DESCRIPTION
CH2, CH3, and differential pair CH2+, CH3 are not accessed.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DESCRIPTION
72
AMC7812B
www.ti.com
SE13
SE14
SE15
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
These bits specify the external analog auxiliary input channels (CH13, CH14, and CH15) to be converted. The
specified channel is accessed sequentially in the order from bit 14 to bit 0 of ADC channel register 0, and then bit
14 to bit 12 of ADC channel register 1. The input is converted when the corresponding bit is set ('1').
Bits[14:12]
SEn
External single-ended analog input CHn. The result is stored in the ADC-n-data register in straight binary format.
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT 9
BIT 8
BIT 7
BIT 6
ADG0 ADG1 ADG2 ADG3 ADG4 ADG5 ADG6 ADG7 ADG8 ADG9
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
ADG10
ADG11
ADG12
ADG13
ADG14
ADG15
Bit 15
ADG0
0 = The analog input range of single-ended input CH0 (SE0) is 0 V to VREF or differential input pair DF (CH0+, CH1) is
VREF to +VREF
1 = The analog input range of single-ended input CH0 (SE0) is 0 V to (2 VREF) or differential input pair DF (CH0+,
CH1) is (2 VREF) to (+2 VREF)
Bit 14
ADG1
0 = The analog input range of single-ended input CH1 (SE1) is 0 V to VREF
1 = The analog input range is 0 V to (2 VREF)
Bit 13
ADG2
0 = The analog input range of single-ended input CH2 (SE2) is 0 V to VREF or differential input pair DF (CH2+, CH3) is
VREF to +VREF
1 = The analog input range of single-ended input CH2 (SE2) is 0 V to (2 VREF) or differential input pair DF (CH2+,
CH3) is (2 VREF) to (+2 VREF)
Bit 12
ADG3
0 = The analog input range of single-end input CH3 (SE3) is 0 V to VREF
1 = The analog input range is 0 V to (2 VREF)
Bit[11:0]
ADG4 to ADG15
0 = The analog input range of CHn (where n = 4 to 15) is 0 V to VREF
1 = The analog input range is 0 V to (2 VREF)
73
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
NAME
DEFAULT
R/W
15
14
CH0-ALR-CLR
R/W
13
CH1-ALR-CLR
R/W
12
CH2-ALR-CLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
74
DESCRIPTION
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
11
CH3-ALR-CLR
10
LT-Low-ALRCLR
LT-High-ALRCLR
D1-Low-ALRCLR
D1-High-ALRCLR
D2-Low-ALRCLR
D2-High-ALRCLR
R/W
D1-FAIL-CLR
R/W
D2-FAIL-CLR
R/W
THERM-ALRCLR
R/W
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
AMC7812B
www.ti.com
ACLR
11
Bits[14:3]
ACLR
10
ACLR
9
ACLR
8
ACLR
7
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
ACLR
6
ACLR
5
ACLR
4
ACLR
3
ACLR
2
ACLR
1
ACLR
0
ACLRn
Auto clear DAC-n enable bit.
0 = DAC-n is not forced to a clear state when the alarm occurs (default)
1 = DAC-n is forced to a clear state when the alarm occurs
NOTE
ACLRn is always ignored when an alarm occurs for a temperature greater than +150C
(THERM-ALR is '1'). If an alarm activates for a temperature greater than +150C, and if
the THERM-ALR-CLR bit in the AUTO-DAC-CLR-SOURCE register is set ('1'), all DACs
are forced into a clear status. However, if THERM-ALR-CLR is cleared ('0'), the over
+150C alarm does not force any DAC to a clear status.
SW-DAC-CLR Register (Read or Write, Address = 55h, Default = 0000h)
This register uses software to force the DAC into a clear state.
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
ICLR
11
Bits[14:3]
ICLR
10
ICLR
9
ICLR
8
ICLR
7
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
ICLR
6
ICLR
5
ICLR
4
ICLR
3
ICLR
2
ICLR
1
ICLR
0
ICLRn
Software clear DACn bit.
0 = DACn is restored to normal operation
1 = DACn is forced into a clear state
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR
11
10
9
8
7
6
5
4
3
2
1
0
Bits[14:3]
BIT
2
BIT
1
LSB
BIT
0
75
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT
2
BIT
1
LSB
BIT
0
H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR
11
10
9
8
7
6
5
4
3
2
1
0
Bits[14:3]
H1CLRn
Hardware clear DAC-n enable 1 bit.
0 = Pulling the DAC-CLR-1 pin low does not effect the state of DAC-n
1 = DAC-n is forced into a clear state when the DAC-CLR-1 pin goes low
Bits[11:0]
SLDA
11
SLDA
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
SLDA
9
SLDA
8
SLDA
7
SLDA
6
SLDA
5
SLDA
4
SLDA
3
SLDA
2
SLDA
1
SLDA
0
SLDA-n
DAC synchronous load enable bit.
0 = Asynchronous load is enabled. A write command to the DAC-n-data register immediately updates the DAC-n latch
and the output of DAC-n. The synchronous load DAC signal (ILDAC) does not affect DACn. the default value of SLDA-n
is '0'. The device updates the DAC latch only if the ILDAC bit is set ('1'), thereby eliminating unnecessary glitches. Any
DAC channels that are not accessed are not reloaded. When the DAC latch is updated, the corresponding output
changes to the new level immediately. Note that the SLDA-n bit is ignored in auto mode (DAC-n mode bits do not equal
'00'). In auto mode, the DAC latch is always updated asynchronously.
1 = Synchronous load is enabled. When internal load DAC signal ILDAC occurs, the DAC-n latch is loaded with the value
of the corresponding DACn-data register, and the output of DAC-n is updated immediately. The internal load DAC signal
ILDAC is generated by writing a '1' to the ILDAC bit in the AMC configuration register. In synchronous load, a write
command to the DAC-n-data register updates that register only, and does not change the DAC-n output.
NOTE
The DACs can be forced to a clear state immediately by the external DAC-CLR-n signal,
by alarm events, and by writing to the SW-DAC-CLR register. In these cases, the SLDA-n
bit is ignored.
DAC Gain Register (Read or Write, Address = 59h, Default = 0000h)
The DACn GAIN bits specify the output range of DACn.
MSB
BIT 15 BIT 14 BIT 13 BIT 12
0
Bits[11:0]
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
DAC11
GAIN
DAC10
GAIN
DAC9
GAIN
DAC8
GAIN
DAC7
GAIN
DAC6
GAIN
DAC5
GAIN
DAC4
GAIN
DAC3
GAIN
DAC2
GAIN
DAC1
GAIN
DAC0
GAIN
76
AMC7812B
www.ti.com
Analog Input Channel Threshold Registers (Read or Write, Addresses = 5Ah to 61h)
Four analog auxiliary inputs (CH0, CH1, CH2, and CH3) and three temperature sensors (LT, D1, and D2)
implement an out-of-range alarm function. Threshold-High-n and Threshold-Low-n (where n = 0, 1, 2, 3) define
the upper bound and lower bound of the nth analog input range, as shown in Table 27. This window determines
whether the nth input is out-of-range. When the input is outside the window, the corresponding CH-ALR-n bit in
the status register is set to '1'.
For normal operation, the value of Threshold-High-n must be greater than the value of Threshold-Low-n;
otherwise, CH-ALR-n is always set to '1' and an alarm is always indicated. Note that when the analog channel is
accessed as single-ended input, its threshold is in a straight binary format. However, when the channel is
accessed as a differential pair, its threshold is in twos complement format.
Table 27. Threshold Coding
INPUT CHANNEL
INPUT TYPE
THRESHOLD STORED IN
FORMAT
Channel 0
Single-ended
Input-0-Threshold-High-Byte
Input-0-Threshold-Low-Byte
Straight binary
Channel 1
Single-ended
Input-1-Threshold-High-Byte
Input-1-Threshold-Low-Byte
Straight binary
Channel 2
Single-ended
Input-2-Threshold-High-Byte
Input-2-Threshold-Low-Byte
Straight binary
Channel 3
Single-ended
Input-3-Threshold-High-Byte
Input-3-Threshold-Low-Byte
Straight binary
CH0+, CH1
Differential
Input-0-Threshold-High-Byte
Input-0-Threshold-Low-Byte
Twos complement
CH2+, CH3
Differential
Input-2-Threshold-High-Byte
Input-2-Threshold-Low-Byte
Twos complement
Bits[15:12]
THRH
11
THRH
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
THRH
9
THRH
8
THRH
7
THRH
6
THRH
5
THRH
4
THRH
3
THRH
2
THRH
1
THRH
0
Reserved
These bits are '0' when read back. Writing to these bits has no effect.
Bits[11:0]
THRHn
Data bits of the upper-bound threshold of the nth analog input.
Bits[15:12]
THRL
11
THRL
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
THRL
9
THRL
8
THRL
7
THRL
6
THRL
5
THRL
4
THRL
3
THRL
2
THRL
1
THRL
0
Reserved
These bits are '0' when read back. Writing to these bits has no effect.
Bits[11:0]
THRLn
Data bits of the lower-bound threshold of the nth analog input.
77
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
THRH
11
THRH
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
THRH
9
THRH
8
THRH
7
THRH
6
THRH
5
THRH
4
THRH
3
THRH
2
THRH
1
THRH
0
Bits[15:12] are 0' when read back. Writing these bits causes no change
LT-Low-Threshold Register (Read or Write, Address = 63h, Default = 0800h, 256C)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
THRL
11
THRL
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
THRL
9
THRL
8
THRL
7
THRL
6
THRL
5
THRL
4
THRL
3
THRL
2
THRL
1
THRL
0
Bits[15:12] are reserved. Writing to these bits causes no change. Reading these bits returns '0'.
D1-High-Threshold Register (Read or Write, Address = 64h, Default = 07FFh, +255.875C)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
THRH
11
THRH
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
THRH
9
THRH
8
THRH
7
THRH
6
THRH
5
THRH
4
THRH
3
THRH
2
THRH
1
THRH
0
Bits[15:12] are 0' when read back. Writing these bits causes no change.
D1-Low-Threshold Register (Read or Write, Address = 65h, Default = 0800h, 256C)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
THRL
11
THRL
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
THRL
9
THRL
8
THRL
7
THRL
6
THRL
5
THRL
4
THRL
3
THRL
2
THRL
1
THRL
0
Bits[15:12] are 0' when read back. Writing these bits causes no change.
D2-High-Threshold Register (Read or Write, Address = 66h, Default = 07FFh, +255.875C)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
THRH
11
THRH
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
THRH
9
THRH
8
THRH
7
THRH
6
THRH
5
THRH
4
THRH
3
THRH
2
THRH
1
THRH
0
Bits[15:12] are 0' when read back. Writing these bits causes no change.
D2-Low-Threshold Register (Read or Write, Address = 67h, Default = 0800h, 256C)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
THRL
11
THRL
10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
THRL
9
THRL
8
THRL
7
THRL
6
THRL
5
THRL
4
THRL
3
THRL
2
THRL
1
THRL
0
Bits[15:12] are 0' when read back. Writing these bits causes no change.
78
AMC7812B
www.ti.com
Hysteresis Registers
The hysteresis registers define the hysteresis in the alarm detection of an individual alarm.
Hysteresis Register 0 (Read or Write, Address = 68h, Default = 0810h, 8 LSB)
This register contains the hysteresis values for CH0 and CH1.
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
0
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
CH0CH0CH0CH0CH0CH0CH0CH1CH1CH1CH1CH1CH1CH1HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0
Bits[14:8]
LSB
BIT 0
0
CH0-HYS-n
Hysteresis of CH0, 1 LSB per step.
Bits[7:1]
CH1-HYS-n
Hysteresis of CH1, 1 LSB per step.
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
CH2CH2CH2CH2CH2CH2CH2CH3CH3CH3CH3CH3CH3CH3HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0
Bits[14:8]
LSB
BIT 0
0
CH2-HYS-n
Hysteresis of CH2, 1 LSB per step.
Bits[7:1]
CH3-HYS-n
Hysteresis of CH3, 1 LSB per step.
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 0
D2D2D2D2D2D1D1D1D1D1LTLTLTLTLTHYS-7 HYS-6 HYS-5 HYS-4 HYS-3 HYS-7 HYS-6 HYS-5 HYS-4 HYS-3 HYS-7 HYS-6 HYS-5 HYS-4 HYS-3
Bits[14:10]
D2-HYS-n
Hysteresis of D2, 1C per step. Note that bits D2-HYS-[2:0] are always '0'.
Bits[9:5]
D1-HYS-n
Hysteresis of D1, 1C per step. Note that bits D1-HYS-[2:0] are always '0'.
Bits[4:0]
LT-HYS-n
Hysteresis of LT, 1C per step. Note that bits LT-HYS-[2:0] are always '0'.
79
AMC7812B
SBAS625A SEPTEMBER 2013 REVISED SEPTEMBER 2013
www.ti.com
PADC
Bit 14
PREF
PDAC
0
PDAC
1
PDAC
2
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
PDAC
3
PDAC
4
PDAC
5
PDAC
6
PDAC
7
PDAC
8
PDAC
9
PDAC
10
PDAC
11
LSB
BIT 0
0
PADC
Power-down mode control bit.
0 = The ADC is inactive in low-power mode.
1 = The ADC is in normal operating mode.
Bit 13
PREF
Internal reference in power-down mode control bit.
0 = The reference buffer amplifier is inactive in low-power mode.
1 = The reference buffer amplifier is powered on.
Bits[12:1]
PDACn
DACn power-down control bit.
0 = DACn is inactive in low-power mode and its output buffer amplifier is in a Hi-Z state. The output pin of DACn is
internally switched from the buffer output to the analog ground through an internal resistor.
1 = DACn is in normal operating mode.
80
AMC7812B
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2013) to Revision A
Page
81
www.ti.com
13-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
Op Temp (C)
Device Marking
(3)
(4/5)
AMC7812BSPAP
ACTIVE
HTQFP
PAP
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC7812B
AMC7812BSPAPR
ACTIVE
HTQFP
PAP
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC7812B
AMC7812BSRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC7812B
AMC7812BSRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC7812B
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
www.ti.com
13-Sep-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
10-Feb-2014
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
AMC7812BSPAPR
HTQFP
PAP
64
1000
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
AMC7812BSRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
AMC7812BSRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
10-Feb-2014
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AMC7812BSPAPR
HTQFP
PAP
64
1000
367.0
367.0
55.0
AMC7812BSRGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
AMC7812BSRGCT
VQFN
RGC
64
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
www.ti.com/automotive
Amplifiers
amplifier.ti.com
www.ti.com/communications
Data Converters
dataconverter.ti.com
www.ti.com/computers
DLP Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
www.ti.com/energy
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Sicherheit
www.ti.com/security
Power Mgmt
power.ti.com
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
www.ti.com/video
RFID
www.ti-rfid.com
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright 2014, Texas Instruments Incorporated