Silicon Labs Ultra Low Power Bank
Silicon Labs Ultra Low Power Bank
Silicon Labs Ultra Low Power Bank
RF power consumption
18.5 mA receive
18 mA @ +1 dBm transmit
30 mA @ +13 dBm transmit
85 mA @ +20 dBm transmit
Data rate = 0.123 to 256 kbps
Auto-frequency calibration (AFC)
Antenna diversity and transmit/receive switch control
Programmable packet handler
TX and RX 64-byte FIFOs
Frequency hopping capability
On-chip crystal tuning
Memory
Digital Peripherals
Metering-Specific Peripherals
On-Chip Debug
On-chip debug circuitry facilitates full-speed, non-intrusive, in-system debug (no emulator required)
Provides 4 breakpoints, single stepping
Zurücksetzen
UART
Timers
0/1/2/3
VBAT
VREG
Priority
Crossbar
Decoder
PCA/
WDT
C2D
Digital Peripherals
128/64/32/16 kByte
ISP Flash Program
Memory
Debug /
Programming
Hardware
VDC
CIP-51 8051
Controller Core
Wake
VDD
Precision internal oscillators: 24.5 MHz with 2% accuracy supports UART operation; spread-spectrum mode for reduced EMI
Low power internal oscillator: 20 MHz
External oscillator: Crystal, RC, C, CMOS clock
smaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal
LFO with three independent alarms
Power On
Reset/PMU
VBAT
Packages
C2CK/RST
Clock Sources
EZRadioPRO Transceiver
DMA
SMBus
Analog
Power
CRC
Engine
SPI 0
Digital
Power
AES
Engine
Port 0-1
Drivers
16
Port 2
Drivers
Port 3-6
Drivers
32
P0.0...P1.7
P2.4...P2.7
P3.0...P6.7
Port 7
Driver
P7.0/C2D
RF XCVR
(240-960 MHz,
+20/+13 dBm)
Crossbar Control
PA
VCO
LCD (4x32)
TX
Encoder
VBATDC
IND
DC/DC Buck
Converter
Precision
24.5 MHz
Oscillator
GNDDC
CAP
LCD Charge
Pump
XTAL1
XTAL2
GND
SYSCLK
XTAL3
XTAL4
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
SFR
Bus
EMIF
AGC
LNA
Mixer
PGA
Analog Peripherals
Internal
External
VREF
VREF
ADC
Digital
Modem
A
M
U
X
12-bit
75ksps
ADC
VDD
VREF
Temp
Sensor
Delta
Sigma
Modulator
Digital
Logic
SDN
nIRQ
GPIOx
GND
CP0, CP0A
System Clock
Configuration
RXp
RXn
Pulse Counter
EZRadioPro SPI 1
CP1, CP1A
+
-
+
-
30 MHz
XOUT
XIN
Comparators
Si102x/3x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si102x/3x
Rev. 0.3
Si102x/3x
Table of Contents
1. System Overview ..................................................................................................... 26
1.1. Typical Connection Diagram ............................................................................. 29
1.2. CIP-51 Microcontroller Core .......................................................................... 30
1.2.1. Fully 8051 Compatible .............................................................................. 30
1.2.2. Improved Throughput................................................................................ 30
1.2.3. Additional Features ................................................................................... 30
1.3. Port Input/Output ............................................................................................... 31
1.4. Serial Ports ........................................................................................................ 32
1.5. Programmable Counter Array............................................................................ 32
1.6. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode................................................................ 33
1.7. Programmable Current Reference (IREF0)....................................................... 34
1.8. Comparators...................................................................................................... 34
2. Ordering Information ............................................................................................... 36
3. Pinout and Package Definitions ............................................................................. 37
3.1. LGA-85 Package Specifications ........................................................................ 46
3.1.1. Package Drawing ...................................................................................... 46
3.1.2. Land Pattern.............................................................................................. 48
3.1.3. Soldering Guidelines ................................................................................. 49
4. Electrical Characteristics ........................................................................................ 50
4.1. Absolute Maximum Specifications..................................................................... 50
4.2. MCU Electrical Characteristics .......................................................................... 51
4.3. EZRadioPRO Peripheral Electrical Characteristics......................................... 70
4.4. Definition of Test Conditions for the EZRadioPRO Peripheral .......................... 77
5. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode ................................................................... 78
5.1. Output Code Formatting .................................................................................... 78
5.2. Modes of Operation ........................................................................................... 80
5.2.1. Starting a Conversion................................................................................ 80
5.2.2. Tracking Modes......................................................................................... 80
5.2.3. Burst Mode................................................................................................ 82
5.2.4. Settling Time Requirements...................................................................... 83
5.2.5. Gain Setting .............................................................................................. 83
5.3. 8-Bit Mode ......................................................................................................... 84
5.4. 12-Bit Mode ....................................................................................................... 84
5.5. Low Power Mode............................................................................................... 85
5.6. Programmable Window Detector....................................................................... 91
5.6.1. Window Detector In Single-Ended Mode .................................................. 93
5.6.2. ADC0 Specifications ................................................................................. 94
5.7. ADC0 Analog Multiplexer .................................................................................. 95
5.8. Temperature Sensor.......................................................................................... 97
5.8.1. Calibration ................................................................................................. 97
5.9. Voltage and Ground Reference Options ......................................................... 100
Rev. 0.3
Si102x/3x
5.10. External Voltage Reference........................................................................... 101
5.11. Internal Voltage Reference............................................................................ 101
5.12. Analog Ground Reference............................................................................. 101
5.13. Temperature Sensor Enable ......................................................................... 101
5.14. Voltage Reference Electrical Specifications .................................................. 102
6. Comparators........................................................................................................... 103
6.1. Comparator Inputs........................................................................................... 103
6.2. Comparator Outputs ........................................................................................ 104
6.3. Comparator Response Time ........................................................................... 105
6.4. Comparator Hysterisis ..................................................................................... 105
6.5. Comparator Register Descriptions .................................................................. 106
7. Programmable Current Reference (IREF0).......................................................... 110
7.1. PWM Enhanced Mode..................................................................................... 110
7.2. IREF0 Specifications ....................................................................................... 111
7.3. Comparator0 and Comparator1 Analog Multiplexers ...................................... 112
8. CIP-51 Microcontroller........................................................................................... 115
8.1. Instruction Set.................................................................................................. 116
8.1.1. Instruction and CPU Timing .................................................................... 116
8.2. CIP-51 Register Descriptions .......................................................................... 121
9. Memory Organization ............................................................................................ 124
9.1. Program Memory............................................................................................. 124
9.1.1. MOVX Instruction and Program Memory ................................................ 127
9.2. Data Memory ................................................................................................... 127
9.2.1. Internal RAM ........................................................................................... 128
9.2.2. External RAM .......................................................................................... 128
10. External Data Memory Interface and On-Chip XRAM ....................................... 130
10.1. Accessing XRAM........................................................................................... 130
10.1.1. 16-Bit MOVX Example .......................................................................... 130
10.1.2. 8-Bit MOVX Example ............................................................................ 130
10.2. Configuring the External Memory Interface ................................................... 131
10.3. Port Configuration.......................................................................................... 131
10.4. Multiplexed and Non-Multiplexed Selection................................................... 135
10.4.1. Multiplexed Configuration...................................................................... 135
10.4.2. Non-Multiplexed Configuration.............................................................. 135
10.5. Memory Mode Selection................................................................................ 136
10.5.1. Internal XRAM Only .............................................................................. 137
10.5.2. Split Mode without Bank Select............................................................. 137
10.5.3. Split Mode with Bank Select.................................................................. 137
10.5.4. External Only......................................................................................... 137
10.6. Timing .......................................................................................................... 138
10.6.1. Non-Multiplexed Mode .......................................................................... 140
10.6.2. Multiplexed Mode .................................................................................. 143
11. Direct Memory Access (DMA0)........................................................................... 147
11.1. DMA0 Architecture ........................................................................................ 148
11.2. DMA0 Arbitration ........................................................................................... 149
Rev. 0.3
Si102x/3x
11.2.1. DMA0 Memory Access Arbitration ........................................................ 149
11.2.2. DMA0 Channel Arbitration .................................................................... 149
11.3. DMA0 Operation in Low Power Modes ......................................................... 149
11.4. Transfer Configuration................................................................................... 150
12. Cyclic Redundancy Check Unit (CRC0)............................................................. 161
12.1. 16-bit CRC Algorithm..................................................................................... 161
12.3. Preparing for a CRC Calculation ................................................................... 164
12.4. Performing a CRC Calculation ...................................................................... 164
12.5. Accessing the CRC0 Result .......................................................................... 164
12.6. CRC0 Bit Reverse Feature............................................................................ 168
13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)............................... 169
13.1. Polynomial Specification................................................................................ 169
13.2. Endianness.................................................................................................... 170
13.3. CRC Seed Value ........................................................................................... 171
13.4. Inverting the Final Value................................................................................ 171
13.5. Flipping the Final Value ................................................................................. 171
13.6. Using CRC1 with SFR Access ...................................................................... 172
13.7. Using the CRC1 module with the DMA ......................................................... 172
14. Advanced Encryption Standard (AES) Peripheral ............................................ 176
14.1. Hardware Description .................................................................................... 177
14.1.1. AES Encryption/Decryption Core .......................................................... 178
14.1.2. Data SFRs............................................................................................. 178
14.1.3. Configuration sfrs .................................................................................. 179
14.1.4. Input Multiplexer.................................................................................... 179
14.1.5. Output Multiplexer ................................................................................. 179
14.1.6. Internal State Machine .......................................................................... 179
14.2. Key Inversion................................................................................................. 180
14.2.1. Key Inversion using DMA...................................................................... 181
14.2.2. Key Inversion using SFRs..................................................................... 182
14.2.3. Extended Key Output Byte Order.......................................................... 183
14.2.4. Using the DMA to unwrap the extended Key ........................................ 184
14.3. AES Block Cipher .......................................................................................... 185
14.4. AES Block Cipher Data Flow......................................................................... 186
14.4.1. AES Block Cipher Encryption using DMA ............................................. 187
14.4.2. AES Block Cipher Encryption using SFRs ............................................ 188
14.5. AES Block Cipher Decryption........................................................................ 189
14.5.1. AES Block Cipher Decryption using DMA............................................. 189
14.5.2. AES Block Cipher Decryption using SFRs............................................ 190
14.6. Block Cipher Modes ...................................................................................... 191
14.6.1. Cipher Block Chaining Mode................................................................. 191
14.6.2. CBC Encryption Initialization Vector Location....................................... 193
14.6.3. CBC Encryption using DMA .................................................................. 193
14.6.4. CBC Decryption .................................................................................... 196
14.6.5. Counter Mode ....................................................................................... 199
14.6.6. CTR Encryption using DMA .................................................................. 201
Rev. 0.3
Si102x/3x
15. Encoder/Decoder ................................................................................................. 208
15.1. Manchester Encoding.................................................................................... 209
15.2. Manchester Decoding.................................................................................... 210
15.3. Three-out-of-Six Encoding............................................................................ 211
15.4. Three-out-of-Six Decoding ............................................................................ 212
15.5. Encoding/Decoding with SFR Access ........................................................... 213
15.6. Decoder Error Interrupt.................................................................................. 213
15.7. Using the ENC0 module with the DMA.......................................................... 214
16. Special Function Registers................................................................................. 217
16.1. SFR Paging ................................................................................................... 217
16.2. Interrupts and SFR Paging ............................................................................ 217
16.3. SFR Page Stack Example ............................................................................. 219
17. Interrupt Handler.................................................................................................. 238
17.1. Enabling Interrupt Sources ............................................................................ 238
17.2. MCU Interrupt Sources and Vectors.............................................................. 238
17.3. Interrupt Priorities .......................................................................................... 239
17.4. Interrupt Latency............................................................................................ 239
17.5. Interrupt Register Descriptions ...................................................................... 241
17.6. External Interrupts INT0 and INT1................................................................. 248
18. Flash Memory....................................................................................................... 250
18.1. Programming the Flash Memory ................................................................... 250
18.1.1. Flash Lock and Key Functions .............................................................. 250
18.1.2. Flash Erase Procedure ......................................................................... 250
18.1.3. Flash Write Procedure .......................................................................... 251
18.1.4. Flash Write Optimization ....................................................................... 252
18.2. Non-volatile Data Storage ............................................................................. 253
18.3. Security Options ............................................................................................ 253
18.4. Determining the Device Part Number at Run Time ....................................... 255
18.5. Flash Write and Erase Guidelines ................................................................. 256
18.5.1. VDD Maintenance and the VDD Monitor .............................................. 256
18.5.2. PSWE Maintenance .............................................................................. 258
18.5.3. System Clock ........................................................................................ 258
18.6. Minimizing Flash Read Current ..................................................................... 259
19. Power Management ............................................................................................. 264
19.1. Normal Mode ................................................................................................. 265
19.2. Idle Mode....................................................................................................... 265
19.3. Stop Mode ..................................................................................................... 266
19.4. Low Power Idle Mode .................................................................................... 266
19.5. Suspend Mode .............................................................................................. 270
19.6. Sleep Mode ................................................................................................... 270
19.7. Configuring Wakeup Sources........................................................................ 271
19.8. Determining the Event that Caused the Last Wakeup................................... 271
19.9. Power Management Specifications ............................................................... 275
20. On-Chip DC-DC Buck Converter (DC0).............................................................. 276
20.1. Startup Behavior............................................................................................ 277
Rev. 0.3
Si102x/3x
20.4. Optimizing Board Layout ............................................................................... 278
20.5. Selecting the Optimum Switch Size............................................................... 278
20.6. DC-DC Converter Clocking Options .......................................................... 278
20.7. Bypass Mode................................................................................................. 279
20.8. DC-DC Converter Register Descriptions ....................................................... 279
20.9. DC-DC Converter Specifications ................................................................... 283
21. Voltage Regulator (VREG0)................................................................................. 284
21.1. Voltage Regulator Electrical Specifications ................................................... 284
22. Reset Sources ...................................................................................................... 285
22.1. Power-On Reset ............................................................................................ 286
22.2. Power-Fail Reset ........................................................................................... 287
22.3. External Reset ............................................................................................... 290
22.4. Missing Clock Detector Reset ....................................................................... 290
22.5. Comparator0 Reset ....................................................................................... 290
22.6. PCA Watchdog Timer Reset ......................................................................... 290
22.7. Flash Error Reset .......................................................................................... 291
22.8. SmaRTClock (Real Time Clock) Reset ......................................................... 291
22.9. Software Reset .............................................................................................. 291
23. Clocking Sources................................................................................................. 293
23.1. Programmable Precision Internal Oscillator .................................................. 294
23.2. Low Power Internal Oscillator........................................................................ 294
23.3. External Oscillator Drive Circuit..................................................................... 294
23.3.1. External Crystal Mode........................................................................... 294
23.3.2. External RC Mode................................................................................. 296
23.3.3. External Capacitor Mode....................................................................... 297
23.3.4. External CMOS Clock Mode ................................................................. 297
23.4. Special Function Registers for Selecting and
Configuring the System Clock ....................................................................... 298
24. SmaRTClock (Real Time Clock).......................................................................... 302
24.1. SmaRTClock Interface .................................................................................. 303
24.1.1. SmaRTClock Lock and Key Functions.................................................. 304
24.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock
Internal Registers ................................................................................. 304
24.1.3. SmaRTClock Interface Autoread Feature ............................................. 304
24.1.4. RTC0ADR Autoincrement Feature........................................................ 304
24.2. SmaRTClock Clocking Sources .................................................................... 307
24.2.1. Using the SmaRTClock Oscillator with a Crystal or
External CMOS Clock ........................................................................... 307
24.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode..................... 308
24.2.3. Using the Low Frequency Oscillator (LFO) ........................................... 308
24.2.4. Programmable Load Capacitance......................................................... 308
24.2.5. Automatic Gain Control (Crystal Mode Only) and
SmaRTClock Bias Doubling ................................................................. 309
24.2.6. Missing SmaRTClock Detector ............................................................. 311
24.2.7. SmaRTClock Oscillator Crystal Valid Detector ..................................... 311
Rev. 0.3
Si102x/3x
24.3. SmaRTClock Timer and Alarm Function ....................................................... 311
24.3.1. Setting and Reading the SmaRTClock Timer Value ............................. 311
24.3.2. Setting a SmaRTClock Alarm ............................................................... 312
24.3.3. Software Considerations for using the
SmaRTClock Timer and Alarm ............................................................. 312
25. Low-Power Pulse Counter .................................................................................. 319
25.1. Counting Modes ............................................................................................ 320
25.2. Reed Switch Types........................................................................................ 321
25.3. Programmable Pull-Up Resistors .................................................................. 322
25.4. Automatic Pull-Up Resistor Calibration ......................................................... 324
25.5. Sample Rate.................................................................................................. 324
25.6. Debounce ...................................................................................................... 324
25.7. Reset Behavior .............................................................................................. 325
25.8. Wake up and Interrupt Sources..................................................................... 325
25.9. Real-Time Register Access ........................................................................... 326
25.10. Advanced Features ..................................................................................... 326
25.10.1. Quadrature Error ................................................................................. 326
25.10.2. Flutter Detection.................................................................................. 327
26. LCD Segment Driver (Si102x Only) .................................................................... 341
26.1. Configuring the LCD Segment Driver ............................................................ 341
26.2. Mapping Data Registers to LCD Pins............................................................ 342
26.3. LCD Contrast Adjustment.............................................................................. 345
26.3.1. Contrast Control Mode 1 (Bypass Mode).............................................. 345
26.3.2. Contrast Control Mode 2 (Minimum Contrast Mode) ............................ 346
26.3.3. Contrast Control Mode 3 (Constant Contrast Mode)............................. 346
26.3.4. Contrast Control Mode 4 (Auto-Bypass Mode) ..................................... 347
26.4. Adjusting the VBAT Monitor Threshold ......................................................... 351
26.5. Setting the LCD Refresh Rate ....................................................................... 352
26.6. Blinking LCD Segments................................................................................. 353
26.7. Advanced LCD Optimizations........................................................................ 355
27. Port Input/Output ................................................................................................. 358
27.1. Port I/O Modes of Operation.......................................................................... 359
27.1.1. Port Pins Configured for Analog I/O...................................................... 359
27.1.2. Port Pins Configured For Digital I/O...................................................... 359
27.1.3. Interfacing Port I/O to High Voltage Logic............................................. 360
27.1.4. Increasing Port I/O Drive Strength ........................................................ 360
27.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 360
27.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 360
27.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 361
27.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 361
27.3. Priority Crossbar Decoder ............................................................................. 362
27.4. Port Match ..................................................................................................... 368
27.5. Special Function Registers for Accessing and Configuring Port I/O ............. 370
28. SMBus................................................................................................................... 388
28.1. Supporting Documents .................................................................................. 389
Rev. 0.3
Si102x/3x
28.2. SMBus Configuration..................................................................................... 389
28.3. SMBus Operation .......................................................................................... 389
28.3.1. Transmitter Vs. Receiver....................................................................... 390
28.3.2. Arbitration.............................................................................................. 390
28.3.3. Clock Low Extension............................................................................. 390
28.3.4. SCL Low Timeout.................................................................................. 390
28.3.5. SCL High (SMBus Free) Timeout ......................................................... 391
28.4. Using the SMBus........................................................................................... 391
28.4.1. SMBus Configuration Register.............................................................. 391
28.4.2. SMB0CN Control Register .................................................................... 395
28.4.3. Hardware Slave Address Recognition .................................................. 397
28.4.4. Data Register ........................................................................................ 400
28.5. SMBus Transfer Modes................................................................................. 400
28.5.1. Write Sequence (Master) ...................................................................... 400
28.5.2. Read Sequence (Master) ...................................................................... 401
28.5.3. Write Sequence (Slave) ........................................................................ 402
28.5.4. Read Sequence (Slave) ........................................................................ 403
28.6. SMBus Status Decoding................................................................................ 404
29. UART0 ................................................................................................................... 409
29.1. Enhanced Baud Rate Generation.................................................................. 410
29.2. Operational Modes ........................................................................................ 411
29.2.1. 8-Bit UART ............................................................................................ 411
29.2.2. 9-Bit UART ............................................................................................ 411
29.3. Multiprocessor Communications ................................................................... 412
30. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 418
30.1. Signal Descriptions........................................................................................ 419
30.1.1. Master Out, Slave In (MOSI)................................................................. 419
30.1.2. Master In, Slave Out (MISO)................................................................. 419
30.1.3. Serial Clock (SCK) ................................................................................ 419
30.1.4. Slave Select (NSS) ............................................................................... 419
30.2. SPI0 Master Mode Operation ........................................................................ 419
30.3. SPI0 Slave Mode Operation .......................................................................... 421
30.4. SPI0 Interrupt Sources .................................................................................. 422
30.5. Serial Clock Phase and Polarity .................................................................... 422
30.6. SPI Special Function Registers ..................................................................... 424
31. EZRadioPRO Serial Interface ........................................................................... 431
31.1. Signal Descriptions........................................................................................ 432
31.1.1. Master Out, Slave In (MOSI)................................................................. 432
31.1.2. Master In, Slave Out (MISO)................................................................. 432
31.1.3. Serial Clock (SCK) ................................................................................ 432
31.1.4. Slave Select (NSS) ............................................................................... 432
31.2. SPI1 Master Mode Operation ........................................................................ 433
31.3. SPI Slave Operation on the EZRadioPRO Peripheral Side........................... 433
31.4. SPI1 Interrupt Sources .................................................................................. 433
31.5. Serial Clock Phase and Polarity .................................................................... 434
Rev. 0.3
Si102x/3x
31.6. Using SPI1 with the DMA .............................................................................. 435
31.7. Master Mode SPI1 DMA Transfers................................................................ 435
31.8. Master Mode Bidirectional Data Transfer ...................................................... 435
31.9. Master Mode Unidirectional Data Transfer.................................................... 437
31.10. SPI Special Function Registers ................................................................... 437
32. EZRadioPRO 240960 MHz Transceiver.......................................................... 443
32.1. EZRadioPRO Operating Modes .................................................................... 444
32.1.1. Operating Mode Control ....................................................................... 445
32.2. Interrupts ...................................................................................................... 447
32.3. System Timing............................................................................................... 448
32.3.1. Frequency Control................................................................................. 449
32.3.2. Frequency Programming....................................................................... 449
32.3.3. Easy Frequency Programming for FHSS.............................................. 451
32.3.4. Automatic State Transition for Frequency Change ............................... 452
32.3.5. Frequency Deviation ............................................................................. 452
32.3.6. Frequency Offset Adjustment................................................................ 453
32.3.7. Automatic Frequency Control (AFC) ..................................................... 453
32.3.8. TX Data Rate Generator ....................................................................... 455
32.4. Modulation Options........................................................................................ 455
32.4.1. Modulation Type.................................................................................... 455
32.4.2. Modulation Data Source........................................................................ 456
32.4.3. PN9 Mode ............................................................................................. 460
32.5. Internal Functional Blocks ............................................................................. 460
32.5.1. RX LNA ................................................................................................. 460
32.5.2. RX I-Q Mixer ......................................................................................... 460
32.5.3. Programmable Gain Amplifier ............................................................... 460
32.5.4. ADC ..................................................................................................... 461
32.5.5. Digital Modem ....................................................................................... 461
32.5.6. Synthesizer ........................................................................................... 462
32.5.7. Power Amplifier ..................................................................................... 463
32.5.8. Crystal Oscillator ................................................................................... 464
32.5.9. Regulators............................................................................................. 464
32.6. Data Handling and Packet Handler ............................................................... 465
32.6.1. RX and TX FIFOs.................................................................................. 465
32.6.2. Packet Configuration............................................................................. 466
32.6.3. Packet Handler TX Mode ...................................................................... 467
32.6.4. Packet Handler RX Mode...................................................................... 467
32.6.5. Data Whitening, Manchester Encoding, and CRC ................................ 469
32.6.6. Preamble Detector ................................................................................ 470
32.6.7. Preamble Length................................................................................... 470
32.6.8. Invalid Preamble Detector..................................................................... 471
32.6.9. Synchronization Word Configuration..................................................... 471
32.6.10. Receive Header Check ....................................................................... 472
32.6.11. TX Retransmission and Auto TX......................................................... 472
32.7. RX Modem Configuration .............................................................................. 473
10
Rev. 0.3
Si102x/3x
32.7.1. Modem Settings for FSK and GFSK ..................................................... 473
32.8. Auxiliary Functions ........................................................................................ 473
32.8.1. Smart Reset .......................................................................................... 473
32.8.2. Output Clock ......................................................................................... 474
32.8.3. General Purpose ADC .......................................................................... 475
32.8.4. Temperature Sensor ............................................................................. 476
32.8.5. Low Battery Detector............................................................................. 478
32.8.6. Wake-Up Timer and 32 kHz Clock Source ........................................... 479
32.8.7. Low Duty Cycle Mode ........................................................................... 481
32.8.8. GPIO Configuration............................................................................... 482
32.8.9. Antenna Diversity .................................................................................. 483
32.8.10. RSSI and Clear Channel Assessment ................................................ 483
32.9. Reference Design.......................................................................................... 484
32.10. Application Notes and Reference Designs .................................................. 487
32.11. Customer Support ....................................................................................... 487
32.12. Register Table and Descriptions ................................................................. 488
32.13. Required Changes to Default Register Values............................................ 490
33. Timers ................................................................................................................... 491
33.1. Timer 0 and Timer 1 ...................................................................................... 493
33.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 493
33.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 494
33.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 494
33.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 495
33.2. Timer 2 .......................................................................................................... 501
33.2.1. 16-bit Timer with Auto-Reload............................................................... 501
33.2.2. 8-bit Timers with Auto-Reload............................................................... 502
33.2.3. Comparator 0/SmaRTClock Capture Mode .......................................... 502
33.3. Timer 3 .......................................................................................................... 507
33.3.1. 16-bit Timer with Auto-Reload............................................................... 507
33.3.2. 8-Bit Timers with Auto-Reload .............................................................. 508
33.3.3. SmaRTClock/External Oscillator Capture Mode ................................... 508
34. Programmable Counter Array............................................................................. 513
34.1. PCA Counter/Timer ....................................................................................... 514
34.2. PCA0 Interrupt Sources................................................................................. 515
34.3. Capture/Compare Modules ........................................................................... 516
34.3.1. Edge-triggered Capture Mode............................................................... 517
34.3.2. Software Timer (Compare) Mode.......................................................... 518
34.3.3. High-Speed Output Mode ..................................................................... 519
34.3.4. Frequency Output Mode ....................................................................... 520
34.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes.............. 521
34.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 523
34.4. Watchdog Timer Mode .................................................................................. 524
34.4.1. Watchdog Timer Operation ................................................................... 524
34.4.2. Watchdog Timer Usage ........................................................................ 525
34.5. Register Descriptions for PCA0..................................................................... 527
Rev. 0.3
11
Si102x/3x
35. C2 Interface .......................................................................................................... 533
35.1. C2 Interface Registers................................................................................... 533
35.2. C2 Pin Sharing .............................................................................................. 536
Contact Information .................................................................................................. 538
12
Rev. 0.3
Si102x/3x
List of Figures
Figure 1.1. Si102x Block Diagram ........................................................................... 28
Figure 1.2. Si103x Block Diagram ........................................................................... 28
Figure 1.3. Si102x/3x RX/TX Direct-tie Application Example .................................. 29
Figure 1.4. Si102x/3x Antenna Diversity Application Example ................................ 29
Figure 1.5. Port I/O Functional Block Diagram ........................................................ 31
Figure 1.6. PCA Block Diagram ............................................................................... 32
Figure 1.7. ADC0 Functional Block Diagram ........................................................... 33
Figure 1.8. ADC0 Multiplexer Block Diagram .......................................................... 34
Figure 1.9. Comparator 0 Functional Block Diagram .............................................. 35
Figure 1.10. Comparator 1 Functional Block Diagram ............................................ 35
Figure 3.1. LGA-85 Pinout Diagram (Top View) ...................................................... 45
Figure 3.2. LGA-85 Package Drawing ..................................................................... 46
Figure 3.3. LGA-85 Land Pattern ............................................................................ 48
Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25C) ............................ 56
Figure 4.2. Typical VOH Curves, 1.83.8 V ............................................................ 58
Figure 4.3. Typical VOL Curves, 1.83.8 V ............................................................. 59
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 78
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing
(BURSTEN = 0) ..................................................................................... 81
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 82
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 83
Figure 5.5. ADC Window Compare Example: Right-Justified
Single-Ended Data ................................................................................ 94
Figure 5.6. ADC Window Compare Example: Left-Justified
Single-Ended Data ................................................................................ 94
Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 95
Figure 5.8. Temperature Sensor Transfer Function ................................................ 97
Figure 5.9. Temperature Sensor Error with 1-Point Calibration
(VREF = 1.68 V) ..................................................................................... 98
Figure 5.10. Voltage Reference Functional Block Diagram ................................... 100
Figure 6.1. Comparator 0 Functional Block Diagram ............................................ 103
Figure 6.2. Comparator 1 Functional Block Diagram ............................................ 104
Figure 6.3. Comparator Hysteresis Plot ................................................................ 105
Figure 7.1. CPn Multiplexer Block Diagram ........................................................... 112
Figure 8.1. CIP-51 Block Diagram ......................................................................... 115
Figure 9.1. Si102x/3x Memory Map ....................................................................... 124
Figure 9.2. Flash Program Memory Map ............................................................... 125
Figure 9.3. Address Memory Map for Instruction Fetches ..................................... 126
Figure 10.1. Multiplexed Configuration Example ................................................... 135
Figure 10.2. Non-Multiplexed Configuration Example ........................................... 136
Figure 10.3. EMIF Operating Modes ..................................................................... 136
Figure 10.4. Non-Multiplexed 16-bit MOVX Timing ............................................... 140
Figure 10.5. Non-Multiplexed 8-bit MOVX without Bank Select Timing ................ 141
Rev. 0.3
13
Si102x/3x
Figure 10.6. Non-Multiplexed 8-bit MOVX with Bank Select Timing ..................... 142
Figure 10.7. Multiplexed 16-bit MOVX Timing ....................................................... 143
Figure 10.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 144
Figure 10.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 145
Figure 11.1. DMA0 Block Diagram ........................................................................ 148
Figure 12.1. CRC0 Block Diagram ........................................................................ 161
Figure 12.2. Bit Reverse Register ......................................................................... 168
Figure 13.1. Polynomial Representation ............................................................... 169
Figure 14.1. AES Peripheral Block Diagram ......................................................... 177
Figure 14.2. Key Inversion Data Flow ................................................................... 180
Figure 14.3. AES Block Cipher Data Flow ............................................................. 186
Figure 14.4. Cipher Block Chaining Mode ............................................................. 191
Figure 14.5. CBC Encryption Data Flow ................................................................ 192
Figure 14.6. CBC Decryption Data Flow ............................................................... 196
Figure 14.7. Counter Mode .................................................................................... 199
Figure 14.8. Counter Mode Data Flow .................................................................. 200
Figure 16.1. SFR Page Stack ................................................................................ 218
Figure 16.2. SFR Page Stack While Using SFR Page 0x0
To Access SMB0ADR ....................................................................... 219
Figure 16.3. SFR Page Stack After SPI0 Interrupt Occurs .................................... 220
Figure 16.4. SFR Page Stack Upon PCA Interrupt Occurring
During a SPI0 ISR ............................................................................. 221
Figure 16.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 222
Figure 16.6. SFR Page Stack Upon Return From SPI0 Interrupt .......................... 223
Figure 18.1. Flash Security Example ..................................................................... 253
Figure 19.1. Si102x/3x Power Distribution ............................................................ 265
Figure 19.2. Clock Tree Distribution ...................................................................... 266
Figure 20.1. Step Down DC-DC Buck Converter Block Diagram .......................... 276
Figure 22.1. Reset Sources ................................................................................... 285
Figure 22.2. Power-On Reset Timing Diagram ..................................................... 286
Figure 23.1. Clocking Sources Block Diagram ...................................................... 293
Figure 23.2. 25 MHz External Crystal Example ..................................................... 295
Figure 24.1. SmaRTClock Block Diagram ............................................................. 302
Figure 24.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 310
Figure 25.1. Pulse Counter Block Diagram ........................................................... 319
Figure 25.2. Mode Examples ................................................................................. 320
Figure 25.3. Reed Switch Configurations .............................................................. 321
Figure 25.4. Debounce Timing .............................................................................. 325
Figure 25.5. Flutter Example ................................................................................. 327
Figure 26.1. LCD Segment Driver Block Diagram ................................................. 341
Figure 26.2. LCD Data Register to LCD Pin Mapping ........................................... 343
Figure 26.3. Contrast Control Mode 1 ................................................................... 345
Figure 26.4. Contrast Control Mode 2 ................................................................... 346
Figure 26.5. Contrast Control Mode 3 ................................................................... 346
Figure 26.6. Contrast Control Mode 4 ................................................................... 347
14
Rev. 0.3
Si102x/3x
Figure 27.1. Port I/O Functional Block Diagram .................................................... 358
Figure 27.2. Port I/O Cell Block Diagram .............................................................. 359
Figure 27.3. Crossbar Priority Decoder with No Pins Skipped .............................. 363
Figure 27.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 364
Figure 28.1. SMBus Block Diagram ...................................................................... 388
Figure 28.2. Typical SMBus Configuration ............................................................ 389
Figure 28.3. SMBus Transaction ........................................................................... 390
Figure 28.4. Typical SMBus SCL Generation ........................................................ 392
Figure 28.5. Typical Master Write Sequence ........................................................ 401
Figure 28.6. Typical Master Read Sequence ........................................................ 402
Figure 28.7. Typical Slave Write Sequence .......................................................... 403
Figure 28.8. Typical Slave Read Sequence .......................................................... 404
Figure 29.1. UART0 Block Diagram ...................................................................... 409
Figure 29.2. UART0 Baud Rate Logic ................................................................... 410
Figure 29.3. UART Interconnect Diagram ............................................................. 411
Figure 29.4. 8-Bit UART Timing Diagram .............................................................. 411
Figure 29.5. 9-Bit UART Timing Diagram .............................................................. 412
Figure 29.6. UART Multi-Processor Mode Interconnect Diagram ......................... 413
Figure 30.1. SPI Block Diagram ............................................................................ 418
Figure 30.2. Multiple-Master Mode Connection Diagram ...................................... 421
Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram .......................................................................... 421
Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram .......................................................................... 421
Figure 30.5. Master Mode Data/Clock Timing ....................................................... 423
Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 423
Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 424
Figure 30.8. SPI Master Timing (CKPHA = 0) ....................................................... 428
Figure 30.9. SPI Master Timing (CKPHA = 1) ....................................................... 428
Figure 30.10. SPI Slave Timing (CKPHA = 0) ....................................................... 429
Figure 30.11. SPI Slave Timing (CKPHA = 1) ....................................................... 429
Figure 31.1. SPI Block Diagram ............................................................................ 431
Figure 31.2. Master Mode Data/Clock Timing ....................................................... 434
Figure 31.3. SPI Master Timing (CKPHA = 0) ....................................................... 441
Figure 32.1. State Machine Diagram ..................................................................... 445
Figure 32.2. TX Timing .......................................................................................... 448
Figure 32.3. RX Timing .......................................................................................... 449
Figure 32.4. Frequency Deviation ......................................................................... 452
Figure 32.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 454
Figure 32.6. FSK vs. GFSK Spectrums ................................................................. 456
Figure 32.7. Direct Synchronous Mode Example .................................................. 459
Figure 32.8. Direct Asynchronous Mode Example ................................................ 459
Figure 32.9. Microcontroller Connections .............................................................. 460
Figure 32.10. PLL Synthesizer Block Diagram ...................................................... 462
Figure 32.11. FIFO Thresholds ............................................................................. 465
Rev. 0.3
15
Si102x/3x
Figure 32.12. Packet Structure .............................................................................. 466
Figure 32.13. Multiple Packets in TX Packet Handler ........................................... 467
Figure 32.14. Required RX Packet Structure with Packet Handler Disabled ........ 467
Figure 32.15. Multiple Packets in RX Packet Handler ........................................... 468
Figure 32.16. Multiple Packets in RX with CRC or Header Error .......................... 468
Figure 32.17. Operation of Data Whitening, Manchester Encoding,
and CRC ......................................................................................... 470
Figure 32.18. Manchester Coding Example .......................................................... 470
Figure 32.19. Header ............................................................................................. 472
Figure 32.20. POR Glitch Parameters ................................................................... 473
Figure 32.21. General Purpose ADC Architecture ................................................ 476
Figure 32.22. Temperature Ranges using ADC8 .................................................. 478
Figure 32.23. WUT Interrupt and WUT Operation ................................................. 481
Figure 32.24. Low Duty Cycle Mode ..................................................................... 482
Figure 32.25. RSSI Value vs. Input Power ............................................................ 484
Figure 32.26. Si1024 Split RF TX/RX Direct-Tie
Reference DesignSchematic ....................................................... 485
Figure 32.27. Si1020 Switch Matching Reference DesignSchematic ................ 486
Figure 33.1. T0 Mode 0 Block Diagram ................................................................. 494
Figure 33.2. T0 Mode 2 Block Diagram ................................................................. 495
Figure 33.3. T0 Mode 3 Block Diagram ................................................................. 496
Figure 33.4. Timer 2 16-Bit Mode Block Diagram ................................................. 501
Figure 33.5. Timer 2 8-Bit Mode Block Diagram ................................................... 502
Figure 33.6. Timer 2 Capture Mode Block Diagram .............................................. 503
Figure 33.7. Timer 3 16-Bit Mode Block Diagram ................................................. 507
Figure 33.8. Timer 3 8-Bit Mode Block Diagram ................................................... 508
Figure 33.9. Timer 3 Capture Mode Block Diagram .............................................. 509
Figure 34.1. PCA Block Diagram ........................................................................... 513
Figure 34.2. PCA Counter/Timer Block Diagram ................................................... 515
Figure 34.3. PCA Interrupt Block Diagram ............................................................ 516
Figure 34.4. PCA Capture Mode Diagram ............................................................. 518
Figure 34.5. PCA Software Timer Mode Diagram ................................................. 519
Figure 34.6. PCA High-Speed Output Mode Diagram ........................................... 520
Figure 34.7. PCA Frequency Output Mode ........................................................... 521
Figure 34.8. PCA 8-Bit PWM Mode Diagram ........................................................ 522
Figure 34.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 523
Figure 34.10. PCA 16-Bit PWM Mode ................................................................... 524
Figure 34.11. PCA Module 5 with Watchdog Timer Enabled ................................ 525
Figure 35.1. Typical C2 Pin Sharing ...................................................................... 536
16
Rev. 0.3
Si102x/3x
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 36
Table 3.1. Pin Definitions for the Si102x/3x ............................................................. 37
Table 3.2. LGA-85 Package Dimensions ................................................................ 46
Table 3.3. LGA-85 Land Pattern Dimensions .......................................................... 48
Table 4.1. Absolute Maximum Ratings .................................................................... 50
Table 4.2. Global Electrical Characteristics ............................................................. 51
Table 4.3. Digital Supply Current at VBAT pin with DC-DC
Converter Enabled .................................................................................. 51
Table 4.4. Digital Supply Current with DC-DC Converter Disabled ......................... 52
Table 4.5. Port I/O DC Electrical Characteristics ..................................................... 57
Table 4.6. Reset Electrical Characteristics .............................................................. 60
Table 4.7. Power Management Electrical Specifications ......................................... 61
Table 4.8. Flash Electrical Characteristics .............................................................. 61
Table 4.9. Internal Precision Oscillator Electrical Characteristics ........................... 61
Table 4.10. Internal Low-Power Oscillator Electrical Characteristics ...................... 61
Table 4.11. SmaRTClock Characteristics ................................................................ 62
Table 4.12. ADC0 Electrical Characteristics ............................................................ 62
Table 4.13. Temperature Sensor Electrical Characteristics .................................... 63
Table 4.14. Voltage Reference Electrical Characteristics ....................................... 64
Table 4.15. IREF0 Electrical Characteristics ........................................................... 65
Table 4.16. Comparator Electrical Characteristics .................................................. 66
Table 4.17. VREG0 Electrical Characteristics ......................................................... 67
Table 4.18. LCD0 Electrical Characteristics ............................................................ 68
Table 4.19. PC0 Electrical Characteristics .............................................................. 68
Table 4.20. DC0 (Buck Converter) Electrical Characteristics .................................. 69
Table 4.21. DC Characteristics ................................................................................ 70
Table 4.22. Synthesizer AC Electrical Characteristics ............................................ 71
Table 4.23. Receiver AC Electrical Characteristics ................................................. 72
Table 4.24. Transmitter AC Electrical Characteristics ............................................. 73
Table 4.25. Auxiliary Block Specifications ............................................................... 74
Table 4.26. Digital IO Specifications (nIRQ) ............................................................ 75
Table 4.27. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ........................ 75
Table 4.28. Absolute Maximum Ratings .................................................................. 76
Table 5.1. Representative Conversion Times and Energy Consumption
for the SAR ADC with 1.65 V High-Speed VREF ................................... 85
Table 8.1. CIP-51 Instruction Set Summary .......................................................... 117
Table 10.1. EMIF Pinout ........................................................................................ 132
Table 10.2. AC Parameters for External Memory Interface ................................... 146
Table 12.1. Example 16-bit CRC Outputs ............................................................. 162
Table 12.2. Example 32-bit CRC Outputs ............................................................. 164
Table 14.1. Extended Key Output Byte Order ....................................................... 183
Table 14.2. 192-Bit Key DMA Usage ..................................................................... 184
Table 14.3. 256-bit Key DMA Usage ..................................................................... 184
Rev. 0.3
17
Si102x/3x
Table 15.1. Encoder Input and Output Data Sizes ................................................ 208
Table 15.2. Manchester Encoding ......................................................................... 209
Table 15.3. Manchester Decoding ......................................................................... 210
Table 15.4. Three-out-of-Six Encoding Nibble ...................................................... 211
Table 15.5. Three-out-of-Six Decoding ................................................................. 212
Table 16.1. SFR Map (0xC00xFF) ...................................................................... 228
Table 16.2. SFR Map (0x800xBF) ....................................................................... 229
Table 16.3. Special Function Registers ................................................................. 230
Table 17.1. Interrupt Summary .............................................................................. 240
Table 18.1. Flash Security Summary .................................................................... 254
Table 19.1. Power Modes ...................................................................................... 264
Table 20.1. IPeak Inductor Current Limit Settings ................................................. 277
Table 23.1. Recommended XFCN Settings for Crystal Mode ............................... 295
Table 23.2. Recommended XFCN Settings for RC and C modes ......................... 296
Table 24.1. SmaRTClock Internal Registers ......................................................... 303
Table 24.2. SmaRTClock Load Capacitance Settings .......................................... 309
Table 24.3. SmaRTClock Bias Settings ................................................................ 310
Table 25.1. Pull-Up Resistor Current ..................................................................... 322
Table 25.2. Sample Rate Duty-Cycle Multiplier ..................................................... 322
Table 25.3. Pull-Up Duty-Cycle Multiplier .............................................................. 322
Table 25.4. Average Pull-Up Current (Sample Rate = 250 s) ............................. 323
Table 25.5. Average Pull-Up Current (Sample Rate = 500 s) ............................. 323
Table 25.6. Average Pull-Up Current (Sample Rate = 1 ms) ............................... 323
Table 25.7. Average Pull-Up Current (Sample Rate = 2 ms) ................................ 323
Table 26.1. Bit Configurations to select Contrast Control Modes .......................... 345
Table 27.1. Port I/O Assignment for Analog Functions ......................................... 360
Table 27.2. Port I/O Assignment for Digital Functions ........................................... 361
Table 27.3. Port I/O Assignment for External Digital Event
Capture Functions .............................................................................. 361
Table 28.1. SMBus Clock Source Selection .......................................................... 392
Table 28.2. Minimum SDA Setup and Hold Times ................................................ 393
Table 28.3. Sources for Hardware Changes to SMB0CN ..................................... 397
Table 28.4. Hardware Address Recognition Examples (EHACK = 1) ................... 398
Table 28.5. SMBus Status Decoding With Hardware ACK Generation
Disabled (EHACK = 0) ........................................................................ 405
Table 28.6. SMBus Status Decoding With Hardware ACK Generation
Enabled (EHACK = 1) ......................................................................... 407
Table 29.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 416
Table 29.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 416
Table 30.1. SPI Slave Timing Parameters ............................................................ 430
Table 31.1. SPI Timing Parameters ...................................................................... 441
Table 32.1. EZRadioPRO Operating Modes ......................................................... 444
Table 32.2. EZRadioPRO Operating Modes Response Time ............................... 445
18
Rev. 0.3
Si102x/3x
Table 32.3. Frequency Band Selection ................................................................. 450
Table 32.4. Packet Handler Registers ................................................................... 469
Table 32.5. Minimum Receiver Settling Time ........................................................ 471
Table 32.6. POR Parameters ................................................................................ 474
Table 32.7. Temperature Sensor Range ............................................................... 477
Table 32.8. Antenna Diversity Control ................................................................... 483
Table 32.9. EZRadioPRO Internal Register Descriptions ...................................... 488
Table 33.1. Timer 0 Running Modes ..................................................................... 493
Table 34.1. PCA Timebase Input Options ............................................................. 514
Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA
Capture/Compare Modules ................................................................ 516
Table 34.3. Watchdog Timer Timeout Intervals1 ................................................... 526
Rev. 0.3
19
Si102x/3x
List of Registers
SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 86
SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 87
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 88
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 89
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 90
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 91
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 91
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 92
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 92
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 93
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 93
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 96
SFR Definition 5.13. TOFFH: Temperature Sensor Offset High Byte ........................... 99
SFR Definition 5.14. TOFFL: Temperature Sensor Offset Low Byte ............................ 99
SFR Definition 5.15. REF0CN: Voltage Reference Control ........................................ 102
SFR Definition 6.1. CPT0CN: Comparator 0 Control .................................................. 106
SFR Definition 6.2. CPT0MD: Comparator 0 Mode Selection .................................... 107
SFR Definition 6.3. CPT1CN: Comparator 1 Control .................................................. 108
SFR Definition 6.4. CPT1MD: Comparator 1 Mode Selection .................................... 109
SFR Definition 7.1. IREF0CN: Current Reference Control ......................................... 110
SFR Definition 7.2. IREF0CF: Current Reference Configuration ................................ 111
SFR Definition 7.3. CPT0MX: Comparator0 Input Channel Select ............................. 113
SFR Definition 7.4. CPT1MX: Comparator1 Input Channel Select ............................. 114
SFR Definition 8.1. DPL: Data Pointer Low Byte ........................................................ 121
SFR Definition 8.2. DPH: Data Pointer High Byte ....................................................... 121
SFR Definition 8.3. SP: Stack Pointer ......................................................................... 122
SFR Definition 8.4. ACC: Accumulator ....................................................................... 122
SFR Definition 8.5. B: B Register ................................................................................ 122
SFR Definition 8.6. PSW: Program Status Word ........................................................ 123
SFR Definition 9.1. PSBANK: Program Space Bank Select ....................................... 127
SFR Definition 10.1. EMI0CN: External Memory Interface Control ............................ 133
SFR Definition 10.2. EMI0CF: External Memory Configuration .................................. 134
SFR Definition 10.3. EMI0TC: External Memory Timing Control ................................ 139
SFR Definition 11.1. DMA0EN: DMA0 Channel Enable ............................................. 151
SFR Definition 11.2. DMA0INT: DMA0 Full-Length Interrupt ...................................... 152
SFR Definition 11.3. DMA0MINT: DMA0 Mid-Point Interrupt ..................................... 153
SFR Definition 11.4. DMA0BUSY: DMA0 Busy .......................................................... 154
SFR Definition 11.5. DMA0SEL: DMA0 Channel Select for Configuration ................. 155
SFR Definition 11.6. DMA0NMD: DMA Channel Mode .............................................. 156
SFR Definition 11.7. DMA0NCF: DMA Channel Configuration ................................... 157
SFR Definition 11.8. DMA0NBAH: Memory Base Address High Byte ........................ 158
SFR Definition 11.9. DMA0NBAL: Memory Base Address Low Byte ......................... 158
SFR Definition 11.10. DMA0NAOH: Memory Address Offset High Byte .................... 159
20
Rev. 0.3
Si102x/3x
SFR Definition 11.11. DMA0NAOL: Memory Address Offset Low Byte ..................... 159
SFR Definition 11.12. DMA0NSZH: Transfer Size High Byte ..................................... 160
SFR Definition 11.13. DMA0NSZL: Memory Transfer Size Low Byte ........................ 160
SFR Definition 12.1. CRC0CN: CRC0 Control ........................................................... 165
SFR Definition 12.2. CRC0IN: CRC0 Data Input ........................................................ 166
SFR Definition 12.3. CRC0DAT: CRC0 Data Output .................................................. 166
SFR Definition 12.4. CRC0AUTO: CRC0 Automatic Control ...................................... 167
SFR Definition 12.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 167
SFR Definition 12.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 168
SFR Definition 13.1. CRC1CN: CRC1 Control ........................................................... 173
SFR Definition 13.2. CRC1IN: CRC1 Data IN ............................................................ 174
SFR Definition 13.3. CRC1POLL: CRC1 Polynomial LSB .......................................... 174
SFR Definition 13.4. CRC1POLH: CRC1 Polynomial MSB ........................................ 174
SFR Definition 13.5. CRC1OUTL: CRC1 Output LSB ................................................ 175
SFR Definition 13.6. CRC1OUTH: CRC1 Output MSB .............................................. 175
SFR Definition 14.1. AES0BCFG: AES Block Configuration ...................................... 203
SFR Definition 14.2. AES0DCFG: AES Data Configuration ....................................... 204
SFR Definition 14.3. AES0BIN: AES Block Input ........................................................ 205
SFR Definition 14.4. AES0XIN: AES XOR Input ......................................................... 206
SFR Definition 14.5. AES0KIN: AES Key Input .......................................................... 206
SFR Definition 14.6. AES0YOUT: AES Y Output ....................................................... 207
SFR Definition 15.1. ENC0CN: Encoder Decoder 0 Control ...................................... 215
SFR Definition 15.2. ENC0L: ENC0 Data Low Byte ................................................... 216
SFR Definition 15.3. ENC0M: ENC0 Data Middle Byte .............................................. 216
SFR Definition 15.4. ENC0H: ENC0 Data High Byte .................................................. 216
SFR Definition 16.1. SFRPGCN: SFR Page Control .................................................. 224
SFR Definition 16.2. SFRPAGE: SFR Page ............................................................... 225
SFR Definition 16.3. SFRNEXT: SFR Next ................................................................ 226
SFR Definition 16.4. SFRLAST: SFR Last .................................................................. 227
SFR Definition 17.1. IE: Interrupt Enable .................................................................... 242
SFR Definition 17.2. IP: Interrupt Priority .................................................................... 243
SFR Definition 17.3. EIE1: Extended Interrupt Enable 1 ............................................ 244
SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 ............................................ 245
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2 ............................................ 246
SFR Definition 17.6. EIP2: Extended Interrupt Priority 2 ............................................ 247
SFR Definition 17.7. IT01CF: INT0/INT1 Configuration .............................................. 249
SFR Definition 18.1. DEVICEID: Device Identification ................................................ 255
SFR Definition 18.2. REVID: Revision Identification ................................................... 256
SFR Definition 18.3. PSCTL: Program Store R/W Control ......................................... 260
SFR Definition 18.4. FLKEY: Flash Lock and Key ...................................................... 261
SFR Definition 18.5. FLSCL: Flash Scale ................................................................... 262
SFR Definition 18.6. FLWR: Flash Write Only ............................................................ 262
SFR Definition 18.7. FRBCN: Flash Read Buffer Control ........................................... 263
SFR Definition 19.1. PCLKACT: Peripheral Active Clock Enable ............................... 267
SFR Definition 19.2. PCLKEN: Peripheral Clock Enable ............................................ 268
Rev. 0.3
21
Si102x/3x
SFR Definition 19.3. CLKMODE: Clock Mode ............................................................ 269
SFR Definition 19.4. PMU0CF: Power Management Unit Configuration ..................... 272
SFR Definition 19.5. PMU0FL: Power Management Unit Flag ................................... 273
SFR Definition 19.6. PMU0MD: Power Management Unit Mode ................................ 274
SFR Definition 19.7. PCON: Power Management Control Register ........................... 275
SFR Definition 20.1. DC0CN: DC-DC Converter Control ........................................... 280
SFR Definition 20.2. DC0CF: DC-DC Converter Configuration .................................. 281
SFR Definition 20.3. DC0MD: DC-DC Converter Mode .............................................. 282
SFR Definition 20.4. DC0RDY: DC-DC Converter Ready Indicator ........................... 283
SFR Definition 21.1. REG0CN: Voltage Regulator Control ........................................ 284
SFR Definition 22.1. VDM0CN: VDD Supply Monitor Control .................................... 289
SFR Definition 22.2. RSTSRC: Reset Source ............................................................ 292
SFR Definition 23.1. CLKSEL: Clock Select ............................................................... 298
SFR Definition 23.2. OSCICN: Internal Oscillator Control .......................................... 299
SFR Definition 23.3. OSCICL: Internal Oscillator Calibration ..................................... 300
SFR Definition 23.4. OSCXCN: External Oscillator Control ........................................ 301
SFR Definition 24.1. RTC0KEY: SmaRTClock Lock and Key .................................... 305
SFR Definition 24.2. RTC0ADR: SmaRTClock Address ............................................ 305
SFR Definition 24.3. RTC0DAT: SmaRTClock Data .................................................. 306
Internal Register Definition 24.4. RTC0CN: SmaRTClock Control ............................. 313
Internal Register Definition 24.5. RTC0XCN: SmaRTClock Oscillator Control ........... 314
Internal Register Definition 24.6. RTC0XCF: SmaRTClock
Oscillator Configuration .......................................... 315
Internal Register Definition 24.7. RTC0CF: SmaRTClock Configuration .................... 316
Internal Register Definition 24.8. CAPTUREn: SmaRTClock Timer Capture ............. 317
Internal Register Definition 24.9. ALARM0Bn: SmaRTClock Alarm 0
Match Value ............................................................ 317
Internal Register Definition 24.10. ALARM1Bn: SmaRTClock Alarm 1
Match Value .......................................................... 318
Internal Register Definition 24.11. ALARM2Bn: SmaRTClock Alarm 2
Match Value ............................................................ 318
SFR Definition 25.1. PC0MD: PC0 Mode Configuration ............................................. 328
SFR Definition 25.2. PC0PCF: PC0 Mode Pull-Up Configuration .............................. 329
SFR Definition 25.3. PC0TH: PC0 Threshold Configuration ....................................... 330
SFR Definition 25.4. PC0STAT: PC0 Status .............................................................. 331
SFR Definition 25.5. PC0DCH: PC0 Debounce Configuration High ........................... 332
SFR Definition 25.6. PC0DCL: PC0 Debounce Configuration Low ............................ 333
SFR Definition 25.7. PC0CTR0H: PC0 Counter 0 High (MSB) .................................. 334
SFR Definition 25.8. PC0CTR0M: PC0 Counter 0 Middle .......................................... 334
SFR Definition 25.9. PC0CTR0L: PC0 Counter 0 Low (LSB) ..................................... 334
SFR Definition 25.10. PC0CTR1H: PC0 Counter 1 High (MSB) ................................ 335
SFR Definition 25.11. PC0CTR1M: PC0 Counter 1 Middle ........................................ 335
SFR Definition 25.12. PC0CTR1L: PC0 Counter 1 Low (LSB) ................................... 335
SFR Definition 25.13. PC0CMP0H: PC0 Comparator 0 High (MSB) .......................... 336
SFR Definition 25.14. PC0CMP0M: PC0 Comparator 0 Middle ................................. 336
22
Rev. 0.3
Si102x/3x
SFR Definition 25.15. PC0CMP0L: PC0 Comparator 0 Low (LSB) ............................ 336
SFR Definition 25.16. PC0CMP1H: PC0 Comparator 1 High (MSB) .......................... 337
SFR Definition 25.17. PC0CMP1M: PC0 Comparator 1 Middle ................................. 337
SFR Definition 25.18. PC0CMP1L: PC0 Comparator 1 Low (LSB) ............................ 337
SFR Definition 25.19. PC0HIST: PC0 History ............................................................ 338
SFR Definition 25.20. PC0INT0: PC0 Interrupt 0 ........................................................ 339
SFR Definition 25.21. PC0INT1: PC0 Interrupt 1 ........................................................ 340
SFR Definition 26.1. LCD0Dn: LCD0 Data ................................................................. 342
SFR Definition 26.2. LCD0CN: LCD0 Control Register .............................................. 344
SFR Definition 26.3. LCD0CNTRST: LCD0 Contrast Adjustment .............................. 348
SFR Definition 26.4. LCD0MSCN: LCD0 Master Control ........................................... 349
SFR Definition 26.5. LCD0MSCF: LCD0 Master Configuration .................................. 350
SFR Definition 26.6. LCD0PWR: LCD0 Power ........................................................... 350
SFR Definition 26.7. LCD0VBMCN: LCD0 VBAT Monitor Control ............................. 351
SFR Definition 26.8. LCD0CLKDIVH: LCD0 Refresh Rate Prescaler High Byte ........ 352
SFR Definition 26.9. LCD0CLKDIVL: LCD Refresh Rate Prescaler Low Byte ........... 352
SFR Definition 26.10. LCD0BLINK: LCD0 Blink Mask ................................................ 353
SFR Definition 26.11. LCD0TOGR: LCD0 Toggle Rate ............................................. 354
SFR Definition 26.12. LCD0CF: LCD0 Configuration ................................................. 355
SFR Definition 26.13. LCD0CHPCN: LCD0 Charge Pump Control ............................ 355
SFR Definition 26.14. LCD0CHPCF: LCD0 Charge Pump Configuration .................. 356
SFR Definition 26.15. LCD0CHPMD: LCD0 Charge Pump Mode .............................. 356
SFR Definition 26.16. LCD0BUFCN: LCD0 Buffer Control ......................................... 356
SFR Definition 26.17. LCD0BUFCF: LCD0 Buffer Configuration ............................... 357
SFR Definition 26.18. LCD0BUFMD: LCD0 Buffer Mode ........................................... 357
SFR Definition 26.19. LCD0VBMCF: LCD0 VBAT Monitor Configuration .................. 357
SFR Definition 27.1. XBR0: Port I/O Crossbar Register 0 .......................................... 365
SFR Definition 27.2. XBR1: Port I/O Crossbar Register 1 .......................................... 366
SFR Definition 27.3. XBR2: Port I/O Crossbar Register 2 .......................................... 367
SFR Definition 27.4. P0MASK: Port0 Mask Register .................................................. 368
SFR Definition 27.5. P0MAT: Port0 Match Register ................................................... 368
SFR Definition 27.6. P1MASK: Port1 Mask Register .................................................. 369
SFR Definition 27.7. P1MAT: Port1 Match Register ................................................... 369
SFR Definition 27.8. P0: Port0 .................................................................................... 371
SFR Definition 27.9. P0SKIP: Port0 Skip .................................................................... 371
SFR Definition 27.10. P0MDIN: Port0 Input Mode ...................................................... 372
SFR Definition 27.11. P0MDOUT: Port0 Output Mode ............................................... 372
SFR Definition 27.12. P0DRV: Port0 Drive Strength .................................................. 373
SFR Definition 27.13. P1: Port1 .................................................................................. 373
SFR Definition 27.14. P1SKIP: Port1 Skip .................................................................. 374
SFR Definition 27.15. P1MDIN: Port1 Input Mode ...................................................... 374
SFR Definition 27.16. P1MDOUT: Port1 Output Mode ............................................... 375
SFR Definition 27.17. P1DRV: Port1 Drive Strength .................................................. 375
SFR Definition 27.18. P2: Port2 .................................................................................. 376
SFR Definition 27.19. P2SKIP: Port2 Skip .................................................................. 376
Rev. 0.3
23
Si102x/3x
SFR Definition 27.20. P2MDIN: Port2 Input Mode ...................................................... 377
SFR Definition 27.21. P2MDOUT: Port2 Output Mode ............................................... 377
SFR Definition 27.22. P2DRV: Port2 Drive Strength .................................................. 378
SFR Definition 27.23. P3: Port3 .................................................................................. 378
SFR Definition 27.24. P3MDIN: Port3 Input Mode ...................................................... 379
SFR Definition 27.25. P3MDOUT: Port3 Output Mode ............................................... 379
SFR Definition 27.26. P3DRV: Port3 Drive Strength .................................................. 380
SFR Definition 27.27. P4: Port4 .................................................................................. 380
SFR Definition 27.28. P4MDIN: Port4 Input Mode ...................................................... 381
SFR Definition 27.29. P4MDOUT: Port4 Output Mode ............................................... 381
SFR Definition 27.30. P4DRV: Port4 Drive Strength .................................................. 382
SFR Definition 27.31. P5: Port5 .................................................................................. 382
SFR Definition 27.32. P5MDIN: Port5 Input Mode ...................................................... 383
SFR Definition 27.33. P5MDOUT: Port5 Output Mode ............................................... 383
SFR Definition 27.34. P5DRV: Port5 Drive Strength .................................................. 384
SFR Definition 27.35. P6: Port6 .................................................................................. 384
SFR Definition 27.36. P6MDIN: Port6 Input Mode ...................................................... 385
SFR Definition 27.37. P6MDOUT: Port6 Output Mode ............................................... 385
SFR Definition 27.38. P6DRV: Port6 Drive Strength .................................................. 386
SFR Definition 27.39. P7: Port7 .................................................................................. 386
SFR Definition 27.40. P7MDOUT: Port7 Output Mode ............................................... 387
SFR Definition 27.41. P7DRV: Port7 Drive Strength .................................................. 387
SFR Definition 28.1. SMB0CF: SMBus Clock/Configuration ...................................... 394
SFR Definition 28.2. SMB0CN: SMBus Control .......................................................... 396
SFR Definition 28.3. SMB0ADR: SMBus Slave Address ............................................ 398
SFR Definition 28.4. SMB0ADM: SMBus Slave Address Mask .................................. 399
SFR Definition 28.5. SMB0DAT: SMBus Data ............................................................ 400
SFR Definition 29.1. SCON0: Serial Port 0 Control .................................................... 414
SFR Definition 29.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 415
SFR Definition 30.1. SPI0CFG: SPI0 Configuration ................................................... 425
SFR Definition 30.2. SPI0CN: SPI0 Control ............................................................... 426
SFR Definition 30.3. SPI0CKR: SPI0 Clock Rate ....................................................... 427
SFR Definition 30.4. SPI0DAT: SPI0 Data ................................................................. 427
SFR Definition 31.1. SPI1CFG: SPI1 Configuration ................................................... 438
SFR Definition 31.2. SPI1CN: SPI1 Control ............................................................... 439
SFR Definition 31.3. SPI1CKR: SPI1 Clock Rate ....................................................... 440
SFR Definition 31.4. SPI1DAT: SPI1 Data ................................................................. 440
SFR Definition 33.1. CKCON: Clock Control .............................................................. 492
SFR Definition 33.2. TCON: Timer Control ................................................................. 497
SFR Definition 33.3. TMOD: Timer Mode ................................................................... 498
SFR Definition 33.4. TL0: Timer 0 Low Byte ............................................................... 499
SFR Definition 33.5. TL1: Timer 1 Low Byte ............................................................... 499
SFR Definition 33.6. TH0: Timer 0 High Byte ............................................................. 500
SFR Definition 33.7. TH1: Timer 1 High Byte ............................................................. 500
SFR Definition 33.8. TMR2CN: Timer 2 Control ......................................................... 504
24
Rev. 0.3
Si102x/3x
SFR Definition 33.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 505
SFR Definition 33.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 505
SFR Definition 33.11. TMR2L: Timer 2 Low Byte ....................................................... 506
SFR Definition 33.12. TMR2H Timer 2 High Byte ....................................................... 506
SFR Definition 33.13. TMR3CN: Timer 3 Control ....................................................... 510
SFR Definition 33.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 511
SFR Definition 33.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 511
SFR Definition 33.16. TMR3L: Timer 3 Low Byte ....................................................... 512
SFR Definition 33.17. TMR3H Timer 3 High Byte ....................................................... 512
SFR Definition 34.1. PCA0CN: PCA Control .............................................................. 527
SFR Definition 34.2. PCA0MD: PCA Mode ................................................................ 528
SFR Definition 34.3. PCA0PWM: PCA PWM Configuration ....................................... 529
SFR Definition 34.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 530
SFR Definition 34.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 531
SFR Definition 34.6. PCA0H: PCA Counter/Timer High Byte ..................................... 531
SFR Definition 34.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 532
SFR Definition 34.8. PCA0CPHn: PCA Capture Module High Byte ........................... 532
C2 Register Definition 35.1. C2ADD: C2 Address ...................................................... 533
C2 Register Definition 35.2. DEVICEID: C2 Device ID ............................................... 534
C2 Register Definition 35.3. REVID: C2 Revision ID .................................................. 534
C2 Register Definition 35.4. FPCTL: C2 Flash Programming Control ........................ 535
C2 Register Definition 35.5. FPDAT: C2 Flash Programming Data ............................ 535
Rev. 0.3
25
Si102x/3x
1. System Overview
Si102x/3x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are
listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
The on-chip Silicon Labs 2-wire (C2) development interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 1.8 to 3.8 V operation over the industrial temperature range (40 to +85 C).
The port I/O and RST pins are tolerant of input signals up to VIO + 2.0 V. The Si102x/3x devices are available in an 85-pin LGA package that is lead-free and RoHS-compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 and Figure 1.2.
The transceiver's extremely low receive sensitivity (121 dBm) coupled with industry leading +13 or
+20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity
and support for frequency hopping can be used to further extend range and enhance performance. The
advanced radio features including continuous frequency coverage from 240960 MHz in 156 Hz or 312 Hz
steps allow precise tuning control. Additional system features such as an automatic wake-up timer, low
battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall
current consumption.
26
Rev. 0.3
Si102x/3x
The transceivers digital receive architecture features a high-performance ADC and DSP-based modem
which performs demodulation, filtering, and packet handling for increased flexibility and performance. The
direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and
reduced spectral spreading, ensuring compliance with global regulations including FCC, ETSI, ARIB, and
802.15.4d.
Rev. 0.3
27
Si102x/3x
Zurücksetzen
Debug /
Programming
Hardware
VBAT
VDD
DCOUT+
UART
Timers
0/1/2/3
DMA
SMBus
SPI 0
VREG
Analog
Power
CRC
Engine
VREG
Digital
Power
AES
Engine
Priority
Crossbar
Decoder
PCA/
WDT
C2D
VBAT
Digital Peripherals
128/64/32/16 kByte
ISP Flash Program
Memory
Wake
C2CK/RST
CIP-51 8051
Controller Core
Power On
Reset/PMU
Port 0-1
Drivers
16
Port 2
Drivers
Port 3-6
Drivers
32
P0.0...P1.7
P2.4...P2.7
P3.0...P6.7
Port 7
Driver
P7.0/C2D
RF XCVR
(240-960 MHz,
+20/+13 dBm)
Crossbar Control
PA
VCO
LCD (4x32)
TX
Encoder
DCEN
DC/DC
Buck
Converter
SYSCLK
PGA
Analog Peripherals
Internal
External
VREF
VREF
XTAL4
ADC
Digital
Modem
A
M
U
X
12-bit
75ksps
ADC
Enhanced
smaRTClock
Oscillator
XTAL3
LNA
Mixer
External
Oscillator
Circuit
XTAL2
RXp
RXn
Pulse Counter
EZRadioPro SPI 1
Low Power
20 MHz
Oscillator
LCD Charge
Pump
XTAL1
GND
AGC
Precision
24.5 MHz
Oscillator
DCIN-
CAP
SFR
Bus
EMIF
VDD
VREF
Temp
Sensor
Delta
Sigma
Modulator
Digital
Logic
GND
CP0, CP0A
System Clock
Configuration
CP1, CP1A
+
-
XOUT
XIN
30 MHz
+
-
Comparators
Zurücksetzen
Debug /
Programming
Hardware
VBAT
VDD
DCOUT+
UART
Timers
0/1/2/3
DMA
SMBus
SPI 0
VREG
Analog
Power
CRC
Engine
VREG
Digital
Power
AES
Engine
Priority
Crossbar
Decoder
PCA/
WDT
C2D
VBAT
Digital Peripherals
128/64/32/16 kByte
ISP Flash Program
Memory
Wake
C2CK/RST
CIP-51 8051
Controller Core
Power On
Reset/PMU
Port 0-1
Drivers
16
Port 2
Drivers
Port 3-6
Drivers
32
P0.0...P1.7
P2.4...P2.7
P3.0...P6.7
Port 7
Driver
P7.0/C2D
RF XCVR
(240-960 MHz,
+20/+13 dBm)
Crossbar Control
PA
VCO
TX
Encoder
DCEN
DC/DC
Buck
Converter
DCIN-
CAP
LCD Charge
Pump
XTAL1
XTAL2
GND
XTAL3
XTAL4
SYSCLK
SFR
Bus
EMIF
AGC
Pulse Counter
Precision
24.5 MHz
Oscillator
PGA
Analog Peripherals
Internal
External
VREF
VREF
VDD
VREF
Temp
Sensor
Delta
Sigma
Modulator
Digital
Logic
GND
CP0, CP0A
CP1, CP1A
+
-
+
-
Comparators
28
ADC
Digital
Modem
A
M
U
X
12-bit
75ksps
ADC
Enhanced
smaRTClock
Oscillator
System Clock
Configuration
RXp
RXn
Mixer
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
LNA
EZRadioPro SPI 1
Rev. 0.3
30 MHz
XOUT
XIN
Si102x/3x
1.1. Typical Connection Diagram
The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without
the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie
reference design is available from Silicon Laboratories applications support.
For applications seeking improved performance in the presence of multipath fading, antenna diversity can
be used. Antenna diversity support is integrated into the EZRadioPRO transceiver and can improve the
system link budget by 810 dB in the presence of these fading conditions, resulting in substantial range
increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applications support.
supply voltage
1u
L1
L2
VDD_RF
C1
RFp
Si1020/1/2/3
Si1030/1/2/3
RXn
GPIO0
C4
L5
GPIO2
L3
C2
L6
VDD_MCU
VDD_DIG
Px.x
TX
GPIO1
L4
C3
nIRQ
100n
0.1 uF
VR_DIG
100p
X1
30MHz
XIN
C8
XOUT
C7
SDN
C6
0.1 uF
C9
1u
C5
Supply Voltage
100 n
1u
L3
L2
L1
C2
C1
RXp
Si102x
Si103x
RXn
C4
L4
GPIO2
C3
VDD_MCU
VDD_DIG
Px.x
0.1 uF
VR_DIG
GPIO1
VDD_RF
TX
GPIO0
TR & ANT-DIV
Switch
nIRQ
100 p
X1
30 MHz
XIN
C8
XOUT
C7
SDN
C6
0.1 uF
C9
1u
C5
Rev. 0.3
29
Si102x/3x
1.2. CIP-51 Microcontroller Core
1.2.1. Fully 8051 Compatible
The Si102x/3x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51 instruction set; standard 803x/805x assemblers and compilers can be used to
develop software. The CIP-51 core offers all the peripherals included with a standard 8052.
1.2.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute
2/3
3/4
4/5
Number of Instructions
26
50
14
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS.
1.2.3. Additional Features
The Si102x/3x SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention
by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building
multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector,
SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset,
an external reset pin, and an illegal flash access protection circuit. Each reset source except for the POR,
Reset Input Pin, or flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization.
The internal oscillator factory calibrated to 24.5 MHz and is accurate to 2% over the full temperature and
supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz
low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to
generate the system clock. If desired, the system clock source may be switched on-the-fly between both
internal and external oscillator circuits. An external oscillator can also be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to
the fast (up to 25 MHz) internal oscillator as needed.
30
Rev. 0.3
Si102x/3x
1.3. Port Input/Output
Digital and analog resources are available through 53 I/O pins. Port pins are organized as eight byte-wide
ports. Port pins can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P7.0 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See
Section 35. C2 Interface on page 533 for more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See
Section 27. Port Input/Output on page 358 for more information on the Crossbar.
For Port I/Os configured as push-pull outputs, current is sourced from the VIO, VIORF, or VBAT supply pin.
Port I/Os used for analog functions can operate up to the supply voltage. See Section 27. Port Input/Output on page 358 for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications.
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Highest
Priority
UART
Priority
Decoder
PnMDOUT,
PnMDIN Registers
SPI0
SPI1
P1
I/O
Cells
External Interrupts
EX0 and EX1
P0.0
P0.7
P1.0
P1.7
2
8
CP0
CP1
Outputs
Digital
Crossbar
8
SYSCLK
7
2
T0, T1
P0
(Port Latches)
P0
I/O
Cells
SMBus
PCA
Lowest
Priority
XBR0, XBR1,
XBR2, PnSKIP
Registers
8
P6
(P6.0-P6.7)
1
P7
(P7.0)
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
P2
I/O
Cells
P3
I/O
Cells
P4
I/O
Cells
P5
I/O
Cells
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6
I/O
Cells
P6.7
P7
P7.0
To EMIF
To LCD
Rev. 0.3
31
Si102x/3x
1.4. Serial Ports
The Si102x/3x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hardware and
makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
SYSCLK /12
SYSCLK /4
Timer 0 Overflow
ECI
PCA
CLOCK
MUX
16 -Bit Counter/Timer
SYSCLK
External Clock /8
Capture/ Compare
Module 0
Capture/ Compare
Module 1
Capture/ Compare
Module 2
Capture/ Compare
Module 3
32
Rev. 0.3
Capture/ Compare
Module5 / WDT
CEX5
Port I/O
CEX4
CEX3
CEX2
CEX1
CEX0
ECI
Crossbar
Capture/ Compare
Module 4
Si102x/3x
1.6. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode
The ADC0 on Si102x/3x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation-register
(SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples,
then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator
that can automatically oversample and average the ADC results. See Section 5.4. 12-Bit Mode on
page 84 for more details on using the ADC in 12-bit mode.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
single-ended mode and may be configured to measure various different signals using the analog multiplexer described in Section 5.7. ADC0 Analog Multiplexer on page 95. The voltage reference for the ADC
is selected as described in Section 5.9. Voltage and Ground Reference Options on page 100.
AD0EN
BURSTEN
AD0INT
AD0BUSY
AD0WINT
AD0CM2
AD0CM1
AD0CM0
ADC0CN
VDD
Start
Conversion
ADC0TK
Burst Mode Logic
ADC
SYSCLK
REF
16-Bit Accumulator
ADC0H
AIN+
AD0SC4
AD0SC3
AD0SC2
AD0SC1
AD0SC0
AD08BE
AD0TM
AMP0GN
From
AMUX0
10/12-Bit
SAR
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
ADC0L
ADC0PWR
000
001
010
011
100
ADC0LTH ADC0LTL
ADC0CF
ADC0GTH ADC0GTL
AD0WINT
32
Window
Compare
Logic
Rev. 0.3
33
Si102x/3x
AD0MX4
AD0MX3
AD0MX2
AD0MX1
AM0MX0
ADC0MX
P0.0
Programmable
Attenuator
AIN+
P2.6*
AMUX
ADC0
Temp
Sensor
Gain = 0. 5 or 1
VBAT
Digital Supply
VDD/DC+
1.8. Comparators
Si102x/3x devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) which is
shown in Figure 1.9; Comparator 1 (CPT1) which is shown in Figure 1.10. The two comparators operate
identically but may differ in their ability to be used as reset or wake-up sources. See Section 22. Reset
Sources on page 285 and the Section 19. Power Management on page 264 for details on reset sources
and low power mode wake-up sources, respectively.
The comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous latched output (CP0, CP1), or an
asynchronous raw output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
The comparator inputs may be connected to Port I/O pins or to other internal signals.
34
Rev. 0.3
CPT0CN
Si102x/3x
CP0EN
CP0OUT
CP0RIF
CP0FIF
VDD
CP0HYP1
CP0HYP0
CP0HYN1
CP0
Interrupt
CP0HYN0
CPT0MD
CP0RIE
CP0MD1
CP0MD0
Px.x
CP0
Rising-edge
CP0 +
CP0
Falling-edge
Interrupt
Logic
Px.x
CP0
+
SET
CLR
SET
CLR
Px.x
Crossbar
(SYNCHRONIZER)
GND
CP0 -
CP0A
(ASYNCHRONOUS)
Reset
Decision
Tree
Px.x
CPT0CN
CP1EN
CP1OUT
CP1RIF
VDD
CP1FIF
CP1HYP1
CP1
Interrupt
CP1HYP0
CP1HYN1
CP1HYN0
CPT0MD
CP1RIE
CP1MD1
CP1MD0
Px.x
CP1
Rising-edge
CP1 +
CP1
Falling-edge
Interrupt
Logic
Px.x
CP1
+
D
SET
CLR
SET
CLR
Px.x
Crossbar
(SYNCHRONIZER)
CP1 -
GND
(ASYNCHRONOUS)
CP1A
Reset
Decision
Tree
Px.x
Rev. 0.3
35
Si102x/3x
2. Ordering Information
SMBus/I2C
UART
Enhanced SPI
Timers (16-bit)
PCA Channels
Analog Comparators
Package
16
LGA-85 (6x8)
RAM (bytes)
MIPS (Peak)
Si1021-A-GM 25
64
8448 20 128 53
16
LGA-85 (6x8)
Si1022-A-GM 25
32
8448 20 128 53
16
LGA-85 (6x8)
Si1023-A-GM 25
16
4352 20 128 53
16
LGA-85 (6x8)
16
LGA-85 (6x8)
Si1025-A-GM 25
64
8448 13 128 53
16
LGA-85 (6x8)
Si1026-A-GM 25
32
8448 13 128 53
16
LGA-85 (6x8)
Si1027-A-GM 25
16
4352 13 128 53
16
LGA-85 (6x8)
53
16
LGA-85 (6x8)
Si1031-A-GM 25
64
8448 20
53
16
LGA-85 (6x8)
Si1032-A-GM 25
32
8448 20
53
16
LGA-85 (6x8)
Si1033-A-GM 25
16
4352 20
53
16
LGA-85 (6x8)
53
16
LGA-85 (6x8)
Si1035-A-GM 25
64
8448 13
53
16
LGA-85 (6x8)
Si1036-A-GM 25
32
8448 13
53
16
LGA-85 (6x8)
Si1037-A-GM 25
16
4352 13
53
16
LGA-85 (6x8)
36
Rev. 0.3
Si102x/3x
3. Pinout and Package Definitions
Table 3.1. Pin Definitions for the Si102x/3x
Name
Pin
Number
Typ
Description
VBAT
A43
P In
VBATDC
A44
P In
VDC
A46
P In
P Out
GNDDC
A45
P In
GND
D2
Required Ground.
GND
D6
Required Ground.
GND
B16
Required Ground.
GND
B17
Required Ground.
GND
A32
Required Ground.
GND
B28
Required Ground.
IND
B27
P In
VIO
B26
P In
I/O Power Supply for P0.0P1.4 and P2.4P7.0 pins. This supply
voltage must always be VBAT.
VIORF
B29
P In
I/O Power Supply for P1.5P2.3 pins. This supply voltage must
always be VBAT
RST/
A47
D I/O
C2CK
P7.0/
D I/O
A48
D I/O
Port 7.0. This pin can only be used as GPIO. The Crossbar cannot
route signals to this pin and it cannot be configured as an analog
input. See Port I/O Section for a complete description.
Bi-directional data signal for the C2 Debug Interface.
C2D
D I/O
Rev. 0.3
37
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x (Continued)
Name
Pin
Number
Typ
Description
VLCD
A29
P I/O
P0.0
A42
A In
A Out
VREF
P0.1
A41
A40
P0.3
A39
D In
A In
P0.4
A38
P0.5
A37
P0.6
CNVSTR
38
A36
D I/O or A Port 0.5. See Port I/O Section for a complete description.
In
D In
RX
D I/O or A Port 0.4. See Port I/O Section for a complete description.
In
D Out
TX
External Clock Input. This pin is the external oscillator return for a
crystal or resonator. See Oscillator Section.
D I/O or A Port 0.3. See Port I/O Section for a complete description.
In
A Out
XTAL2
D I/O or A Port 0.2. See Port I/O Section for a complete description.
In
A In
XTAL1
D I/O or A Port 0.1. See Port I/O Section for a complete description.
In
G
AGND
P0.2
D I/O or A Port 0.0. See Port I/O Section for a complete description.
In
D I/O or A Port 0.6. See Port I/O Section for a complete description.
In
D In
External Convert Start Input for ADC0. See ADC0 section for a
complete description.
Rev. 0.3
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x (Continued)
Name
Pin
Number
P0.7
A35
IREF0
P1.0
A34
A33
P1.2
A31
D I/O or
A In
D I/O or
A In
A In
XTAL3
P1.3
D I/O or
A In
D I/O
PC1
A30
D I/O or
A In
A Out
XTAL4
Description
D I/O or A Port 0.7. See Port I/O Section for a complete description.
In
A Out IREF0 Output. See IREF Section for complete description.
D I/O
PC0
P1.1
Typ
Port 1.0. See Port I/O Section for a complete description. May
also be used as SCK for SPI0.
Pulse Counter 0.
Port 1.1. See Port I/O Section for a complete description.
May also be used as MISO for SPI0.
Pulse Counter 1.
Port 1.2. See Port I/O Section for a complete description.
May also be used as MOSI for SPI0.
SmaRTClock Oscillator Crystal Input.
Port 1.3. See Port I/O Section for a complete description.
May also be used as NSS for SPI0.
SmaRTClock Oscillator Crystal Output.
P1.4
A28
D I/O or
A In
P1.5
A27
D I/O or
A In
P1.6
A26
D I/O or
A In
P1.7
D7
D I/O or
A In
P2.4
A12
D I/O or
A In
AO
COM0
P2.5
B10
AO
COM1
P2.6
COM2
D I/O or
A In
A11
D I/O or
A In
AO
Rev. 0.3
39
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x (Continued)
Name
Pin
Number
P2.7
A10
A9
A8
A7
A6
A5
A4
A3
A2
LCD8
40
D I/O or
A In
AO
LCD7
P4.0
D I/O or
A In
AO
LCD6
P3.7
D I/O or
A In
AO
LCD5
P3.6
D I/O or
A In
AO
LCD4
P3.5
D I/O or
A In
AO
LCD3
P3.4
D I/O or
A In
AO
LCD2
P3.3
D I/O or
A In
AO
LCD1
P3.2
D I/O or
A In
AO
LCD0
P3.1
D I/O or
A In
AO
COM2
P3.0
Typ
A1
D I/O or
A In
AO
Description
Port 2.7. See Port I/O Section for a complete description.
Rev. 0.3
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x (Continued)
Name
Pin
Number
P4.1
B25
B24
B23
D4/D8
B22
B21
B20
B19
B18
LCD18
D I/O or
A In
AO
LCD17
P5.2
D I/O or
A In
AO
LCD16
P5.1
D I/O or
A In
AO
LCD15
P5.0
D I/O or
A In
AO
LCD14
P4.7
D I/O or
A In
AO
LCD13
P4.6
D I/O or
A In
AO
LCD12
P4.5
D I/O or
A In
AO
LCD11
P4.4
D I/O or
A In
AO
LCD10
P4.3
D I/O or
A In
AO
LCD9
P4.2
Typ
B15
D I/O or
A In
AO
Description
Port 4.1. See Port I/O Section for a complete description.
Rev. 0.3
41
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x (Continued)
Name
Pin
Number
P5.3
B14
B13
B12
B9
B8
B7
B6
B5
B4
LCD28
42
D I/O or
A In
AO
LCD27
P6.4
D I/O or
A In
AO
LCD26
P6.3
D I/O or
A In
AO
LCD25
P6.2
D I/O or
A In
AO
LCD24
P6.1
D I/O or
A In
AO
LCD23
P6.0
D I/O or
A In
AO
LCD22
P5.7
D I/O or
A In
AO
LCD21
P5.6
D I/O or
A In
AO
LCD20
P5.5
D I/O or
A In
AO
LCD19
P5.4
Typ
B3
D I/O or
A In
AO
Description
Port 5.3. See Port I/O Section for a complete description.
Rev. 0.3
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x (Continued)
Name
Pin
Number
P6.5
B2
B1
D I/O or
A In
AO
LCD30
P6.7
D I/O or
A In
AO
LCD29
P6.6
Typ
D1/D5
LCD31
D I/O or
A In
Description
Port 6.5. See Port I/O Section for a complete description.
AO
VDD_RF
A17
P In
TX
A18
AO
RXp
A19
AI
RXn
A20
AI
NC
A16
ANT_A
A21
DO
GPIO_0
A22
D I/O
GPIO_1
A23
D I/O
GPIO_2
A24
D I/O
VR_DIG
D3
P Out
VDD_DIG
A25
P In
nIRQ
B11
DO
General Microcontroller Interrupt Status output. When the EZRadioPRO transceiver exhibits anyone of the Interrupt Events, the
nIRQ pin will be set low. Please see the Control Logic registers
section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading
a corresponding SPI Interrupt Status Registers, Address 03h and
04h. No external resistor pull-up is required, but it may be desirable if multiple interrupt lines are connected.
Rev. 0.3
43
Si102x/3x
Table 3.1. Pin Definitions for the Si102x/3x (Continued)
44
Name
Pin
Number
XOUT
Typ
Description
A13
DI
or
A I/O
XIN
A14
DO
or
A I/O
SDN
A15
DI
Shutdown input pin. SDN should be low in all modes except Shutdown mode. When SDN is high, the radio will be completely shut
down, and the contents of the registers will be lost.
Rev. 0.3
P0.1/AGND/ADC1
B24
P0.3/XTAL2/ADC3
B25
A41
P0.2/XTAL1/ADC2
B26
A42
P4.3/LCD11
GND
B27
A43
P0.0/VREF/ADC0
A2
P6.6/LCD30
B28
A44
P4.2/LCD10
P3.7/LCD7
B29
VBAT
D5
A45
P4.1/LCD9
A1
VBATDC
P4.0/LCD8
A46
VIO
A47
GNDDC
A48
IND
D1
VDC
RSTB/C2CK
P6.7/LCD31
VIORF
P7.0/C2D
Si102x/3x
A40
A39
D4
P4.4/LCD12
D8
A38
P0.4/TX/ADC4
B23
A37
B1
B22
B2
B21
B3
B20
B4
B19
A3
P3.6/LCD6
P6.5/LCD29
P6.4/LCD28
P6.3/LCD27
P3.1/LCD1
A8
P6.0/LCD24
B17
P5.7/LCD23
B16
B8
B15
P5.6/LCD22
P2.6/COM2
B14
B10
B13
B11
B12
A12
P2.4/COM0
nIRQ
XOUT
A13
XIN
A14
P1.5/INT01/ADC9
P5.5/LCD21
A26
D7
P1.4/ADC8
P5.4/LCD20
A27
D6
VLCD
P5.3/LCD19
A28
A11
P2.5/COM1
P1.3/XTAL4
P5.2/LCD18
A29
B9
P1.2/XTAL3
GND
A30
A10
P2.7/COM3
GND
GND
A31
B7
A9
P3.0/LCD0
P1.1/PC1
P5.1/LCD17
A32
Si1020-A-GM
Top View
B6
P6.1/LCD25
P5.0/LCD16
B18
A7
P3.2/LCD2
P1.0/PC0
A33
B5
P6.2/LCD26
P0.7/IREF/ADC7
P4.7/LCD15
A34
A6
P3.3/LCD3
P4.6/LCD14
A35
A5
P3.4/LCD4
P0.6/CNVSTR/ADC6
A36
A4
P3.5/LCD5
P0.5/RX/ADC5
P4.5/LCD13
A25
P1.6/INT01/ADC10
VDD_DIG
A20
A21
A22
A23
A24
GPIO_0
GPIO_1
GPIO_2
A19
ANT_A
A18
RXN
A17
RXP
A16
TX
A15
NC
D2
SDN
GND
VDD_RF
P1.7/ADC11
D3
VR_DIG
Rev. 0.3
45
Si102x/3x
3.1. LGA-85 Package Specifications
3.1.1. Package Drawing
D
A
D3
Pi n A1 ID
E3 E2
E1
(3.385)
D1
8 5X bxb
d dd
D2
e
(bxb)
Min
Nom
Max
0.74
0.84
0.94
0.25
0.30
0.35
6.00 BSC.
D1
2.40
D2
5.50
D3
3.00
0.50 BSC.
8.00 BSC.
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
46
Rev. 0.3
C A B
Si102x/3x
Table 3.2. LGA-85 Package Dimensions (Continued)
Dimension
Min
Nom
Max
E1
5.60
E2
5.00
E3
7.50
L1
0.10
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 0.3
47
Si102x/3x
3.1.2. Land Pattern
C1
P1
DETAIL "A"
C2
P2
(f X f)
(3.385)
f xf
Max (mm)
C1
5.50
C2
7.50
0.50
0.35
P1
2.40
P2
5.60
Notes:
General
1. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance
of 0.05mm is assumed.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask
and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
6. The stencil thickness should be 0.125mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 2x3 array of 0.72x1.45mm openings on 1.77 mm pitch should be used for the center ground pad.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
48
Rev. 0.3
Si102x/3x
3.1.3. Soldering Guidelines
3.1.3.1. Solder Mask Design
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 m minimum, all the way around the pad.
3.1.3.2. Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 2x3 array of 0.72x1.45 mm openings on 1.77 mm pitch should be used for the center ground pad.
Opening size may be reduced as needed to adjust ratio of solder on center ground pad to solder of
signal pins. Excessive solder on center pad may cause opens on signal pins.
3.1.3.3. Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components (>245 C for >20 seconds at peak).
Rev. 0.3
49
Si102x/3x
4. Electrical Characteristics
Throughout the MCU Electrical Characteristics chapter:
Conditions
Min
Typ
Max
Units
55
125
Storage Temperature
65
150
0.3
VIO + 2
0.3
4.0
500
mA
100
mA
200
mA
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
50
Rev. 0.3
Si102x/3x
4.2. MCU Electrical Characteristics
Table 4.2. Global Electrical Characteristics
40 to +85 C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
1.8
Max
Units
3.8
1.4
0.3
0.5
25
MHz
18
ns
18
ns
Specified Operating
Temperature Range
40
+85
Max
Units
Table 4.3. Digital Supply Current at VBAT pin with DC-DC Converter Enabled
40 to +85 C, VBAT = 3.6V, VDC = 1.9V, 24.5 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Digital Supply CurrentCPU Active (Normal Mode, fetching instructions from flash, no external
load)
IBAT 1,2,3
VBAT= 3.0 V
4.5
mA
VBAT= 3.3 V
4.3
mA
VBAT= 3.6 V
4.2
mA
Digital Supply CurrentCPU Inactive (Sleep Mode, sourcing current to external device)
IBAT1
6.5
mA
13
mA
Notes:
1. Based on device characterization data; Not production tested.
2. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained
with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop that accesses an
SFR, and moves data around using the CPU (between accumulator and b-register). The supply current will
vary slightly based on the physical location of this code in flash. As described in the Flash Memory chapter, it
is best to align the jump addresses with a flash word address (byte location /4), to minimize flash accesses
and power consumption.
3. Includes oscillator and regulator supply current.
Rev. 0.3
51
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled
40 to +85 C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
IDD Frequency
Sensitivity
1, 3
4.9
6.2
mA
3.9
mA
175
190
A
A
85
183
A/MHz
VDD = 1.83.8 V, T = 25 C
Digital Supply Current - Active Mode, All Peripharal Clocks Disabled (PCLKACT=0x00)
(CPU Active, fetching instructions from flash)
IDD 3, 4
IDD Frequency
Sensitivity
1, 3
3.9
--
mA
3.1
mA
165
180
A
A
TBD
A/MHz
3.5
mA
2.6
mA
340
360
A
A
2305
VDD = 1.83.8 V, T = 25 C
135
A/MHz
VDD = 1.83.8 V, T = 25 C
52
Rev. 0.3
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
40 to +85 C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current Low Power Idle Mode, All peripheral clocks enabled (PCLKEN = 0x0F)
(CPU Inactive, not fetching instructions from flash)
IDD4, 6
1.5
1.9
mA
1.07
mA
270
280
A
A
2325
VDD = 1.83.8 V, T = 25 C
475
A/MHz
Digital Supply Current Low Power Idle Mode, All Peripheral Clocks Disabled (PCLKEN = 0x00)
(CPU Inactive, not fetching instructions from flash)
IDD4, 7
620
TBD
340
TBD
TBD
A
A
VDD = 1.83.8 V, T = 25 C
115
A/MHz
77
84
VDD = 1.8 V
VDD = 3.8 V
Rev. 0.3
53
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
40 to +85 C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
0.4
0.6
0.8
0.9
1.1
1.3
1.2
1.4
1.6
0.8
1.1
1.4
1.2
1.7
2.0
1.4
1.8
2.1
1.2
1.6
1.8
2.0
1.3
1.8
1.8
2.0
54
Rev. 0.3
Si102x/3x
Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued)
40 to +85 C, 25 MHz system clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
1.8 V, T = 25 C
3.0 V, T = 25 C
3.8 V, T = 25 C
1.8 V, T = 85 C
3.0 V, T = 85 C
3.8 V, T = 85 C
(includes SmaRTClock oscillator and
VBAT Supply Monitor)
0.40
0.60
0.70
1.56
2.38
2.79
1.8 V, T = 25 C
3.0 V, T = 25 C
3.8 V, T = 25 C
1.8 V, T = 85 C
3.0 V, T = 85 C
3.8 V, T = 85 C
(includes SmaRTClock oscillator and
VBAT Supply Monitor)
0.20
0.30
0.40
1.30
2.06
2.41
1.8 V, T = 25 C
3.0 V, T = 25 C
3.8 V, T = 25 C
1.8 V, T = 85 C
3.0 V, T = 85 C
3.8 V, T = 85 C
(includes POR supply monitor)
0.05
0.07
0.11
1.13
1.83
2.25
1.8 V, T = 25 C
3.0 V, T = 25 C
3.8 V, T = 25 C
1.8 V, T = 85 C
3.0 V, T = 85 C
3.8 V, T = 85 C
0.01
0.02
0.03
TBD
TBD
TBD
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Active Current measure using typical code loop - Digital Supply Current depends upon the particular code
being executed. Digital Supply Current depends on the particular code being executed. The values in this
table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop
that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The
supply current will vary slightly based on the physical location of this code in flash. As described in the Flash
Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to
minimize flash accesses and power consumption.
4. Includes oscillator and regulator supply current.
5. Using SmaRTClock osillator with external 32.768 kHz CMOS clock. Does not include crystal bias current.
6. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0F.
7. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00.
Rev. 0.3
55
Si102x/3x
7
6
Active
IDD (mA)
4
Idle
2
LP Idle (PCLKEN=0x0F)
1
LP Idle (PCLKEN=0x00)
0
0
10
15
20
25
Frequency (MHz)
Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25C)
56
Rev. 0.3
30
Si102x/3x
Table 4.5. Port I/O DC Electrical Characteristics
VIO = 1.8 to 3.8 V, 40 to +85 C unless otherwise specified.
Parameters
Conditions
Min
Typ
Max
VIO 0.7
VIO 0.1
Units
See Chart
V
VIO 0.1
See Chart
IOL = 8.5 mA
0.6
IOL = 10 A
0.1
IOL = 25 mA
See Chart
V
Low Drive Strength, PnDRV.n = 0
Input Leakage
Current
IOL = 1.4 mA
0.6
IOL = 10 A
0.1
IOL = 4 mA
See Chart
VIO 0.6
0.7 x VIO
0.6
0.3 x VIO
20
35
Rev. 0.3
57
Si102x/3x
Voltage
3.3
3
VDD = 3.0V
2.7
VDD = 2.4V
2.4
VDD = 1.8V
2.1
1.8
1.5
1.2
0.9
0
10
15
20
25
30
35
40
45
50
Voltage
3.6
3.3
VDD = 3.6V
VDD = 3.0V
2.7
VDD = 2.4V
2.4
VDD = 1.8V
2.1
1.8
1.5
1.2
0.9
0
10 11 12 13 14 15
58
Rev. 0.3
Si102x/3x
Voltage
1.2
VDD = 2.4V
VDD = 1.8V
0.9
0.6
0.3
0
-80
-70
-60
-50
-40
-30
-20
-10
Voltage
1.2
VDD = 2.4V
VDD = 1.8V
0.9
0.6
0.3
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
Rev. 0.3
59
Si102x/3x
Table 4.6. Reset Electrical Characteristics
VDD = 1.8 to 3.8 V, 40 to +85 C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
0.6
VDD 0.6
0.7 x VDD
0.6
0.3 x VDD
20
35
Early Warning
Reset Trigger
(all power modes except Sleep)
1.8
1.85
1.9
1.7
1.75
1.8
A
V
ms
0.45
0.7
1.0
1.75
100
650
1000
10
kHz
10
15
Digital/Analog Monitor
Turn-on Time
300
ns
14
14
60
Rev. 0.3
Si102x/3x
Table 4.7. Power Management Electrical Specifications
VDD = 1.8 to 3.8 V, 40 to +85 C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
SYSCLKs
400
ns
CLKDIV = 0x00
Low Power or Precision Osc.
Parameter
Flash Size
Conditions
Si1020/24/30/34
Si1021/25/31/35
Si1022/26/32/36
Si1023/27/33/37
Endurance
Erase Cycle Time
Write Cycle Time
Min
131072
65536
32768
16384
Typ
Max
20 k
100k
28
57
32
64
36
71
Units
bytes
bytes
bytes
bytes
Erase/Write
Cycles
ms
s
Parameter
Oscillator Frequency
Oscillator Supply Current
(from VDD)
Conditions
40 to +85 C,
VDD = 1.83.8 V
25 C; includes bias current
of 50 A typical
Min
Typ
Max
Units
24
24.5
25
MHz
300*
*Note: Does not include clock divider or clock tree supply current.
Parameter
Oscillator Frequency
Oscillator Supply Current
(from VDD)
Conditions
40 to +85 C,
VDD = 1.83.8 V
25 C
No separate bias current
required
Min
Typ
Max
Units
18
20
22
MHz
100*
*Note: Does not include clock divider or clock tree supply current.
Rev. 0.3
61
Si102x/3x
Table 4.11. SmaRTClock Characteristics
VDD = 1.8 to 3.8 V; TA = 40 to +85 C unless otherwise specified; Using factory-calibrated settings.
Parameter
Oscillator Frequency (LFO)
Conditions
Min
13.1
Typ
16.4
Max
19.7
Units
kHz
Conditions
Min
Typ
Max
Units
12-bit mode
10-bit mode
12-bit mode1
10-bit mode
12
10
1
0.5
3
1
LSB
12-bit mode1
10-bit mode
0.8
0.5
2
1
LSB
12-bit mode
10-bit mode
12-bit mode2
10-bit mode
<1
<1
1
1
3
3
4
2.5
DC Accuracy
Resolution
Integral Nonlinearity
Differential Nonlinearity
(Guaranteed Monotonic)
Offset Error
Full Scale Error
bits
LSB
LSB
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, maximum
sampling rate)
Signal-to-Noise Plus Distortion3
Signal-to-Distortion3
Spurious-Free Dynamic Range3
12-bit mode
10-bit mode
12-bit mode
10-bit mode
12-bit mode
10-bit mode
62
54
65
58
76
73
82
75
13
11
8.33
4.4
1.5
1.1
us
75
300
ksps
dB
dB
dB
Conversion Rate
SAR Conversion Clock
Conversion Time in SAR Clocks
Track/Hold Acquisition Time
Throughput Rate
MHz
clocks
1. INL and DNL specifications for 12-bit mode do not include the first or last four ADC codes.
2. The maximum code in 12-bit mode is 0xFFFC. The Full Scale Error is referenced from the maximum code.
3. Performance in 8-bit mode is similar to 10-bit mode.
62
Rev. 0.3
Si102x/3x
Table 4.12. ADC0 Electrical Characteristics (Continued)
VDD = 1.8 to 3.8 V, VREF = 1.65 V (REFSL[1:0] = 11), 40 to +85 C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
VREF
Single Ended
VDD
1x Gain
0.5x Gain
16
13
pF
650
740
Analog Inputs
ADC Input Voltage Range
Absolute Pin Voltage with respect
to GND
Sampling Capacitance
Input Multiplexer Impedance
Power Specifications
370
400
67
74
dB
1. INL and DNL specifications for 12-bit mode do not include the first or last four ADC codes.
2. The maximum code in 12-bit mode is 0xFFFC. The Full Scale Error is referenced from the maximum code.
3. Performance in 8-bit mode is similar to 10-bit mode.
Conditions
Min
Typ
Max
Units
Linearity
Slope
3.40
mV/C
Slope Error*
40
V/C
Offset
Temp = 25 C
1025
mV
Offset Error*
Temp = 25 C
18
mV
1.7
Supply Current
35
Rev. 0.3
63
Si102x/3x
Table 4.14. Voltage Reference Electrical Characteristics
VDD = 1.8 to 3.8 V, 40 to +85 C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
1.62
1.65
1.68
1.5
260
140
VDD
5.25
40 to +85 C,
VDD = 1.83.8 V
64
Rev. 0.3
Si102x/3x
Table 4.15. IREF0 Electrical Characteristics
VDD = 1.8 to 3.8 V, 40 to +85 C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Static Performance
Resolution
bits
0
0
0.3
0.8
VDD 0.4
VDD 0.8
VDD
VDD
Integral Nonlinearity
<0.2
1.0
LSB
Differential Nonlinearity
<0.2
1.0
LSB
Offset Error
<0.1
0.5
LSB
<1
300
ns
Startup Time
IREF0DAT = 000001
10
IREF0DAT = 111111
10
IREF0DAT = 000001
10
IREF0DAT = 111111
10
IREF0DAT = 000001
IREF0DAT = 111111
11
IREF0DAT = 000001
12
IREF0DAT = 111111
81
Power Consumption
Net Power Supply Current
(VDD supplied to IREF0 minus
any output source current)
Note: Refer to 7.1. PWM Enhanced Mode on page 110 for information on how to improve IREF0 resolution.
Rev. 0.3
65
Si102x/3x
Table 4.16. Comparator Electrical Characteristics
VDD = 1.8 to 3.8 V, 40 to +85 C unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Response Time:
Mode 0, VDD = 2.4 V, VCM* = 1.2 V
120
ns
110
ns
180
ns
220
ns
350
ns
600
ns
1240
ns
3200
ns
1.5
mV/V
0.25
VDD + 0.25
Input Capacitance
12
pF
nA
10
+10
mV
0.1
mV/V
VDD = 3.8 V
0.6
VDD = 3.0 V
1.0
VDD = 2.4 V
1.8
VDD = 1.8 V
10
Mode 0
23
Mode 1
8.8
Response Time:
Mode 1, VDD = 2.4 V, VCM* = 1.2 V
Response Time:
Mode 2, VDD = 2.4 V, VCM* = 1.2 V
Response Time:
Mode 3, VDD = 2.4 V, VCM* = 1.2 V
Power-up Time
Supply Current at DC
Mode 2
2.6
Mode 3
0.4
66
Rev. 0.3
Si102x/3x
Table 4.16. Comparator Electrical Characteristics (Continued)
VDD = 1.8 to 3.8 V, 40 to +85 C unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Hysteresis 1
(CPnHYP/N10 = 00)
mV
Hysteresis 2
(CPnHYP/N10 = 01)
8.5
mV
Hysteresis 3
(CPnHYP/N10 = 10)
17
mV
Hysteresis 4
(CPnHYP/N10 = 11)
34
mV
Hysteresis 1
(CPnHYP/N10 = 00)
mV
Hysteresis 2
(CPnHYP/N10 = 01)
6.5
mV
Hysteresis 3
(CPnHYP/N10 = 10)
13
mV
Hysteresis 4
(CPnHYP/N10 = 11)
26
mV
Hysteresis 1
(CPnHYP/N10 = 00)
mV
Hysteresis 2
(CPnHYP/N10 = 01)
10
mV
Hysteresis 3
(CPnHYP/N10 = 10)
10
20
mV
Hysteresis 4
(CPnHYP/N10 = 11)
12
20
30
mV
Hysteresis 1
(CPnHYP/N10 = 00)
mV
Hysteresis 2
(CPnHYP/N10 = 01)
4.5
mV
Hysteresis 3
(CPnHYP/N10 = 10)
mV
Hysteresis 4
(CPnHYP/N10 = 11)
17
mV
Hysteresis
Mode 0
Mode 1
Mode 2
Mode 3
Parameter
Conditions
Rev. 0.3
Min
Typ
Max
Units
1.8
3.8
20
67
Si102x/3x
Table 4.18. LCD0 Electrical Characteristics
VDD = 1.8 to 3.8 V; TA = 40 to +85 C unless otherwise specified; Using factory-calibrated settings.
Parameter
Conditions
Min
Typ
Max
Units
30
mV
16
33
kHz
Parameter
Supply Current
(25 C, 2 ms sample rate)
68
Conditions
Min
Typ
Max
1.8 V
145
2.2 V
175
3.0 V
235
3.8 V
285
Rev. 0.3
Units
nA
Si102x/3x
Table 4.20. DC0 (Buck Converter) Electrical Characteristics
VDD = 1.8 to 3.8 V; TA = 40 to +85 C unless otherwise specified; Using factory-calibrated settings.
Parameter
Min
Typ
Max
Units
1.8
3.8
0.45
1.8
1.9
3.5
250
mW
85
mA
0.47
0.56
0.68
450
550
mA
2.2
10
4.7
853
703
503
104
mA
Output = 1.9 V;
Load current up-to 85 mA;
Supply range = 2.43.8 V
0.03
mv/mA
mA
1.9
2.9
3.8
MHz
Condition
Load Regulation
Notes:
1. Recommended: Inductor similar to NLV32T-R56J-PF (0.56 H)
2. Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with
ESR < 10 m ( @ frequency > 1 MHz)
Rev. 0.3
69
Si102x/3x
4.3. EZRadioPRO Peripheral Electrical Characteristics
Table 4.21. DC Characteristics1
Parameter
Supply Voltage
Range
Symbol
Min
Typ
Max
Units
1.8
3.0
3.6
15
50
nA
IStandby
450
800
nA
ISleep
ISensor-
ISensor-TS
IReady
800
ITune
8.5
mA
18.5
mA
VDD_RF
LBD
Conditions
IRX
TX Mode Current
Si1020/21/22/23/30/
31/32/33
ITX_+20
85
mA
TX Mode Current
Si1024/25/26/27/34/
35/36/37
ITX_+13
30
mA
ITX_+1
17
mA
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 77.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions"
section on page 77.
70
Rev. 0.3
Si102x/3x
Table 4.22. Synthesizer AC Electrical Characteristics1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
240
960
MHz
Synthesizer Frequency
Range
FSYN
Synthesizer Frequency
Resolution2
FRES-LB
156.25
Hz
FRES-HB
312.5
Hz
fREF_LV
0.7
1.6
tLOCK
200
Residual FM2
FRMS
kHzRMS
Phase Noise2
L(fM)
F = 10 kHz
80
dBc/Hz
F = 100 kHz
90
dBc/Hz
F = 1 MHz
115
dBc/Hz
F = 10 MHz
130
dBc/Hz
Reference Frequency
Input Level2
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 77.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section
on page 77.
Rev. 0.3
71
Si102x/3x
Table 4.23. Receiver AC Electrical Characteristics1
Parameter
RX Frequence Range
RX Sensitivity2
Symbol
FRX
PRX_2
PRX_40
PRX_100
PRX_125
PRX_OOK
Conditions
(BER < 0.1%)
(2 kbps, GFSK, BT = 0.5,
f = 5 kHz)3
(BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)3
(BER < 0.1%)
(100 kbps, GFSK, BT = 0.5,
f = 50 kHz)3
(BER < 0.1%)
(125 kbps, GFSK, BT = 0.5,
f = 62.5 kHz)
(BER < 0.1%)
(4.8 kbps, 350 kHz BW, OOK)3
(BER < 0.1%)
(40 kbps, 400 kHz BW, OOK)3
RX Channel Bandwidth3
BER Variation vs Power
Level3
LNA Input Impedance3
(Unmatchedmeasured
differentially across RX
input pins)
BW
PRX_RES
RIN-RX
915 MHz
RSSI Resolution
1-Ch Offset Selectivity3
RESRSSI
C/I1-CH
868 MHz
433 MHz
315 MHz
Min
240
Typ
121
Max
960
Units
MHz
dBm
108
dBm
104
dBm
101
dBm
110
dBm
102
dBm
2.6
620
0.1
kHz
ppm
5160j
5463j
89110j
107137j
0.5
31
dB
dB
35
dB
40
dB
52
dB
56
dB
63
dB
30
dB
54
dBm
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 77.
2. Receive sensitivity at multiples of 30 MHz may be degraded. If channels with a multiple of 30 MHz are required
it is recommended to shift the crystal frequency. Contact Silicon Labs Applications Support for
recommendations.
3. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section
on page 77.
72
Rev. 0.3
Si102x/3x
Table 4.24. Transmitter AC Electrical Characteristics1
Parameter
TX Frequency Range
Symbol
Conditions
Min
Typ
Max
Units
FTX
240
960
MHz
DRFSK
0.123
256
kbps
DROOK
0.123
40
kbps
320
kHz
Modulation Deviation
Modulation Deviation
Resolution2
Output Power Range
Si1020/21/22/23/30/31/32/333
Output Power Range
Si1024/25/26/27/34/35/36/373
TX RF Output Steps2
f1
860960 MHz
0.625
f2
240860 MHz
0.625
160
kHz
fRES
0.625
kHz
PTX
+1
+20
dBm
PTX
+13
dBm
PRF_OUT
controlled by txpow[2:0]
dB
PRF_TEMP
40 to +85 C
dB
PRF_FREQ
dB
Transmit Modulation
Filtering2
B*T
0.5
Spurious Emissions2
POB-TX1
POUT = 11 dBm,
Frequencies <1 GHz
54
dBm
POB-TX2
54
dBm
P2HARM
42
dBm
42
dBm
TX RF Output Level
Variation vs. Temperature
TX RF Output Level
Variation vs. Frequency2
Harmonics2
P3HARM
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 77.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section
on page 77.
3. Output power is dependent on matching components, board layout, and is measured at the pin.
Rev. 0.3
73
Si102x/3x
Table 4.25. Auxiliary Block Specifications1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Temperature Sensor
Accuracy2
TSA
0.5
Temperature Sensor
Sensitivity2
TSS
mV/C
LBDRES
50
mV
LBDCT
250
Microcontroller Clock
Output Frequency
FMC
32.768k
30M
Hz
ADCENB
bit
ADCRES
mV/bit
ADCCT
305
Configurable to
30 MHz, 15 MHz,
10 MHz, 4 MHz, 3 MHz,
2 MHz, 1 MHz, or
32.768 kHz
t30M
600
30MRES
97
fF
t32k
sec
32KRCRES
1000
ppm
t32kRC
500
9.5
ms
250
tPOR
tsoft
Current consumption
during POR time is
200 A typical
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max
limits are listed in the "Production Test Conditions" section on page 77.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section
on page 77.
74
Rev. 0.3
Si102x/3x
Table 4.26. Digital IO Specifications (nIRQ)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Rise Time
TRISE
ns
Fall Time
TFALL
ns
Input Capacitance
CIN
pF
VIH
VDD_RF 0.6
0.6
IIN
0<VIN< VDD_RF
100
100
nA
VOH
VDD_RF 0.6
VOL
0.6
VIL
Note: All specifications guaranteed by qualification. Qualification test conditions are listed in the "Production Test
Conditions" section on page 77.
Symbol
Conditions
Min
Typ
Max
Units
Rise Time
TRISE
ns
Fall Time
TFALL
ns
pF
Input Capacitance
CIN
VIH
VDD_RF 0.6
VIL
0.6
IIN
0<VIN< VDD_RF
100
100
nA
IINP
VIL = 0 V
25
IOmaxLL
DRV<1:0> = LL
0.1
0.5
0.8
mA
IOmaxLH
DRV<1:0> = LH
0.9
2.3
3.5
mA
IOmaxHL
DRV<1:0> = HL
1.5
3.1
4.8
mA
IOmaxHH
DRV<1:0> = HH
1.8
3.6
5.4
mA
VOH
VDD_RF 0.6
VOL
0.6
Note: All specifications guaranteed by qualification. Qualification test conditions are listed in the "Production Test
Conditions" section on page 77.
Rev. 0.3
75
Si102x/3x
Table 4.28. Absolute Maximum Ratings
Parameter
Value
Unit
VDD_RF to GND
0.3, +3.6
0.3, +8.0
0.3, +6.5
+10
dBm
40 to +85
Thermal Impedance JA
30
C/W
Junction Temperature TJ
+125
55 to +125
RX Input Power
Operating Ambient Temperature Range TA
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at or beyond these ratings in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Power Amplifier may be damaged if switched on without proper
load or termination connected. TX matching network design will influence TX VRF-peak on TX output pin.
Caution: ESD sensitive device.
76
Rev. 0.3
Si102x/3x
4.4. Definition of Test Conditions for the EZRadioPRO Peripheral
Production Test Conditions:
TA = +25 C
TA = 40 to +85 C
Rev. 0.3
77
Si102x/3x
5. SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode
The ADC0 on Si102x/3x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation-register
(SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples,
then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator
that can automatically oversample and average the ADC results. See Section 5.4 for more details on using
the ADC in 12-bit mode.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
Single-ended mode and may be configured to measure various different signals using the analog multiplexer described in 5.7. ADC0 Analog Multiplexer on page 95. The voltage reference for the ADC is
selected as described in 5.9. Voltage and Ground Reference Options on page 100.
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0INT
AD0BUSY
AD0EN
BURSTEN
ADC0CN
VDD
Start
Conversion
ADC0TK
Burst Mode Logic
ADC0PWR
ADC
Timer 2 Overflow
011
Timer 3 Overflow
100
CNVSTR Input
REF
16-Bit Accumulator
SYSCLK
AD0TM
AMP0GN
AD08BE
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
ADC0CF
Timer 0 Overflow
010
ADC0L
10/12-Bit
SAR
AIN+
AD0BUSY (W)
001
ADC0H
From
AMUX0
000
AD0WINT
32
ADC0LTH ADC0LTL
Window
Compare
Logic
ADC0GTH ADC0GTL
78
Rev. 0.3
Si102x/3x
Input Voltage
Right-Justified ADC0H:ADC0L
(AD0SJST = 000)
Left-Justified ADC0H:ADC0L
(AD0SJST = 100)
VREF x 1023/1024
0x03FF
0xFFC0
VREF x 512/1024
0x0200
0x8000
VREF x 256/1024
0x0100
0x4000
0x0000
0x0000
When the repeat count is greater than 1, the output conversion code represents the accumulated result of
the conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8,
16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0AC register. When a repeat count higher
than 1, the ADC output must be right-justified (AD0SJST = 0xx); unused bits in the ADC0H and ADC0L
registers are set to 0. The example below shows the right-justified result for various input voltages and
repeat counts. Notice that accumulating 2n samples is equivalent to left-shifting by n bit positions when all
samples returned from the ADC have the same value.
Input Voltage
Repeat Count = 4
Repeat Count = 16
Repeat Count = 64
VREF x 1023/1024
0x0FFC
0x3FF0
0xFFC0
VREF x 512/1024
0x0800
0x2000
0x8000
VREF x 511/1024
0x07FC
0x1FF0
0x7FC0
0x0000
0x0000
0x0000
The AD0SJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions. Based on the principles of oversampling and averaging, the
effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4.
The example below shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12-bit, or 13-bit respectively without CPU intervention.
Input Voltage
Repeat Count = 4
Shift Right = 1
11-Bit Result
Repeat Count = 16
Shift Right = 2
12-Bit Result
Repeat Count = 64
Shift Right = 3
13-Bit Result
VREF x 1023/1024
0x07F7
0x0FFC
0x1FF8
VREF x 512/1024
0x0400
0x0800
0x1000
VREF x 511/1024
0x03FE
0x04FC
0x0FF8
0x0000
0x0000
0x0000
Rev. 0.3
79
Si102x/3x
5.2. Modes of Operation
ADC0 has a maximum conversion speed of 300 ksps in 10-bit mode. The ADC0 conversion clock (SARCLK) is a divided version of the system clock when burst mode is disabled (BURSTEN = 0), or a divided
version of the low power oscillator when burst mode is enabled (BURSEN = 1). The clock divide value is
determined by the AD0SC bits in the ADC0CF register.
5.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM20) in register ADC0CN. Conversions may be initiated by one of the following:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 3 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be
used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic 1.
When Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if
Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See 33. Timers on
page 491 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to 1 Bit 6 in register P0SKIP. See 27. Port Input/Output on page 358 for details on Port I/O configuration.
5.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in Table 4.12. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0 input is
continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0
operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking
period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate
conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on
the rising edge of CNVSTR (see Figure 5.2). Tracking can also be disabled (shutdown) when the device is
in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings
are frequently changed, due to the settling time requirements described in 5.2.4. Settling Time Requirements on page 83.
80
Rev. 0.3
Si102x/3x
A. ADC0 Timing for External Trigger Source
CNVSTR
(AD0CM[2:0]=100)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SAR Clocks
AD0TM=1
AD0TM=0
Low Power
or Convert
Track
Track or Convert
Convert
Low Power
Mode
Convert
Track
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SAR
Clocks
AD0TM=1
Low Power
Track
or Convert
Convert
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SAR
Clocks
AD0TM=0
Track or
Convert
Convert
Track
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0)
Rev. 0.3
81
Si102x/3x
5.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conversions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or
64 using an internal Burst Mode clock (approximately 20 MHz), then re-enters a low power state. Since the
Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a
low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 kHz), or
suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3 shows an example of Burst Mode Operation with a slow system clock and a repeat count of 4.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after repeat count conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until repeat count conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for
these registers will work in most applications without modification; however, settling time requirements may
need adjustment in some applications. Refer to 5.2.4. Settling Time Requirements on page 83 for more
details.
Notes:
Setting AD0TM to 1 will insert an additional 3 SAR clocks of tracking before each conversion,
regardless of the settings of AD0PWR and AD0TK.
When using Burst Mode, care must be taken to issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
System Clock
Convert Start
AD0TM = 1
AD0EN = 0
Powered
Down
Power-Up
and Track
T
T
T
T
C T
C T
C T
C
3
3
3
3
AD0TM = 0
AD0EN = 0
Powered
Down
Power-Up
and Track
C T C T C T C
AD0PWR
AD0TK
Powered
Down
Powered
Down
Power-Up
and Track
T C..
Power-Up
and Track
T C..
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
82
Rev. 0.3
Si102x/3x
5.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
For many applications, these three SAR clocks will meet the minimum tracking time requirements, and
higher values for the external source impedance will increase the required tracking time.
Figure 5.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation . When measuring the Temperature Sensor output or
VDD with respect to GND, RTOTAL reduces to RMUX. See Table 4.12 for ADC0 minimum settling time
requirements as well as the mux impedance and sampling capacitor values.
n
2
t = ln ------- R TOTAL C SAMPLE
SA
ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
MUX Select
P0.x
R MUX
C SAMPLE
RCInput= R MUX * C SAMPLE
Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.12 for details.
Rev. 0.3
83
Si102x/3x
5.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
84
Rev. 0.3
Si102x/3x
5.5. Low Power Mode
The SAR converter provides a low power mode that allows a significant reduction in operating current
when operating at low SAR clock frequencies. Low power mode is enabled by setting the AD0LPM bit
(ADC0PWR.7) to 1. In general, low power mode is recommended when operating with SAR conversion
clock frequency at 4 MHz or less. See the Electrical Characteristics chapter for details on power consumption and the maximum clock frequencies allowed in each mode. Setting the Low Power Mode bit reduces
the bias currents in both the SAR converter and in the High-Speed Voltage Reference.
Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC
with 1.65 V High-Speed VREF
Normal Power Mode
8 bit
10 bit
12 bit
8 bit
10 bit
12 bit
Highest nominal
SAR clock
frequency
8.17 MHz
(24.5/3)
8.17 MHz
(24.5/3)
6.67 MHz
(20.0/3)
4.08
MHz
(24.5/6)
4.08
MHz
(24.5/6)
4.00 MHz
(20.0/5)
Total number of
conversion clocks
required
11
13
52 (13 x 4)
11
13
52 (13*4)
1.5 s
1.5 s
4.8 s
(1.5+3 x 1.1)
1.5 s
1.5 s
4.8 s
(1.5+3 x 1.1)
2.85 s
3.09 s
12.6 s
4.19 s
4.68 s
17.8 s
ADC Throughput
351 ksps
323 ksps
79 ksps
238 ksps
214 ksps
56 ksps
Energy per
conversion
8.2 nJ
8.9 nJ
36.5 nJ
6.5 nJ
7.3 nJ
27.7 nJ
Note: This table assumes that the 24.5 MHz precision oscillator is used for 8- and 10-bit modes, and the 20 MHz
low power oscillator is used for 12-bit mode. The values in the table assume that the oscillators run at their
nominal frequencies. The maximum SAR clock values given in Table 4.12 allow for maximum oscillation
frequencies of 25.0 MHz and 22 MHz for the precision and low-power oscillators, respectively, when using
the given SAR clock divider values. Energy calculations are for the ADC subsystem only and do not include
CPU current.
Rev. 0.3
85
Si102x/3x
SFR Definition 5.1. ADC0CN: ADC0 Control
Bit
Name
AD0EN
BURSTEN
AD0INT
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
AD0BUSY AD0WINT
ADC0CM[2:0]
R/W
0
Bit
Name
AD0EN
Function
ADC0 Enable.
0: ADC0 Disabled (low-power shutdown).
1: ADC0 Enabled (active and ready for data conversions).
BURSTEN
AD0INT
AD0BUSY
ADC0 Busy.
Writing 1 to this bit initiates an ADC conversion when ADC0CM[2:0] = 000.
AD0WINT
2:0
86
Rev. 0.3
Si102x/3x
Name
AD0SC[4:0]
AD08BE
AD0TM
AMP0GN
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
Bit
7:3
Name
Function
FCLK
AD0SC = -------------------- 1 *
CLK SAR
*Round the result up.
or
FCLK
CLK SAR = ---------------------------AD0SC + 1
2
AD08BE
AD0TM
AMP0GN
Rev. 0.3
87
Si102x/3x
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration
Bit
Name AD012BE
AD0AE
AD0SJST[2:0]
AD0RPT[2:0]
R/W
R/W
Typ
R/W
Zurücksetzen
Bit
Name
AD012BE
Function
ADC0 12-Bit Mode Enable.
Enables 12-bit Mode.
0: 12-bit Mode Disabled.
1: 12-bit Mode Enabled.
AD0AE
5:3
2:0
88
Rev. 0.3
Si102x/3x
Name
AD0LPM
Typ
R/W
Zurücksetzen
AD0PWR[3:0]
R/W
1
Bit
Name
AD0LPM
Function
ADC0 Low Power Mode Enable.
Enables Low Power Mode Operation.
0: Low Power Mode disabled.
1: Low Power Mode enabled.
6:4
3:0
Unused
Tstartup
AD0PWR = ---------------------- 1
400ns
or
Rev. 0.3
89
Si102x/3x
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time
Bit
Name
AD0TK[5:0]
Typ
Zurücksetzen
R/W
0
Bit
Name
Reserved
Unused
5:0
Function
Read = 0b; Write = Must Write 0b.
Read = 0b; Write = Dont Care.
Ttrack
AD0TK = 63 ----------------- 1
50ns
oder
90
Rev. 0.3
Si102x/3x
Name
ADC0[15:8]
Typ
R/W
Zurücksetzen
Lesen
Write
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register
should not be written when the SYNC bit is set to 1.
Name
ADC0[7:0]
Typ
R/W
Zurücksetzen
ADC0[7:0]
Lesen
Write
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be the least significant bits of
the accumulator high byte. This register should not be written when the SYNC bit is set to 1.
Rev. 0.3
91
Si102x/3x
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte
Bit
Name
AD0GT[15:8]
Typ
R/W
Zurücksetzen
Function
Name
AD0GT[7:0]
Typ
R/W
Zurücksetzen
Function
92
Rev. 0.3
Si102x/3x
Name
AD0LT[15:8]
Typ
R/W
Zurücksetzen
Bit
7:0
Name
Function
Name
AD0LT[7:0]
Typ
R/W
Zurücksetzen
Bit
7:0
Name
Function
Rev. 0.3
93
Si102x/3x
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
0x03FF
0x03FF
AD0WINT
not affected
AD0WINT=1
0x0081
VREF x (128/1024)
0x0080
0x0081
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x007F
0x0080
0x007F
AD0WINT=1
VREF x (64/1024)
0x0041
0x0040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x003F
0x0041
0x0040
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x003F
AD0WINT=1
AD0WINT
not affected
0
0x0000
0x0000
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
0xFFC0
0xFFC0
AD0WINT
not affected
AD0WINT=1
0x2040
VREF x (128/1024)
0x2000
0x2040
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x1FC0
0x2000
0x1FC0
AD0WINT=1
0x1040
VREF x (64/1024)
0x1000
0x1040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x0FC0
0x1000
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x0FC0
AD0WINT=1
AD0WINT
not affected
0
0x0000
0x0000
94
Rev. 0.3
Si102x/3x
5.7. ADC0 Analog Multiplexer
ADC0 on Si102x/3x has an analog multiplexer, referred to as AMUX0.
AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, the VBAT Power Supply, Regulated Digital
Supply Voltage (Output of VREG0), VDC Supply, or the positive input may be connected to GND. The
ADC0 input channels are selected in the ADC0MX register described in SFR Definition 5.12.
AM0MX0
AD0MX2
AD0MX1
AD0MX3
AD0MX4
ADC0MX
P0.0
Programmable
Attenuator
AIN+
P2.3*
AMUX
ADC0
Temp
Sensor
Gain = 0.5 or 1
VBAT
Digital Supply
VDC
Rev. 0.3
95
Si102x/3x
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select
Bit
AD0MX
Name
Type
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Unused
AD0MX
Function
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Reserved
Reserved
Reserved
Reserved
P1.4
P1.5
P1.6
P1.7
10000:
10001:
10010:
10011:
10100:
10101:
10110:
10111:
11000:
11001:
11010:
11011:
11100:
P2.0
P2.1
P2.2
P2.3
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Temperature Sensor
VBAT Supply Voltage
(1.83.6 V)
11101:
11110:
11111:
96
Rev. 0.3
Si102x/3x
5.8. Temperature Sensor
An on-chip temperature sensor is included on the Si102x/3x which can be directly accessed via the ADC
multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC
mux channel should select the temperature sensor. The temperature sensor transfer function is shown in
Figure 5.8. The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set correctly.
The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in SFR
Definition 5.15. REF0CN: Voltage Reference Control. While disabled, the temperature sensor defaults to a
high impedance state and any ADC measurements performed on the sensor will result in meaningless
data. Refer to Table 4.12 for the slope and offset parameters of the temperature sensor.
Voltage
Slope ( V / deg C)
Offset ( V at 25 Celsius)
Temperature
Figure 5.8. Temperature Sensor Transfer Function
5.8.1. Calibration
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 4.13 for linearity specifications). For absolute temperature measurements, offset
and/or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
1. Control/measure the ambient temperature (this temperature must be known).
2. Power the device, and delay for a few seconds to allow for self-heating.
3. Perform an ADC conversion with the temperature sensor selected as the positive input and GND
selected as the negative input.
4. Calculate the offset characteristics, and store this value in non-volatile memory for use with
subsequent temperature sensor measurements.
Rev. 0.3
97
Si102x/3x
Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 C. Parameters that affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement.
Error (degrees C)
A single-point offset measurement of the temperature sensor is performed on each device during production test. The measurement is performed at 25 C 5 C, using the ADC with the internal high speed reference buffer selected as the Voltage Reference. The direct ADC result of the measurement is stored in the
SFR registers TOFFH and TOFFL, shown in SFR Definition 5.13 and SFR Definition 5.14.
5.00
5.00
4.00
4.00
3.00
3.00
2.00
2.00
1.00
1.00
0.00
-40.00
-20.00
40.00
0.00
20.00
60.00
0.00
80.00
-1.00
-1.00
-2.00
-2.00
-3.00
-3.00
-4.00
-4.00
-5.00
-5.00
Temperature (degrees C)
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V)
98
Rev. 0.3
Si102x/3x
Name
TOFF[9:2]
Typ
Zurücksetzen
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
TOFF[9:2]
Function
Name
TOFF[1:0]
Typ
Zurücksetzen
Varies
Varies
TOFF[1:0]
5:0
Unused
Function
Rev. 0.3
99
Si102x/3x
5.9. Voltage and Ground Reference Options
The voltage reference MUX is configurable to use an externally connected voltage reference, the internal
voltage reference, or one of two power supply voltages (see Figure 5.10). The ground reference MUX
allows the ground reference for ADC0 to be selected between the ground pin (GND) or a port pin dedicated to analog ground (P0.1/AGND).
The voltage and ground reference options are configured using the REF0CN SFR described on SFR
Definition 5.15. REF0CN: Voltage Reference Control. Electrical specifications are can be found in the
Electrical Specifications Chapter.
Important Note About the VREF and AGND Inputs: Port pins are used as the external VREF and AGND
inputs. When using an external voltage reference or the internal precision reference, P0.0/VREF should be
configured as an analog input and skipped by the Digital Crossbar. When using AGND as the ground reference to ADC0, P0.1/AGND should be configured as an analog input and skipped by the Digital Crossbar.
Refer to Section 27. Port Input/Output on page 358 for complete Port I/O configuration details. The external reference voltage must be within the range 0 VREF VDD and the external ground reference must be
at the same DC voltage potential as GND.
VDD
R1
REFOE
REFGND
REFSL1
REFSL0
TEMPE
R E F 0C N
Te m p S enso r
EN
ADC
In put
M ux
E xternal
V olta ge
R e ference
C ircuit
P 0.0/V R E F
00
VBAT
01
Intern al 1 .8V
R e gu late d D ig ital S up ply
GND
10
VREF
(to A D C )
11
4.7 F
Intern al 1.65V
H igh S p ee d R e ference
0 .1 F
GND
0
R eco m m en ded
B yp ass C apa citors
P 0 .1/A G N D
R E FG N D
100
Rev. 0.3
G rou nd
(to A D C )
Si102x/3x
5.10. External Voltage Reference
To use an external voltage reference, REFSL[1:0] should be set to 00. Bypass capacitors should be added
as recommended by the manufacturer of the external voltage reference. If the manufacturer does not provide recommendations, a 4.7uF in parallel with a 0.1uF capacitor is recommended.
Rev. 0.3
101
Si102x/3x
SFR Definition 5.15. REF0CN: Voltage Reference Control
Bit
Name
REFGND
3
REFSL
TEMPE
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
Function
4:3
REFSL
TEMPE
1:0
Unused
102
Rev. 0.3
Si102x/3x
6. Comparators
Si102x/3x devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is
shown in Figure 6.1; Comparator 1 (CPT1) is shown in Figure 6.2. The two comparators operate identically, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources chapter
and the Power Management chapter for details on reset sources and low power mode wake-up sources,
respectively.
The comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the port pins: a synchronous output (CP0, CP1), or an asynchronous output (CP0A, CP1A). The asynchronous CP0A signal is available even when the system clock is not
active. This allows the comparator to operate and generate an output when the device is in some low
power modes.
CPT0CN
Important Note About Comparator Inputs: The port pins selected as comparator inputs should be configured as analog inputs and skipped by the crossbar. See "27. Port Input/Output" on page 358 for more
details on how to configure port I/O pins as analog inputs. The comparator may also be used to compare
the logic level of digital signals, however, port I/O pins configured as digital inputs must be driven to a valid
logic state (HIGH or LOW) to avoid increased power consumption.
CP0EN
CP0OUT
CP0RIF
VDD
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0
Interrupt
CPT0MD
CP0RIE
CP0MD1
CP0MD0
Px.x
CP0
Rising-edge
CP0 +
CP0
Falling-edge
Interrupt
Logic
Px.x
CP0
+
D
SET
CLR
SET
CLR
Px.x
Crossbar
(SYNCHRONIZER)
CP0 -
GND
(ASYNCHRONOUS)
Px.x
CP0A
Reset
Decision
Tree
Rev. 0.3
103
Si102x/3x
6.2. Comparator Outputs
When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the
voltage at the negative input. When disabled, the comparator output is a logic 0. The comparator output is
synchronized with the system clock as shown in Figure 6.2. The synchronous output (CP0, CP1) can be
polled in software (CPnOUT bit), used as an interrupt source, or routed to a port pin through the crossbar.
The asynchronous comparator output (CP0A, CP1A) is used by the low power mode wakeup logic and
reset decision logic. See "19. Power Management" on page 264 and "22. Reset Sources" on page 285 for
more details on how the asynchronous comparator outputs are used to make wake-up and reset decisions.
The asynchronous comparator output can also be routed directly to a port pin through the crossbar, and is
available for use outside the device even if the system clock is stopped.
When using a comparator as an interrupt source, comparator interrupts can be generated on rising-edge
and/or falling-edge comparator output transitions. Two independent interrupt flags (CPnRIF and CPnFIF)
allow software to determine which edge caused the comparator interrupt. The comparator rising-edge and
falling-edge interrupt flags are set by hardware when a corresponding edge is detected regardless of the
interrupt enable state. Once set, these bits remain set until cleared by software.
The rising-edge and falling-edge interrupts can be individually enabled using the CPnRIE and CPnFIE
interrupt enable bits in the CPTnMD register. In order for the CPnRIF and/or CPnFIF interrupt flags to generate an interrupt request to the CPU, the comparator must be enabled as an interrupt source and global
interrupts must be enabled. See "17. Interrupt Handler" on page 238 for additional information.
CP1EN
CPT1CN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
VDD
CP1
Interrupt
CP1HYP0
CP1HYN1
CP1HYN0
CPT1MD
CP1RIE
CP1MD1
CP1MD0
Px.x
CP1
Rising-edge
CP1 +
CP1
Falling-edge
Interrupt
Logic
Px.x
CP1
+
D
SET
CLR
SET
CLR
Px.x
Crossbar
(SYNCHRONIZER)
CP1 -
GND
(ASYNCHRONOUS)
Reset
Decision
Tree
Px.x
104
Rev. 0.3
CP1A
Si102x/3x
6.3. Comparator Response Time
Comparator response time may be configured in software via the CPTnMD registers described on "SFR
Definition 6.2. CPT0MD: Comparator 0 Mode Selection" on page 107 and "SFR Definition 6.4. CPT1MD:
Comparator 1 Mode Selection" on page 109. Four response time settings are available: Mode 0 (Fastest
Response Time), Mode 1, Mode 2, and Mode 3 (Lowest Power). Selecting a longer response time reduces
the comparator active supply current. The comparators also have low power shutdown state, which is
entered any time the comparator is disabled. Comparator rising edge and falling edge response times are
typically not equal. See Table 4.16 on page 66 for complete comparator timing and supply current specifications.
VIN+
VIN-
CPn+
+
CPn
_
CPn-
OUT
CIRCUIT CONFIGURATION
VIN-
INPUTS
VIN+
V OH
OUTPUT
V OL
Negative Hysteresis
Disabled
Positive Hysteresis
Disabled
Maximum
Negative Hysteresis
Maximum
Positive Hysteresis
Rev. 0.3
105
Si102x/3x
6.5. Comparator Register Descriptions
The SFRs used to enable and configure the comparators are described in the following register descriptions. A comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used. From an
enabled state, a comparator can be disabled and placed in a low power state by clearing the CPnEN bit to
logic 0.
Important Note About Comparator Settings: False rising and falling edges can be detected by the comparator while powering on or if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short
time after the comparator is enabled or its mode bits have been changed. The comparator power up time is
specified in Table 4.16, Comparator Electrical Characteristics, on page 66.
Name
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP[1:0]
CP0HYN[1:0]
Typ
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
CP0EN
Function
CP0OUT
CP0RIF
CP0FIF
3-2
1-0
106
Rev. 0.3
Si102x/3x
Name
CP0RIE
CP0FIE
R/W
R/W
R/W
Zurücksetzen
7
6
5
Reserved
Unused
CP0RIE
CP0FIE
3:2
1:0
CP0MD[1:0]
Typ
R/W
1
Function
Unused
Read = 00b, Write = dont care.
CP0MD[1:0] Comparator0 Mode Select
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 0.3
107
Si102x/3x
SFR Definition 6.3. CPT1CN: Comparator 1 Control
Bit
Name
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP[1:0]
CP1HYN[1:0]
Typ
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
CP1EN
Function
CP1OUT
CP1RIF
CP1FIF
3:2
1:0
108
Rev. 0.3
Si102x/3x
Name
CP1RIE
CP1FIE
R/W
R/W
R/W
Zurücksetzen
R/W
1
Function
7
6
Reserved
Unused
CP1RIE
CP1FIE
3:2
1:0
CP1MD[1:0]
Typ
Unused
Read = 00b, Write = dont care.
CP1MD[1:0] Comparator1 Mode Select
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 0.3
109
Si102x/3x
7. Programmable Current Reference (IREF0)
Si102x/3x devices include an on-chip programmable current reference (source or sink) with two output current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power Mode
is 63 A (1 A steps) and the maximum current output in High Current Mode is 504 A (8 A steps).
The current source/sink is controlled though the IREF0CN special function register. It is enabled by setting
the desired output current to a non-zero value. It is disabled by writing 0x00 to IREF0CN. The port I/O pin
associated with ISRC0 should be configured as an analog input and skipped in the Crossbar. See Port
Input/Output on page 358 for more details.
Name
SINK
MODE
IREF0DAT
Typ
R/W
R/W
R/W
Zurücksetzen
SINK
Function
MDSEL
5:0
IREF0DAT[5:0]
110
Rev. 0.3
Si102x/3x
Name
PWMEN
Typ
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
PWMEN
PWMSS[2:0]
R/W
0
Function
6:3
Unused
2:0
PWMSS[2:0]
Rev. 0.3
111
Si102x/3x
7.3. Comparator0 and Comparator1 Analog Multiplexers
Comparator0 and Comparator1 on Si102x/3x devices have analog input multiplexers to connect port I/O
pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input multiplexers for Comparator0 and CP1+/CP1- are the positive and negative input multiplexers for Comparator1.
The comparator input multiplexers directly support capacitive sensors. When the Compare input is
selected on the positive or negative multiplexer, any Port I/O pin connected to the other multiplexer can be
directly connected to a capacitive sensor with no additional external components. The Compare signal provides the appropriate reference level for detecting when the capacitive sensor has charged or discharged
through the on-chip Rsense resistor. The Comparator0 output can be routed to Timer2 for capturing the
capacitors charge and discharge time. See Section 33. Timers on page 491 for details.
Any of the following may be selected as comparator inputs: port I/O pins, capacitive touch sense compare,
VDD/DC+ supply voltage, regulated digital supply voltage (output of VREG0), the VBAT supply voltage or
ground. The comparators supply voltage divided by 2 is also available as an input; the resistors used to
divide the voltage only draw current when this setting is selected. The comparator input multiplexers are
configured using the CPT0MX and CPT1MX registers described in SFR Definition 7.3 and SFR Definition
7.4.
P0.1
P0.3
P0.5
P1.5
P1.7
P2.1
P2.3
P0.0
P0.2
P0.4
P0.6
P1.4
P1.6
P2.0
P2.2
CPnOUT
Rsense
CPnOUT
Rsense
Only enabled
when Compare is
selected on CPnInput MUX.
VBAT
R
R
CPnOUT
R
Compare
(1/3 or 2/3) x VBAT
VBAT
R
R
CPnInput
MUX
VBAT
CPnOUT
Compare
(1/3 or 2/3) x VBAT
CPn+
Input
MUX
VBAT
GND
R
R
VBAT
VBAT
x VBAT
CMXnP0
CMXnP3
CMXnP2
CMXnP1
CMXnN2
CMXnN1
CMXnN0
CMXnN3
CPTnMX
x VBAT
Digital Supply
VDC
GND
112
Rev. 0.3
Si102x/3x
CMX0N[3:0]
Name
CMX0P[3:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
3:0
CMX0N
CMX0P
Function
P0.1
1000:
P2.1
0001:
P0.3
1001:
P2.3
0010:
P0.5
1010:
Reserved
0011:
Reserved
1011:
Reserved
0100:
Reserved
1100:
Compare
0101:
Reserved
1101:
VBAT divided by 2
0110:
P1.5
1110:
0111:
P1.7
1111:
Ground
P0.0
1000:
P2.0
0001:
P0.2
1001:
P2.2
0010:
P0.4
1010:
Reserved
0011:
P0.6
1011:
Reserved
0100:
Reserved
1100:
Compare
0101:
Reserved
1101:
VBAT divided by 2
0110:
P1.4
1110:
0111:
P1.6
1111:
Rev. 0.3
113
Si102x/3x
SFR Definition 7.4. CPT1MX: Comparator1 Input Channel Select
Bit
CMX1N[3:0]
Name
CMX1P[3:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
3:0
114
CMX1N
CMX1P
Function
P0.1
1000:
P2.1
0001:
P0.3
1001:
P2.3
0010:
P0.5
1010:
Reserved
0011:
Reserved
1011:
Reserved
0100:
Reserved
1100:
Compare
0101:
Reserved
1101:
VBAT divided by 2
0110:
P1.5
1110:
0111:
P1.7
1111:
Ground
P0.0
1000:
P2.0
0001:
P0.2
1001:
P2.2
0010:
P0.4
1010:
Reserved
0011:
P0.6
1011:
Reserved
0100:
Reserved
1100:
Compare
0101:
Reserved
1101:
VBAT divided by 2
0110:
P1.4
1110:
0111:
P1.6
1111:
Rev. 0.3
Si102x/3x
8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51 instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 35), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput with 25 MHz
Clock
- 0 to 25 MHz Clock Frequency
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
D8
D8
ACCUMULATOR
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
PSW
D8
D8
D8
ALU
SRAM
D8
DATA BUS
B REGISTER
D8
D8
D8
DATA BUS
DATA BUS
SFR_ADDRESS
BUFFER
D8
DATA POINTER
D8
D8
SFR
BUS
INTERFACE
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
DATA BUS
PC INCREMENTER
MEM_ADDRESS
D8
MEM_CONTROL
A16
MEMORY
INTERFACE
MEM_WRITE_DATA
MEM_READ_DATA
PIPELINE
RESET
D8
CONTROL
LOGIC
SYSTEM_IRQs
CLOCK
D8
STOP
IDLE
POWER CONTROL
REGISTER
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
Rev. 0.3
115
Si102x/3x
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execution time.
Clocks to Execute
2/3
3/4
4/5
Number of Instructions
26
50
14
116
Rev. 0.3
Si102x/3x
Table 8.1. CIP-51 Instruction Set Summary
Mnemonic
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
Description
Arithmetic Operations
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
Logical Operations
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Rev. 0.3
Bytes
Clock
Cycles
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
117
Si102x/3x
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
118
Description
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
Swap nibbles of A
Data Transfer
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
Boolean Manipulation
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
Rev. 0.3
Bytes
Clock
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
1
2
1
2
1
2
2
1
2
1
2
1
2
2
Si102x/3x
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
Description
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Program Branching
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
Compare immediate to indirect and jump if not
equal
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
Rev. 0.3
Bytes
Clock
Cycles
2
2
2
2
2
2
2
3
3
3
2
2
2
2
2
2/3
2/3
3/4
3/4
3/4
2
3
1
1
2
3
2
1
2
2
3
3
3
4
5
5
3
4
3
3
2/3
2/3
3/4
3/4
3/4
4/5
2
3
1
2/3
3/4
1
119
Si102x/3x
120
Rev. 0.3
Si102x/3x
8.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the data sheet associated with their corresponding system function.
Name
DPL[7:0]
Typ
R/W
Zurücksetzen
DPL[7:0]
Function
Name
DPH[7:0]
Typ
R/W
Zurücksetzen
DPH[7:0]
Function
Rev. 0.3
121
Si102x/3x
SFR Definition 8.3. SP: Stack Pointer
Bit
Name
SP[7:0]
Typ
R/W
Zurücksetzen
SP[7:0]
Function
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
Name
ACC[7:0]
Typ
R/W
Zurücksetzen
ACC[7:0]
Accumulator.
This register is the accumulator for arithmetic operations.
Name
B[7:0]
Typ
R/W
Zurücksetzen
B[7:0]
B Register.
This register serves as a second accumulator for certain arithmetic operations.
122
Rev. 0.3
Si102x/3x
Name
CY
AC
F0
Typ
R/W
R/W
R/W
Zurücksetzen
RS[1:0]
OV
F1
PARITY
R/W
R/W
R/W
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations.
AC
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3
RS[1:0]
OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
Rev. 0.3
123
Si102x/3x
9. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
Si102x/3x device family is shown in Figure 9.1
PROGRAM/DATA MEMORY
(FLASH)
DATA MEMORY
(RAM)
INTERNAL DATA ADDRESS SPACE
S1020/24/30/34
0x1FFFF
0x00000
128 kB FLASH
Special Function
Registers
(Indirect Addressing Only) (Direct Addressing Only)
(In-System
Programmable in 1024
Byte Sectors)
Si1021/25/31/35
64 kB FLASH
Bit Addressable
General Purpose
Registers
0x00000
(In-System
Programmable in 1024
Byte Sectors)
0x00000
(In-System
Programmable in 1024
Byte Sectors)
Si1022/26/32/36
32 kB FLASH
0x0FFFF
0x07FFF
0xFFFF
0xFFFF
Off-chip XRAM space
(only on 76-pin package)
Si1023/27/33/37
0x03FFF
0x00000
16 kB FLASH
0x2000
0x1000
0x1FFF
0x0FFF
(In-System
Programmable in 1024
Byte Sectors)
0x0000
0x0000
124
Rev. 0.3
Si102x/3x
on the selection of bits in the PSBANK register, as described in SFR Definition 9.1. All other devices with
64 kB or less of program memory can be used as non-banked devices.
The IFBANK bits select which of the upper banks are used for code execution, while the COBANK bits
select the bank to be used for direct writes and reads of the flash memory.
The address 0x1FFFF (Si1020/24/30/34 ), 0xFFFF (Si1021/25/31/35), 0x07FFF (Si1022/26/32/36), or
0x3FFF (Si1023/27/33/37) serves as the security lock byte for the device. Any addresses above the lock
byte are reserved.
Lock Byte
0x1FFFF
Lock Byte
Page
0x1FFFE
0x1FC00
0x1FBFF
Flash
Memory
Space
Si1021/25/31/35
Lock Byte
0x0FFFF
Lock Byte
Page
0x0FFFE
0x0FC00
0x0FBFF
Flash
Memory
Space
0x0000
Si1022/26/32/36
Lock Byte
0x07FFF
Lock Byte
Page
0x7FFE
0x07C00
0x07BFF
Flash
Memory
Space
0x0000
0x00000
Si1023/27/33/37
Lock Byte
0x03FFF
Lock Byte
Page
0x3FFE
Flash
Memory
Space
Si1020/24/30/34
0x03C00
0x03BFF
0x00000
Rev. 0.3
125
Si102x/3x
Internal
Address
0 xFFFF
IFBANK = 0
IFBANK = 1
IFBANK = 2
IFBANK = 3
Bank0
Bank1
Bank2
Bank3
Bank0
Bank0
Bank0
Bank0
0x 8000
0x7FFF
0x 0000
Figure 9.3. Address Memory Map for Instruction Fetches
126
Rev. 0.3
Si102x/3x
COBANK[1:0]
Name
IFBANK[1:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Reserved
Function
Reserved
Note:
1. COBANK[1:0] and IFBANK[1:0] should not be set to select any bank other than Bank 0 (00b) on the
Si1022/23/26/27/32/33/36/37 devices.
2. COBANK[1:0] and IFBANK[1:0] should not be set to select Bank 2 (10b) or Bank 3 (11b) on the
Si1021/25/31/35 devices.
Rev. 0.3
127
Si102x/3x
of the 8051. 8192 or 4096 bytes of this memory is on-chip external memory. The data memory map is
shown in Figure 9.1 for reference.
9.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 9.1 illustrates the data memory organization of the Si102x/3x.
9.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
9.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51 assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
9.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
9.2.2. External RAM
There are 8192 bytes or 4096 bytes of on-chip RAM mapped into the external data memory space. All of
these address locations may be accessed using the external move instruction (MOVX) and the data
pointer (DPTR), or using MOVX indirect addressing mode (such as @R1) in combination with the EMI0CN
register. Additional off-chip memory or memory-mapped devices may be mapped to the external memory
128
Rev. 0.3
Si102x/3x
address space and accessed using the external memory interface. See Section 10. External Data Memory Interface and On-Chip XRAM on page 130 for further details.
Rev. 0.3
129
Si102x/3x
10. External Data Memory Interface and On-Chip XRAM
An External Memory Interface (EMIF) is available on the Si102x/3x devices, which can be used to access
off-chip data memories and memory-mapped devices connected to the GPIO ports. The external memory
space may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using
the MOVX indirect addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address
operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN, shown in SFR Definition 10.1).
Note: The MOVX instruction can also be used for writing to the flash memory. See Section 18. Flash Memory on
page 250 for details. The MOVX instruction accesses XRAM by default.
DPTR, #1234h
A, @DPTR
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
10.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV
MOV
MOVX
130
EMI0CN, #12h
R0, #34h
a, @R0
Rev. 0.3
Si102x/3x
10.2. Configuring the External Memory Interface
Configuring the EMIF consists of five steps:
1. Configure the output modes of the associated port pins as either push-pull or open-drain (push-pull is
most common). The input mode of the associated port pins should be set to digital (reset value).
2. Configure port latches to park the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select Multiplexed mode or Non-Multiplexed mode.
4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select,
or off-chip only).
5. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The port selection, Multiplexed
mode selection, and mode bits are located in the EMI0CF register shown in SFR Definition .
Rev. 0.3
131
Si102x/3x
Table 10.1. EMIF Pinout
Multiplexed Mode
Signal Name
Port Pin
Signal Name
8-Bit Mode1
16-Bit Mode2
RD
P3.6
P3.6
WR
P3.7
ALE
8-Bit Mode 1
16-Bit Mode2
RD
P3.6
P3.6
P3.7
WR
P3.7
P3.7
P3.5
P3.5
D0
P6.0
P6.0
AD0
P6.0
P6.0
D1
P6.1
P6.1
AD1
P6.1
P6.1
D2
P6.2
P6.2
AD2
P6.2
P6.2
D3
P6.3
P6.3
AD3
P6.3
P6.3
D4
P6.4
P6.4
AD4
P6.4
P6.4
D5
P6.5
P6.5
AD5
P6.5
P6.5
D6
P6.6
P6.6
AD6
P6.6
P6.6
D7
P6.7
P6.7
AD7
P6.7
P6.7
A0
P5.0
P5.0
A8
P5.0
A1
P5.1
P5.1
A9
P5.1
A2
P5.2
P5.2
A10
P5.2
A3
P5.3
P5.3
A11
P5.3
A4
P5.4
P5.4
A12
P5.4
A5
P5.5
P5.5
A13
P5.5
A6
P5.6
P5.6
A14
P5.6
A7
P5.7
P5.7
A15
P5.7
A8
P4.0
A9
P4.1
A10
P4.2
A11
P4.3
A12
P4.4
A13
P4.5
A14
P4.6
A15
P4.7
Required I/O:
11
19
Required I/O:
18
26
Notes:
1. Using 8-bit movx instruction without bank select.
2. Using 16-bit movx instruction.
132
Port Pin
Rev. 0.3
Si102x/3x
Name
PGSEL[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
133
Si102x/3x
SFR Definition 10.2. EMI0CF: External Memory Configuration
Bit
Name
4
EMD2
Type
Reset
EMD[1:0]
0
EALE[1:0]
R/W
0
Function
7:5
Unused
EMD2
3:2
EMD[1:0]
1:0
EALE[1:0]
134
Rev. 0.3
Si102x/3x
10.4. Multiplexed and Non-Multiplexed Selection
The External Memory Interface is capable of acting in a Multiplexed mode or Non-Multiplexed mode,
depending on the state of the EMD2 (EMI0CF.4) bit.
10.4.1. Multiplexed Configuration
In Multiplexed mode, the data bus and the lower 8 bits of the address bus share the same port pins:
AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8 bits
of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is
driven by the EMIF logic. An example of a Multiplexed configuration is shown in Figure 10.1.
In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state
of the ALE signal. During the first phase, ALE is high and the lower 8 bits of the address bus are presented
to AD[7:0]. During this phase, the address latch is configured such that the Q outputs reflect the states of
the D inputs. When ALE falls, signaling the beginning of the second phase, the address latch outputs
remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the data bus controls the state of the AD[7:0] port at the time RD or WR is asserted.
See Section 10.6.2. Multiplexed Mode on page 143 for more information.
A[15:8]
ADDRESS BUS
A[15:8]
74HC373
E
M
I
F
ALE
AD[7:0]
G
ADDRESS/DATA BUS
A[7:0]
VDD
64 K X 8
SRAM
(Optional)
8
I/O[7:0]
CE
WE
OE
WR
RD
Figure 10.1. Multiplexed Configuration Example
10.4.2. Non-Multiplexed Configuration
In Non-Multiplexed mode, the data bus and the address bus pins are not shared. An example of a nonmultiplexed configuration is shown in Figure 10.2. See Section 10.6.1. Non-Multiplexed Mode on
page 140 for more information about non-multiplexed operation.
Rev. 0.3
135
Si102x/3x
E
M
I
F
A[15:0]
A[15:0]
ADDRESS BUS
VDD
(Optional)
64 K X 8
SRAM
I/O[7:0]
8
D[7:0]
DATA BUS
CE
WE
OE
WR
RD
EMI0CF[3:2] = 10
EMI0CF[3:2] = 01
EMI0CF[3:2] = 00
0xFFFF
0xFFFF
EMI0CF[3:2] = 11
0xFFFF
0xFFFF
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
Off-Chip
Memory
(Bank Select)
On-Chip XRAM
Off-Chip
Memory
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
0x0000
0x0000
0x0000
136
Rev. 0.3
0x0000
Si102x/3x
10.5.1. Internal XRAM Only
When bits EMI0CF[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the
device. Memory accesses to addresses beyond the populated space will wrap on 8 kB boundaries. As an
example, the addresses 0x2000 and 0x4000 both evaluate to address 0x0000 in on-chip XRAM space.
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
10.5.2. Split Mode without Bank Select
When bit EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and offchip space.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is onchip or off-chip. However, in the No Bank Select mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with Split Mode with Bank Select described below. The lower 8-bits of the Address Bus A[7:0]
are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven
during the off-chip transaction.
10.5.3. Split Mode with Bank Select
When EMI0CF[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and offchip space.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is onchip or off-chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower
8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are
driven in Bank Select mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven
(identical behavior to an off-chip access in Split Mode without Bank Select described above). This
allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full
16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
Rev. 0.3
137
Si102x/3x
10.6. Timing
The timing parameters of the EMIF can be configured to enable connection to devices having different
setup and hold time requirements. The address setup time, address hold time, RD and WR strobe widths,
and in Multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods
through EMI0TC, shown in SFR Definition 10.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing
parameters defined by the EMI0TC register. Assuming Non-Multiplexed operation, the minimum execution
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in Multiplexed mode is
7 SYSCLK cycles (2 for /ALE + 1 for RD or WR + 4). The programmable setup and hold times default to
the maximum delay settings after a reset. Table 10.2 lists the ac parameters for the EMIF, and Figure 10.4
through Figure 10.9 show the timing diagrams for the different EMIF modes and MOVX operations.
138
Rev. 0.3
Si102x/3x
Name
EAS[1:0]
EWR[3:0]
EAH[1:0]
Typ
R/W
R/W
R/W
Zurücksetzen
Name
Function
7:6
EAS[1:0]
5:2
EWR[3:0]
1:0
EAH[1:0]
Rev. 0.3
139
Si102x/3x
10.6.1. Non-Multiplexed Mode
10.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111
Nonmuxed 16-bit WRITE
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
WDS
ACS
WDH
ACW
ACH
WR
RD
P2
ADDR[7:0]
DATA[7:0]
RDS
ACS
ACW
RDH
ACH
RD
WR
140
Rev. 0.3
Si102x/3x
10.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111
Nonmuxed 8-bit WRITE without Bank Select
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
WDS
ACS
WDH
ACW
ACH
WR
RD
ADDR[7:0]
DATA[7:0]
RDS
ACS
ACW
RDH
ACH
RD
WR
Rev. 0.3
141
Si102x/3x
10.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110
Nonmuxed 8-bit WRITE with Bank Select
ADDR[15:8]
ADDR[7:0]
DATA[7:0]
WDS
ACS
WDH
ACW
ACH
WR
RD
ADDR[7:0]
DATA[7:0]
RDS
ACS
ACW
RDH
ACH
RD
WR
142
Rev. 0.3
Si102x/3x
10.6.2. Multiplexed Mode
10.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011
Muxed 16-bit WRITE
ADDR[15:8]
AD[7:0]
ALEH
ALEL
ALE
T
WDS
ACS
WDH
ACW
ACH
WR
RD
AD[7:0]
ALEH
ALEL
RDS
RDH
ALE
ACS
ACW
ACH
RD
WR
Rev. 0.3
143
Si102x/3x
10.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011
Muxed 8-bit WRITE Without Bank Select
ADDR[15:8]
AD[7:0]
ALEH
ALEL
ALE
T
WDS
ACS
WDH
ACW
ACH
WR
RD
AD[7:0]
ALEH
ALEL
RDS
RDH
ALE
ACS
ACW
ACH
RD
WR
144
Rev. 0.3
Si102x/3x
10.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010
Muxed 8-bit WRITE with Bank Select
ADDR[15:8]
AD[7:0]
ALEH
ALEL
ALE
T
WDS
ACS
WDH
ACW
ACH
WR
RD
AD[7:0]
ALEH
ALEL
RDS
RDH
ALE
ACS
ACW
ACH
RD
WR
Rev. 0.3
145
Si102x/3x
Table 10.2. AC Parameters for External Memory Interface
Parameter
Description
Min*
Max*
Units
TACS
3 x TSYSCLK
ns
TACW
1 x TSYSCLK
16 x TSYSCLK
ns
TACH
3 x TSYSCLK
ns
TALEH
1 x TSYSCLK
4 x TSYSCLK
ns
TALEL
1 x TSYSCLK
4 x TSYSCLK
ns
TWDS
1 x TSYSCLK
19 x TSYSCLK
ns
TWDH
3 x TSYSCLK
ns
TRDS
20
ns
TRDH
ns
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
146
Rev. 0.3
Si102x/3x
11. Direct Memory Access (DMA0)
An on-chip direct memory access (DMA0) is included on the Si102x/3x devices. The DMA0 subsystem
allows autonomous variable-length data transfers between XRAM and peripheral SFR registers without
CPU intervention. During DMA0 operation, the CPU is free to perform some other tasks. In order to save
total system power consumption, the CPU and flash can be powered down. DMA0 improves the system
performance and efficiency with high data throughput peripherals.
DMA0 contains seven independent channels, common control registers, and a DMA0 Engine (see
Figure 11.1). Each channel includes a register that assigns a peripheral to the channel, a channel control
register, and a set of SFRs that include XRAM address information and SFR address information used by
the channel during a data transfer. The DMA0 architecture is described in detail in Section 11.1.
The DMA0 in Si102x/3x devices supports four peripherals: AES0, ENC0, CRC1, and SPI1. Peripherals
with DMA0 capability should be configured to work with the DMA0 through their own registers. The DMA0
provides up to seven channels, and each channel can be configured for one of nine possible data transfer
functions:
XRAM to ENC0L/M/H
ENC0L/M/H sfrs to XRAM
XRAM to CRC1IN sfr
XRAM to SPI1DAT sfr
SPI1DAT sfr to XRAM
XRAM to AES0KIN sfr
XRAM to AES0BIN sfr
XRAM to AES0XIN sfr
AES0YOUT sfr to XRAM
The DMA0 subsystem signals the MCU through a set of interrupt service routine flags. Interrupts can be
generated when the DMA0 transfers half of the data length or full data length on any channel.
Rev. 0.3
147
Si102x/3x
...
Channel 6
Channel 1
Channel 0
Peripheral assignment DMA0nCF[2:0]
Channel memory
interface config
Channel
Control
DMA0nBAH
DMA0nBAL
DMA0nAOH
DMA0nAOL
DMA0nSZH
DMA0nSZL
DMA0nCF
PERIPH0
PERIPH1
ENDIAN
PERIPH2
PERIPH3
INTEN
STALL
MINTEN
DMA
ENGINE
DMA0nMD
CH0_EN
CH1_EN
CH2_EN
CH3_EN
CH4_EN
CH5_EN
CH6_EN
DMA0EN
CH0_INT
CH1_INT
CH2_INT
CH3_INT
CH4_INT
CH5_INT
DMA0INT
CH0_MINT
CH1_MINT
CH2_MINT
CH3_MINT
CH4_MINT
CH5_MINT
CH6_MINT
DMA0MINT
CH0_BUSY
CH1_BUSY
CH2_BUSY
CH3_BUSY
CH4_BUSY
CH5_BUSY
DMA0BUSY
CH6_BUSY
DMA0SEL[1]
DMA0SEL[2]
DMA0SEL
DMA0SEL[0]
Common
Control/
Status
WRAP
CH6_INT
Internal
DMA
bus
control
148
Rev. 0.3
Si102x/3x
Data transfer size DMA0NSZH:L defines the maximum number of bytes for the DMA0 transfer of the
selected channel. If the address offset reaches data transfer size, the full-length interrupt flag bit CHn_INT
(DMA0INT) of the selected channel will be asserted. Similarly, the mid-point interrupt flag bit CHn_MINT is
set when the address offset is equal to half of data transfer size if the transfer size is an even number or
when the address offset is equal to half of the transfer size plus one if the transfer size is an odd number.
Interrupt flags must be cleared by software so that the next DMA0 data transfer can proceed.
The DMA0 subsystem permits data transfer between SFR registers and XRAM. The DMA0 subsystem
executes its task based on settings of a channels control and memory interface configuration SFRs. When
data is copied from XRAM to SFR registers, it takes two cycles for DMA0 to read from XRAM and the SFR
write occurs in the second cycle. If more than one byte is involved, a pipeline is used. When data is copied
from SFR registers to XRAM, the DMA0 only requires one cycle for one byte transaction.
The selected DMA0 channel for a peripheral should be enabled through the enable bits CHn_EN
(DMA0EN.n) to allow the DMA0 to transfer the data. When the DMA0 is transferring data on a channel, the
busy status bit of the channel CHn_BUSY (DMA0BUSY.n) is set. During the transaction, writes to
DMA0NSZH:L, DMA0NBAH:L, and DMA0NAOH:L are disabled.
Each peripheral is responsible for asserting the peripheral transfer requests necessary to service the particular peripheral. Some peripherals may have a complex state machine to manage the peripheral
requests. Please refer to the DMA enabled peripheral chapters for additional information (AES0, CRC1,
ENC0 and SPI1).
Besides reporting transaction status of a channel, DMA0BUSY can be used to force a DMA0 transfer on
an already configured channel by setting the CHn_BUSY bit (DMA0BUSY.n).
The DMA0NMD SFR has a wrap bit that supports address offset wrapping. The size register DMA0NSZ
sets the transfer size. Normally the address offset starts at zero and increases until it reaches size minus
one. At this point the transfer is complete and the interrupt bit will be set. When the wrap bit is set, the
address offset will automatically be reset to zero and transfers will continue as long as the peripheral keeps
requesting data.
The wrap feature can be used to support key wrapping for the AES0 module. Normally the same key is
used over and over with additional data blocks. So the wrap bit should be set when using the XRAM to
AES0KIN request. This feature supports multiple-block encryption operations.
Rev. 0.3
149
Si102x/3x
11.4. Transfer Configuration
The following steps are required to configure one of the DMA0 channels for operation:
1. Select the channel to be configured by writing DMA0SEL.
2. Specify the data transfer function by writing DMA0NCF. This register also specifies the endian-ness
of the data in XRAM and enables full or mid-point interrupts.
3. Configure the wrapping mode by writing to DMA0NMD. Setting this bit will automatically reset the
address offset after each completed transfer.
4. Specify the base address in XRAM for the transfer by writing DMA0NBAH:L.
5. Specify the size of the transfer in bytes by writing DMA0NSZH:L.
6. Reset the address offset counter by writing 0 to DMA0NAOH:L.
7. Enable the DMA0 channel by writing 1 to the appropriate bit in DMA0EN.
150
Rev. 0.3
Si102x/3x
Name
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Function
Unused
CH6_EN
Channel 6 Enable.
0: Disable DMA0 channel 6.
1: Enable DMA0 channel 6.
CH5_EN
Channel 5 Enable.
0: Disable DMA0 channel 5.
1: Enable DMA0 channel 5.
CH4_EN
Channel 4 Enable.
0: Disable DMA0 channel 4.
1: Enable DMA0 channel 4.
CH3_EN
Channel 3 Enable.
0: Disable DMA0 channel 3.
1: Enable DMA0 channel 3.
CH2_EN
Channel 2 Enable.
0: Disable DMA0 channel 2.
1: Enable DMA0 channel 2.
CH1_EN
Channel 1 Enable.
0: Disable DMA0 channel 1.
1: Enable DMA0 channel 1.
CH0_EN
Channel 0 Enable.
0: Disable DMA0 channel 0.
1: Enable DMA0 channel 0.
Rev. 0.3
151
Si102x/3x
SFR Definition 11.2. DMA0INT: DMA0 Full-Length Interrupt
Bit
Name
CH6_INT
CH5_INT
CH4_INT
CH3_INT
CH2_INT
CH1_INT
CH0_INT
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Unused
CH6_INT
Function
Read = 0b, Write = Dont Care
Channel 6 Full-Length Interrupt Flag.1
0: Full-length interrupt has not occured on channel 6.
1: Full-length interrupt has not occured on channel 6.
CH5_INT
CH4_INT
CH3_INT
CH2_INT
CH1_INT
CH0_INT
Note: 1.Full-length interrupt flag is set when the offset address DMA0NAOH/L is equal to the data transfer size
DMA0NSZH/L minus 1. This flag must be cleared by software or system reset. The full-length interrupt is
enabled by setting bit 7 of DMA0NCF with DMA0SEL configured for the corresponding channel.
152
Rev. 0.3
Si102x/3x
Name
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Unused
CH6_MINT
Function
Read = 0b, Write = Dont Care
Channel 6 Mid-Point Interrupt Flag.
0: Mid-Point interrupt has not occured on channel 6.
1: Mid-Point interrupt has not occured on channel 6.
CH5_MINT
CH4_MINT
CH3_MINT
CH2_MINT
CH1_MINT
CH0_MINT
Note: Mid-point Interrupt flag is set when the offset address DMA0NAOH/L is equal to half of the data transfer size
DMA0NSZH/L if the transfer size is an even number or half of data transfer size DMA0NSZH/L plus one if the
transfer size is an odd number. This flag must be cleared by software or system reset.The mid-point interrupt
is enabled by setting bit 6 of DMA0NCF with DMA0SEL configured for the corresponding channel.
Rev. 0.3
153
Si102x/3x
SFR Definition 11.4. DMA0BUSY: DMA0 Busy
Bit
Name
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Unused
Description
Write
No effect.
Read
Always Reads 0.
0: No effect.
0: DMA0 channel 6 Idle.
1: Force DMA0 transfer to 1: DMA0 transfer in progstart on channel 6.
ress on channel 6.
0: No effect.
0: DMA0 channel 5 Idle.
1: Force DMA0 transfer to 1: DMA0 transfer in progstart on channel 5.
ress on channel 5.
0: No effect.
0: DMA0 channel 4 Idle.
1: Force DMA0 transfer to 1: DMA0 transfer in progstart on channel 4.
ress on channel 4.
0: No effect.
0: DMA0 channel 3 Idle.
1: Force DMA0 transfer to 1: DMA0 transfer in progstart on channel 3.
ress on channel 3.
0: No effect.
0: DMA0 channel 2 Idle.
1: Force DMA0 transfer to 1: DMA0 transfer in progstart on channel 2.
ress on channel 2.
0: No effect.
0: DMA0 channel 1 Idle.
1: Force DMA0 transfer to 1: DMA0 transfer in progstart on channel 1.
ress on channel 1.
0: No effect.
0: DMA0 channel 0 Idle.
1: Force DMA0 transfer to 1: DMA0 transfer in progstart on channel 0.
ress on channel 0.
154
Rev. 0.3
Si102x/3x
SFR Definition 11.5. DMA0SEL: DMA0 Channel Select for Configuration
Bit
Name
DMA0SEL[2:0]
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
R/W
0
Name
7:3
Unused
2:0
DMA0SEL[2:0]
Function
Read = 0b, Write = Dont Care
Channel Select for Configuration.
These bits select the channel for configuration of the DMA0 transfer. The
first step to configure a channel for DMA0 transfer is to select the desired
channel, and then write to channel specific registers DMA0NCF,
DMA0NBAL/H, DMA0NAOL/H, DMA0NSZL/H.
000: Select channel 0
001: Select channel 1
010: Select channel 2
011: Select channel 3
100: Select channel 4
101: Select channel 5
110: Select channel 6
111: Invalid
Rev. 0.3
155
Si102x/3x
Name
0
WRAP
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
7:1
reserved
WRAP
Function
Read = 0, Write = 0
Wrap Enable.
Setting this bit will enable wrapping.
The DMA0NSZ register sets the transfer size. Normally the DMA0AO value
starts at zero in increases to the DMANSZ minus one. At this point the transfer is complete and the interrupt bit will be set. If the WRAP bit is set, the
DMA0NAO will be reset to zero.
Note: This is a DMA channel indirect register. Select the desired channel first writing the DMA0SEL register.
156
Rev. 0.3
Si102x/3x
SFR Definition 11.7. DMA0NCF: DMA Channel Configuration
Bit
Name
INTEN
MINTEN
STALL
ENDIAN
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
PERIPH[3:0]
R/W
0
Name
INTEN
Function
Full-Length Interrupt Enable.
0: Disable the full-length interrupt of the selected channel.
1: Enable the full-length interrupt of the selected channel.
MINTEN
STALL
DMA0 Stall.
Setting this bit stalls the DMA0 transfer on the selected channel. After a
Stall, this bit must be cleared by software to resume normal operation.
0: The DMA0 transfer of the selected channel is not being stalled.
1: The DMA0 transfer of the selected channel is stalled.
ENDIAN
3:0
PERIPH[2:0]
Note: This is a DMA channel indirect register. Select the desired channel first writing the DMA0SEL register.
Rev. 0.3
157
Si102x/3x
SFR Definition 11.8. DMA0NBAH: Memory Base Address High Byte
Bit
Name
NBAH[3:0]
Typ
Zurücksetzen
R/W
0
Name
7:4
Unused
3:0
NBAH[3:0]
Function
Read = 0b, Write = Dont Care
Memory Base Address High Byte.
Sets high byte of the memory base address which is the DMA0 XRAM starting address of the selected channel if the channels address offset
DMA0NAO is reset to 0.
Note: This is a DMA channel indirect register. Select the desired channel first writing the DMA0SEL register.
Name
NBAH[7:0]
Typ
R/W
Zurücksetzen
Name
7:0
NBAL[7:0]
Function
Memory Base Address Low Byte.
Sets low byte of the memory base address which is the DMA0 XRAM starting address of the selected channel if the channels address offset
DMA0NAO is reset to 0.
Note: This is a DMA channel indirect register. Select the desired channel first writing the DMA0SEL register.
158
Rev. 0.3
Si102x/3x
SFR Definition 11.10. DMA0NAOH: Memory Address Offset High Byte
Bit
Name
NAOH[1:0]
Typ
Zurücksetzen
R/W
0
Name
7:2
Unused
1:0
NAOH[1:0]
Function
Read = 0b, Write = Dont Care
Memory Address Offset High Byte.
Sets the high byte of the address offset of the selected channel which acts a
counter during DMA0 transfer. The address offset auto-increments by one
after one byte is transferred. When configuring a channel for DMA0 transfer,
the address offset should be reset to 0.
Note: This is a DMA channel indirect register. Select the desired channel first writing the DMA0SEL register.
Name
NACL[7:0]
Typ
R/W
Zurücksetzen
Name
7:0
NACL[7:0]
Function
Memory Address Offset Low Byte.
Sets the low byte of the address offset of the selected channel which acts a
counter during DMA0 transfer. The address offset auto-increments by one
after one byte is transferred. When configuring a channel for DMA0 transfer,
the address offset should be reset to 0.
Note: This is a DMA channel indirect register. Select the desired channel first writing the DMA0SEL register.
Rev. 0.3
159
Si102x/3x
SFR Definition 11.12. DMA0NSZH: Transfer Size High Byte
Bit
Name
NSZH[1:0]
Typ
Zurücksetzen
R/W
0
Name
7:2
Unused
1:0
NSZH[1:0]
Function
Read = 0b, Write = Dont Care
Transfer Size High Byte.
Sets high byte of DMA0 transfer size of the selected channel. Transfer size
sets the maximum number of bytes for the DMA0 transfer. When the
address offset is equal to the transfer size, a full-length interrupt is generated on the channel.
Note: This is a DMA channel indirect register. Select the desired channel first writing the DMA0SEL register.
Name
NSZL[7:0]
Typ
R/W
Zurücksetzen
Name
7:0
NSZL[7:0]
Function
Memory Transfer Size Low Byte.
Sets low byte of DMA0 transfer size of the selected channel. Transfer size
sets the maximum number of bytes for the DMA0 transfer. When the
address offset is equal to the transfer size, a full-length interrupt is generated on the channel.
Note: This is a DMA channel indirect register. Select the desired channel first writing the DMA0SEL register.
160
Rev. 0.3
Si102x/3x
12. Cyclic Redundancy Check Unit (CRC0)
Si102x/3x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or
32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the 16bit or 32-bit result to an internal register. The internal result register may be accessed indirectly using the
CRC0PNT bits and CRC0DAT register, as shown in Figure 12.1. CRC0 also has a bit reverse register for
quick data manipulation.
CRC0CN
CRC0IN
Automatic CRC
Controller
Flash
Memory
CRC0AUTO
CRC0SEL
CRC0INIT
CRC0VAL
CRC0PNT1
CRC0PNT0
CRC Engine
CRC0CNT
32
RESULT
CRC0FLIP
Write
4 to 1 MUX
8
CRC0DAT
CRC0FLIP
Read
The following
1. XOR the most-significant byte of the current CRC result with the input byte. If this is the first iteration
of the CRC unit, the current CRC result will be the set initial value (0x0000 or 0xFFFF).
a. If the MSB of the CRC result is set, left-shift the CRC result, and then XOR the CRC result with
the polynomial (0x1021).
b. If the MSB of the CRC result is not set, left-shift the CRC result.
2. Repeat at Step 2a for the number of input bits (8).
Rev. 0.3
161
Si102x/3x
The 16-bit Si102x/3x CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)
{
unsigned char i;
// loop counter
#define POLY 0x1021
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input << 8);
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x8000) == 0x8000)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc << 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc << 1;
}
}
// Return the final remainder (CRC value)
return CRC_acc;
}
The following table lists several input values and the associated outputs using the 16-bit CRC algorithm:
162
Input
Output
0x63
0x8C
0x7D
0xAA, 0xBB, 0xCC
0x00, 0x00, 0xAA, 0xBB, 0xCC
0xBD35
0xB1F4
0x4ECA
0x6CF6
0xB166
Rev. 0.3
Si102x/3x
12.2. 32-bit CRC Algorithm
The CRC0 unit calculates the 32-bit CRC using a polynomial of 0x04C11DB7. The CRC-32 algorithm is
reflected, meaning that all of the input bytes and the final 32-bit output are bit-reversed in the processing
engine. The following is a description of a simplified CRC algorithm that produces results identical to the
hardware:
Step 1. XOR the least-significant byte of the current CRC result with the input byte. If this is the
first iteration of the CRC unit, the current CRC result will be the set initial value
(0x00000000 or 0xFFFFFFFF).
Step 2. Right-shift the CRC result.
Step 3. If the LSB of the CRC result is set, XOR the CRC result with the reflected polynomial
(0xEDB88320).
Step 4. Repeat at Step 2 for the number of input bits (8).
For example, the 32-bit CRC algorithm can be described by the following code:
unsigned long UpdateCRC (unsigned long CRC_acc, unsigned char CRC_input)
{
unsigned char i; // loop counter
#define POLY 0xEDB88320 // bit-reversed version of the poly 0x04C11DB7
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ CRC_input;
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x00000001) == 0x00000001)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc >> 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc >> 1;
}
}
// Return the final remainder (CRC value)
return CRC_acc;
}
The following table lists several input values and the associated outputs using the 32-bit CRC algorithm
(an initial value of 0xFFFFFFFF is used):
Rev. 0.3
163
Si102x/3x
Table 12.2. Example 32-bit CRC Outputs
Input
Output
0x63
0xF9462090
0x41B207B3
0x78D129BC
164
Rev. 0.3
Si102x/3x
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Unused
CRC0SEL
CRC0PNT[1:0]
R/W
0
Function
CRC0INIT
CRC0VAL
Rev. 0.3
165
Si102x/3x
SFR Definition 12.2. CRC0IN: CRC0 Data Input
Bit
Name
CRC0IN[7:0]
Typ
R/W
Zurücksetzen
CRC0IN[7:0]
Function
Name
CRC0DAT[7:0]
Typ
R/W
Zurücksetzen
Function
166
Rev. 0.3
Si102x/3x
Name
AUTOEN
CRCDONE
CRC0ST[5:0]
R/W
Type
Reset
AUTOEN
R/W
Function
CRCDONE
5:0
CRC0ST[5:0]
R/W
Type
Reset
5:0
CRC0CNT[5:0]
Name
7:6
Unused
R/W
0
Function
Rev. 0.3
167
Si102x/3x
12.6. CRC0 Bit Reverse Feature
CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 12.2. Each byte
of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLIP, the
data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FFT.
CRC0FLIP
Write
CRC0FLIP
Read
Figure 12.2. Bit Reverse Register
Name
CRC0FLIP[7:0]
Typ
R/W
Zurücksetzen
CRC0FLIP[7:0]
Function
168
Rev. 0.3
Si102x/3x
13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)
Si102x/3x devices include a DMA-enabled cyclic redundancy check module (CRC1) that can perform a
CRC of data using an arbitrary 16-bit polynomial. This peripheral can compute CRC results using direct
DMA access to data in XRAM.
Using a DMA transfer provides much higher data throughput than using SFR access. Since the CPU can
be in Idle mode while the CRC is calculated, CRC1 also provides substantial power savings. The CRC1
module is not restricted to a limited list of fixed polynomials. Instead, the user can specify any valid 16-bit
polynomial.
CRC1 accepts a stream of 8-bit data written to the CRC1IN register. A DMA transfer can be used to autonomously transfer data from XRAM to the CRC1IN SFR. The CRC1 module may also be used with SFR
access by writing directly to the CRC1IN SFR. After each byte is written, the CRC resultant is updated on
the CRC1OUTH:L SFRs. After writing all data bytes, the final CRC results are available from the
CRC1OUTH:L registers. The final results may be flipped or inverted using the FLIP and INV bits in the
CRC1CN SFR. The initial seed value can be reset to 0x0000 or seeded with 0xFFFF.
x16+
7
0
6
0
5
0
4
1
3
0
CRC1POLL
2
0
1
0
0
0
7
0
x12+
6
0
5
1
4
0
3
0
2
0
x5+
1
0
0
1
Rev. 0.3
169
Si102x/3x
13.2. Endianness
The CRC1 module is optimized to process big endian data. Data written to the CRC1IN SFR should be in
the normal bit order with the most significant bit stored in bit 7 and the least significant bit stored in bit 0.
The input data is shifted left into the CRC engine. The CRC1 module will process one byte at a time and
update the results for each byte. When used with the DMA, the first byte to be written should be stored in
the lowest address.
Some communications systems may transmit data least significant bit first and may require calculation of a
CRC in the transmission bit order. In this case, the bits must be flipped, using the CRC0FLIP SFR, before
writing to the CRC1IN SFR. The final 16-bit result may be flipped using the flip bit in the CRC1CN SFR.
Note that the polynomial is always written in big endian bit order.
170
Rev. 0.3
Si102x/3x
13.3. CRC Seed Value
Normally, the initial value or the CRC results is cleared to 0x0000. However, a CRC might be specified with
an initial value preset to all ones (0xFFFF).
The steps to preset the CRC with all ones is as follows:
1. Set the SEED bit to 1.
2. Reset the CRC1 module by setting the CLR bit to 1 in CRC1CN.
3. Clear the SEED bit to 0.
The CRC1 module is not ready to calculate a CRC using a CRC seed value of 0xFFFF.
Rev. 0.3
171
Si102x/3x
13.6. Using CRC1 with SFR Access
The steps to perform a CRC using SFR access with the CRC1 module is as follow:
1. If desired, set the SEED bit in the CRC1CN SFR to seed with 0xFFFF.
2. Clear the CRC module by setting the CLR bit in the CRC1CN SFR.
3. Clear the SEED bit, if set previously in step 1.
4. Write the polynomial to CRC1POLH:L.
5. Write all data bytes to CRC1IN.
6. If desired, invert and/or flip the final results using the INV and FLIP bits.
7. Read the final CRC results from CRC1OUTH:L.
8. Clear the INV and/or FLIP bits, if set previously in step 6.
Note that all of the CRC1 SFRs are on SFR page 0x2.
Enable the interrupt on the desired channel by setting the corresponding bit in DMA0INT.
j.
172
Rev. 0.3
Si102x/3x
Name
CLR
Typ
R/W
Zurücksetzen
DMA
FLIP
INV
SEED
R/W
R/W
R/W
R/W
RST
6:4
3
Reserved
DMA
FLIP
INV
SEED
Reset.
Setting this bit to 1 will reset the CRC module and set the CRC results SFR to
the seed value as specified by the SEED bit. The CRC module should be reset
before starting a new CRC.
This bit is self-clearing.
DMA Mode.
Setting this bit will configure the CRC1 module for DMA mode.
Once a DMA channel has been configured to use accept peripheral requests
from CRC1, setting this bit will initiate a DMA CRC operation.
This bit should be cleared after each CRC DMA transfer.
Flip.
Setting this bit will flip the contents of the 16-bit CRC result SFRs.
(CRC0OUTH:CRC0OUTL)
This operation is normally performed only on the final CRC results.
This bit should be cleared before starting a new CRC computation.
Invert.
Setting this bit will invert the contents of the 16-bit CRC result SFR.
(CRC0OUTH:CRC0OUTL)
This operation is normally performed only on the final CRC results.
This bit should be cleared before starting a new CRC computation.
Seed Polarity.
If this bit is zero, a seed value or 0x0000 will be used.
If this bit is 1, a seed value of 0xFFFF will be used.
This bit should be set before setting the RST bit.
Rev. 0.3
173
Si102x/3x
SFR Definition 13.2. CRC1IN: CRC1 Data IN
Bit
CRC1IN[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
CRC1IN[7:0]
CRC1Data IN.
CRC Data should be sequentially written, one byte at a time, to the CRC1IN
Data input SFR.
When the CRC1 module is used with the DMA, the DMA will write directly to this
SFR.
CRC1POLL[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
CRC1POLH[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
174
Rev. 0.3
Si102x/3x
CRC1OUTL[7:0]
Name
Type
Zurücksetzen
CRC1OUTH[7:0]
Name
Type
Zurücksetzen
Rev. 0.3
175
Si102x/3x
14. Advanced Encryption Standard (AES) Peripheral
The Si102x/3x devices include a hardware implementation of the Advanced Encryption Standard Block
Cipher as specified in NIST publication FIPS 197 Advanced Encryption Standard (AES), November 2001.
The Rijndael encryption algorithm was chosen by NIST for the AES block cipher. The AES block cipher
can be used to encrypt data for wireless communications. Data can be encrypted before transmission and
decrypted upon reception. This provides security for private networks.
The AES block cipher is a Symmetric key encryption algorithm. Symmetric Key encryption relies on secret
keys that are known by both the sender and receiver. The decryption key may be obtained using a simple
transformation of the encryption key. AES is not a public key encryption algorithm.
The AES block Cipher uses a fixed 16 byte block size. So data less than 16 bytes must be padded with
zeros to fill the entire block. Wireless data must be padded and transmitted in 16-byte blocks. The entire
16-byte block must be transmitted to successfully decrypt the information.
The AES engine supports key lengths of 128-bits, 192-bits, or 256-bits. A key size of 128-bits is sufficient
to protect the confidentiality of classified secret information. The Advanced Encryption Standard was
designed to be secure for at least 20 to 30 years. The 128-bit key provides fastest encryption. The 192-bit
and 256-bit key lengths may be used to protect highly sensitive classified top secret information.
Since symmetric key encryption relies on secret keys, the security of the data can only be protected if the
key remains secret. If the encryption key is stored in flash memory, then the entire flash should be locked
to ensure the encryption key cannot be discovered. (See flash security.)
The basic AES block cipher is implemented in hardware. This hardware accelerator provides performance
that may be 1000 times faster than a software implementation. The higher performance translates to a
power savings for low-power wireless applications.
The AES block cipher, or block cipher modes based on the AES block cipher, is used in many wireless
standards. These include several IEEE standards in the wireless PAN (802.15) and wireless LAN (802.11)
working groups.
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14.1. Hardware Description
AES0BIN
AES0XIN
internal state
machine
+
AES0DCF
Data In
AES0KIN
Key
In
AES
Core
Key
Out
Data Out
AES0BCFG
AES0YOUT
Figure 14.1. AES Peripheral Block Diagram
The AES Encryption module consists of the following elements:
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14.1.1. AES Encryption/Decryption Core
The AES Encryption/Decryption Core is a digital implementation of the Advanced Encryption Standard
block cipher. The core may be used for either encryption or decryption. Encryption may be selected by setting bit 5 in the AES0BCFG SFR. When configured for encryption, plaintext is written to the AES Core data
input and the encrypted ciphertext is read from the Data Output. Conversely, when configured for Decryption, encrypted ciphertext is written to the data input and decrypted plaintext is read form the Data Output.
When configured for Encryption, the encryption key must be written to the Key Input. When configured for
decryption, the decryption key must be written to the Key Input.
The AES core may also be used to generate a decryption key from a known encryption key. To generate a
decryption key, the core must be configured for encryption, the encryption key is written to the Key Input,
and the Decryption Key may be read from the Key output.
AES is a symmetric key encryption algorithm. This means that the decryption key may be generated from
an encryption key using a simple algorithm. Both keys must remain secret. If security of the encryption key
is compromised, one can easily generate the decryption key.
Since it is easy to generate the decryption key, only the encryption key may be stored in Flash memory.
14.1.2. Data SFRs
The data SFRs are used for the data flow into and out of the AES module. When used with the DMA, the
DMA itself will write to and read from the data SFRs. When used in manual mode, the data must be written
to the data SFRs one byte at a time in the proper sequence.
The AES0KIN SFR provides a data path for the AES core Key input. For an encryption operation, the
encryption key is written to the AES0KIN SFR, either by the DMA or direct SFR access. For a decryption
operation, the decryption key must be written to the AES0KIN SFR.
The AES0BIN is the direct data input SFR for the AES block. For a simple encryption operation, the plaintext is written to the AES0BIN SFR either by the DMA or direct SFR access. For decryption, the ciphertext to be decrypted is written to the AES0BIN SFR. The AES0BIN SFR is also used together with the
AES0XIN when an exclusive OR operation is required on the input data path.
The AES0XIN SFR provides an input data path to the exclusive OR operator. The AES0XIN is not used for
simple AES block cipher encryption or decryption. It is only use for block cipher modes that require an
exclusive OR operator on the input or output data.
The AES core requires that the input data bytes are written in a specific order. When used with the DMA,
this is managed by the internal state machine. When using direct SFR access, each of input data must be
written one byte at a time to each SFR in this particular order.
1. Write AES0BIN
2. Write AES0XIN (optional)
3. Write AES0KIN
This sequence is repeated 16 times. When using a 192-bit or 256-bit key length, the remaining additional
key bytes are written after writing all sixteen of the AES0BIN and AES0XIN bytes.
After encryption or decryption is completed, the resulting data may be read from the AES0YOUT. Optionally, exclusive OR data may be written to the AES0XIN SFR before reading the AES0YOUT SFR.
1. Write AES0XIN (optional)
2. Read AES0YOUT
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14.1.3. Configuration sfrs
The AES Module has two configuration SFRs. The AES0BCFG SFR is used to configure the AES core.
Bits 0 and 1 are used to select the key size. The AES core supports 128-bit, 192-bit and 256-bit encryption.
Bit 2 selects encrypt or decrypt. The AES enable bit (bit 3) is used to enable the AES module and start new
encryption operation. The AES DONE bit (bit 5) is the AES interrupt flag that signals a block of data has
been completely encrypted or decrypted and is ready to be read from the AES0YOUT SFR. Note that the
AES DONE interrupt is not normally used when the AES module is used with the DMA. Instead, the DMA
interrupt is used to signal that the encrypted or decrypted data has been transferred completely to memory.
The DMA done interrupt is normally only used with direct SFR access.
The AES0DCFG SFR is used to select the data path for the AES module. Bits 0 through 2 are used to
select the input and output multiplexer configuration. The AES data path should be configured prior to initiating a new encryption or decryption operation.
14.1.4. Input Multiplexer
The input multiplexer is used to select either the contents of the AES0BIN SFR or the contents of the
AES0BIN SFR exclusive ORed with the contents of the AES0XIN SFR. The exclusive OR input data path
provides support for CBC encryption.
14.1.5. Output Multiplexer
The output multiplexer selects the data source for the AES0YOUT SFR. The three possible sources are
the AES Core data output, the AES core key output, and the AES core data output exclusive ORed with
the AES0XIN SFR.
The AES core data output is used for simple encryption and decryption.
The exclusive OR output data path provides support for CBC mode decryption and CTR mode encryption/decryption. The AES0XIN is the source for both input and output exclusive OR data. When the
AES0XIN is used with the input exclusive OR data path, the AEXIN data is written in sequence with the
AES0BIN data. When used with the output XRO data path, the AES0XIN data is written after the encryption or decryption operation is complete.
The Key output is used to generate an inverse key. To generate a decryption key from an encryption key,
the AES core should be configured for an encryption operation. To generate an encryption key from a
decryption key, the AES core should be configured for a decryption operation.
14.1.6. Internal State Machine
The AES module has an internal state machine that manages the data flow. The internal state machine
accommodates the two different usage scenarios. When using the DMA, the internal state machine will
send peripheral requests to the DMA requesting the DMA to transfer data from XRAM to the AES module
input SFRs. Upon the completion of one block of data, the AES module will send peripheral requests
requesting data to be transferred from the AES0YOUT SFR to XRAM. These peripheral requests are managed by the internal state machine.
When not using the DMA, data must be written and read in a specific order. The DMA state machine will
advance with each byte written or read.
The internal state machine may be reset by clearing the enable bit in the AESBGFG SFR. Clearing the
enable bit before encryption or decryption operation will ensure that the state machine starts at the proper
state.
When encrypting or decrypting multiple blocks it is not necessary to disable the AES module between
blocks, as long as the proper sequence of events is obeyed.
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14.2. Key Inversion
The key output is used to generate an inverse key. To generate a decryption key from an encryption key,
the AES core should be configured for an encryption operation. Dummy data and the encryption key are
written to the AES0BIN and AES0KIN SFRs respectively. The output multiplexer should be configured to
output the decryption key to the AES0YOUT SFR.
AES0BIN
AES0XIN
internal state
machine
+
AES0DCFG
Data In
AES0KIN
Key
In
AES
Core
Key
Out
Data Out
AES0BCFG
AES0YOUT
Figure 14.2. Key Inversion Data Flow
The dummy data may be zeros or arbitrary data. The content of the dummy data does not matter. But sixteen bytes of data must be written to the AES0BIN SFR to generate the inverse key.
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14.2.1. Key Inversion using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power consumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are listed here for completeness.
Steps to generate the Decryption Key from Encryption Key
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The key and data to be encrypted should be stored as an array with the first byte to be encrypted at the
lowest address. The value of the big endian bit of the DMACF0 SFR does not matter. The AES block uses
only one byte transfers, so there is no particular endianness associated with a one byte transfer.
The dummy data can be zeros or any value. The encrypted data is discarded, so the value of the dummy
data does not mater.
It is not strictly required to use DMA channels 0, 1, and 2. Any three DMA channels may be used. The
internal state machine of the AES module will send the peripheral requests in the required order.
If the other DMA channels are going to be used concurrently with encryption, then only the bits corresponding to the encryption channels should be manipulated in DM0AEN and DMA0NT SFRs.
14.2.2. Key Inversion using SFRs
Normally, the AES block is used with the DMA. This provides the best performance and lowest power consumption. However, it is also possible to use the DMA with direct SFR access. The steps are documented
here for completeness.
Steps to generate the decryption key from the encryption key using SFR access follow:
If using 192-bit and 256-bit key, write remaining key bytes to AES0KIN:
Wait on AES done interrupt or poll bit 5 of AES0BCFG
Read first byte of the decryption key from AES0YOUT
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14.2.3. Extended Key Output Byte Order
When using a key length of 128-bits, the key output is in the same order as the bytes were written. When
using an extended key of 192-bits or 256-bits. The extended portion of the key comes out first, before the
first 16-bytes of the extended key.This is illustrated in Table 14.1.
Input
Output
Order
Bits
Bytes
Order
128
16
K0...15
192
24
K0...23
256
32
K0...31
K0...15
K16...23
Rev. 0.3
K16...23
K0...15
K24...31
K0...15
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14.2.4. Using the DMA to unwrap the extended Key
When used with the DMA, the address offset sfr DMANAOH/L may be manipulated to store the extended
key in the desired order. This requires two DMA transfers for the AES0YOUT channel. When using a 192bit key, the DMA0NSZ can be set to 24 bytes and the DMA0NA0 set to 16. This will place the last 8 bytes
of the 192-bit key in the desired location as shown in Table 14.2. The Yout arrow indicates the address offset position after each 8 bytes are transferred. Enabling the WRAP bit in DMA0NMD will reset the
DMA0NAO value after byte 23. Then the DMA0NZ can be reset to 16 for the remaining sixteen bytes.
Yout
K16...23
Yout
K0...7
K16...23
Yout
K0...7
K8...15
K16...23
When using a 256-bit key, DMA0NSZ can be set to 32 and DMA0NAOL set to 16 This will place the last 16
bytes of the 256-bit key in the desired location as shown in Table 14.3. Enabling the WRAP bit in
DMA0NMD will reset the DMA0NAO value after byte 31. Then DMA0NZ can be set to 16 for the remaining
sixteen bytes.
Yout
K16...23
Yout
K16...23
K24...31
K16...23
K24...31
Yout
K0...7
Yout
K0...7
184
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K16...23
Rev. 0.3
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Si102x/3x
14.3. AES Block Cipher
The basic AES Block Cipher is the basic encryption/decryption algorithm as defined by the NIST standard.
A clock cipher mode is a method of encrypting and decrypting one block of data. The input data and output
data are not manipulated, chained, or exclusive ORed with other data. This simple block cipher mode is
sometimes called the Electronic Code Book (ECB) mode. This mode is illustrated in Figure 14.3
Each operation represents one block (sixteen bytes) of data. The plaintext is the plain unencrypted data.
The ciphertext is the encrypted data. The encryption key and decryption keys are symmetric. The decryption key is the inverse key of the decryption key. Note that the Encryption operation is not the same as the
decryption operation. The two operations are different and the AES core operates differently depending on
whether encryption or decryption is selected.
Note that each encryption or decryption operation is independent of other operations. Also note that the
same key is used over and over again for each operation.
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14.4. AES Block Cipher Data Flow
The AES0 module data flow for AES Block Cipher encryption and decryption shown in Figure 14.3. The
data flow is the same for encryption and decryption. The AES0DCF SFR is always configured to route the
AES core output to AES0YOUT. The XOR on the input and output paths are not used.
For an encryption operation, the core is configured for an encryption cipher, the encryption key is written to
AES0KIN, the plaintext is written to the AES0BIN SFR. and the ciphertext is read from AES0YOUT.
For a decryption operation, the core is configured for an decryption cipher, the decryption key is written to
AES0KIN, the ciphertext is written to the AES0BIN SFR. and the plaintext is read from AES0YOUT.
The key size is set to the desired key size.
AES0BIN
AES0XIN
internal state
machine
+
AES0DCFG
Data In
AES0KIN
Key
In
AES
Core
Key
Out
Data Out
AES0BCFG
AES0YOUT
Figure 14.3. AES Block Cipher Data Flow
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14.4.1. AES Block Cipher Encryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power consumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are listed here for completeness.
Steps to encrypt data using Simple AES block encryption (ECB mode)
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14.4.2. AES Block Cipher Encryption using SFRs
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit encryption only.
Wait on AES done interrupt or poll bit 5 of AES0BCFG.
Read 16 encrypted bytes from AES0YOUT.
If encrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES module for each block.
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14.5. AES Block Cipher Decryption
14.5.1. AES Block Cipher Decryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power consumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are listed here for completeness.
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14.5.2. AES Block Cipher Decryption using SFRs
Write remaining decryption key bytes to AES0KIN for 192-bit and 256-bit decryption only.
Wait on AES done interrupt or poll bit 5 of AES0BCFG.
Read 16 plaintext bytes from AES0YOUT.
If decrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES module for each block.
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14.6. Block Cipher Modes
14.6.1. Cipher Block Chaining Mode
The Cipher Block Chaining (CBC) algorithm significantly improves the strength of basic AES encryption by
making each block encryption be a function of the previous block in addition to the current plaintext and
key. This algorithm is shown inFigure 14.4
Encryption
Decryption
Encryption
Key
Decryption
Key
Plain Text
Plain Text
XOR
XOR
Encryption
Cipher
Encryption
Key
Encryption
Cipher
Cipher Text
Cipher Text
Cipher Text
Cipher Text
Decryption
Cipher
Decryption
Key
Decryption
Cipher
XOR
XOR
Plain Text
Plain Text
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14.6.1.1. CBC Encryption Data Flow
The AES0 module data flow for CBC encryption is shown in Figure 14.5. The plaintext is written to
AES0BIN. For the first block, the initialization vector is written to AES0XIN. For subsequent blocks, the
previous block ciphertext is written to AES0XIN. AES0DCFG is configured to XOR AES0XIN with
AES0BIN for the AES core data input. The XOR on the output is not used. The AES core is configured for
an encryption operation. The encryption key is written to AES0KIN. The key size is set to the desired key
size.
AES0BIN
AES0XIN
internal state
machine
+
AES0DCFG
Data In
AES0KIN
Key
In
AES
Core
Key
Out
Data Out
AES0BCFG
AES0YOUT
Figure 14.5. CBC Encryption Data Flow
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14.6.2. CBC Encryption Initialization Vector Location
The first block to be encrypted uses the initialization vector for the AES0XIN data. Subsequent blocks will
use the encrypted ciphertext from the previous block. The DMA is capable of encrypting multiple bocks. If
the initialization is located at an arbitrary location in XRAM, the DMA base address location will need to be
changed to the start of the encrypted ciphertext after encrypting the first block. However, if the initialization
vector is located in XRAM immediately before the encrypted ciphertext, the pointer will be advanced to the
start of the encrypted ciphertext, and multiple blocks can be encrypted autonomously.
14.6.3. CBC Encryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power consumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are listed here for completeness.
Rev. 0.3
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194
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Si102x/3x
14.6.3.1. CBC Encryption using SFRs
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit decryption only.
Wait on AES done interrupt or poll bit 5 of AES0BCFG.
Read 16 encrypted bytes from AES0YOUT.
If encrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES module for each block. When using Cipher Block Chaining, the initialization vector is written to AES0XIN for the
first block only, as described. Additional blocks will chain the encrypted data from the previous block.
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14.6.4. CBC Decryption
The AES0 module data flow for CBC decryption is shown in Figure 14.6. The ciphertext is written to
AES0BIN. For the first block, the initialization vector is written to AES0XIN. For subsequent blocks, the
previous block ciphertext is written to AES0XIN. AES0DCFG is configured to XOR AES0XIN with the AES
core data output. The XOR on the input is not used. The AES core is configured for a decryption operation.
The decryption key is written to AES0KIN. The key size is set to the desired key size.
AES0BIN
AES0XIN
internal state
machine
+
AES0DCFG
Data In
AES0KIN
Key
In
AES
Core
Key
Out
Data Out
AES0BCFG
AES0YOUT
Figure 14.6. CBC Decryption Data Flow
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14.6.4.1. CBC Decryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power consumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are listed here for completeness.
Select
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14.6.4.2. CBC Decryption using SFRs
First Configure AES Module for CBC Block Cipher Mode Decryption
Reset
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit decryption only.
Wait on AES done interrupt or poll bit 5 of AES0BCFG.
Repeat alternating write read sequence 16 times
Write
Read
If decrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES module for each block. When using Cipher Block Chaining the initialization vector is written to AES0XIN for the
first block only, as described. Additional blocks will chain the ciphertext data from the previous block.
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14.6.5. Counter Mode
The Counter (CTR) Mode uses a sequential counter which is incremented after each block. This turns the
block cipher into a stream cipher. This algorithm is shown inFigure 14.4. Note that the decryption operation
actually uses the encryption key and encryption block cipher. The XOR operation is always on the output
of the cipher. The counter is a 16-byte block. Often, several bytes of the counter are initialized to a nonce
(number used once). The last byte of the counter is incremented and propagated. Thus, the counter is
treated as a 16-byte big endian integer.
Counter
(0x00...00)
Encryption
Encryption Key
Plaintext
Decryption
Encryption
Key
Ciphertext
Encryption
Cipher
Counter
(0x00...01)
Encryption Key
XOR
Plaintext
Encryption
Cipher
XOR
Ciphertext
Ciphertext
Counter
(0x00...00)
Counter
(0x00...01)
Encryption
Cipher
Encryption
Key
XOR
Plaintext
Ciphertext
Encryption
Cipher
XOR
Plaintext
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14.6.5.1. CTR Data Flow
The AES0 module data flow for CTR encryption and decryption shown in Figure 14.5. The data flow is the
same for encryption and decryption. AES0DCFG is always configured to XOR AES0XIN with the AES core
output.The XOR on the input is not used. The AES core is configured for an encryption operation. The
encryption key is written to AES0KIN. The key size is set to the desired key size.
For an encryption operation, the plaintext is written to AES0BIN and the ciphertext is read from
AES0YOUT. For decryption, the ciphertext is written to AES0BIN and the plaintext is read from
AES0YOUT.
Note the counter must be incremented after each block using software.
AES0BIN
AES0XIN
internal state
machine
+
AES0DCFG
Data In
AES0KIN
Key
In
AES
Core
Key
Out
Data Out
AES0BCFG
AES0YOUT
Figure 14.8. Counter Mode Data Flow
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14.6.6. CTR Encryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power consumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use the code examples. The steps are listed here for completeness.
Select
Rev. 0.3
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14.6.6.1. CTR Encryption using SFRs
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit decryption only.
Wait on AES done interrupt or poll bit 5 of AES0BCFG.
Read 16 encrypted bytes from AES0YOUT.
If encrypting multiple blocks, increment the counter and repeat this process. It is not necessary reconfigure
the AES module for each block.
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Name
DONE
BUSY
EN
ENC
KSIZE
R/W
Typ
R/W
R/W
R/W
Zurücksetzen
DONE
Done Flag.
This bit is set upon completion of an encryption operation. When used with the DMA,
the DONE bit signals the start of the out transfer. When used without the DMA, the
done flag indicates data is ready to be read from AES0YOUT. The DONE bit is not
cleared by hardware and must be cleared to zero by software at the start of the next
encryption operation.
BUSY
AES BUSY.
This bit is set while the AES block is engaged in an encryption or decryption operation.
This bit is read only.
EN
AES Enable.
This bit should be set to 1 to initiate an encryption or decryption operation. Clearing this
bit to 0 will reset the AES module.
ENC
Encryption/Decryption Select.
This is set to 1 to select an encryption operation. Clearing this bit to 0 will select a
decryption operation.
1:0
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SFR Definition 14.2. AES0DCFG: AES Data Configuration
Bit
Name
Type
Zurücksetzen
OUTSEL[1:0]
XORIN
R/W
R/W
OUTSEL[1:0]
DATA Select.
These bits select the output data source for the AES0YOUT sfr.
00: Direct AES Data
01: AES Data XOR with AES0XIN
10: Inverse Key
11: reserved
XORIN
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AES0BIN[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
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SFR Definition 14.4. AES0XIN: AES XOR Input
Bit
AES0XIN[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
AES0KIN[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
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AES0YOUT[7:0]
Name
Type
Zurücksetzen
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15. Encoder/Decoder
The Encoder/Decoder consists of three 8-bit data registers, a control register and an encoder/decoder
logic block.
The size of the input data depends on the mode. The input data for Manchester encoding is one byte. For
Manchester decoding it is two bytes. Three-out-of-Six encoding is two bytes. Three-out-of six decoding is
three bytes.
The output size also depends on the mode selected. The input and output data size are shown below:
Bytes
Bytes
Manchester Encode
Manchester Decode
The input and output data is always right justified. So for Manchester mode the input uses only ENC0L and
the output data is only in ENC0M and ENC0L. ENC0H is not used for Manchester mode
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15.1. Manchester Encoding
To encode Manchester Data, first clear the MODE bit for Manchester encoding or decoding.
To encode, one byte of data is written to the data register ENC0L.
Setting the ENC bit will initiate encoding. After encoding, the encoded data will be in ENC0M and ENC0L.
The upper nibble of the input data is encoded and placed in ENC0M. The lower nibble is encoded and
placed in ENC0L.
Note that the input data should be readable in the data register until the encode bit is set. Once the READY
bit is set, the input data has been replaced by the output data.
The ENC and DEC bits are self clearing. The READY bit is not cleared by hardware and must be cleared
manually. The control register does not need to be bit addressable. The READY bit can be cleared while
setting the ENC or DEC bit using a direct or immediate SFR mov instruction.
Encoded Output
nibble
byte
dec
hex
bin
bin
hex
dec
0000
10101010
AA
170
0001
10101001
A9
169
0010
10100110
A6
166
0011
10100101
A5
165
0100
10011010
9A
154
0101
10011001
99
153
0110
10010110
96
150
0111
10010101
95
149
1000
01101010
6A
106
1001
01101001
69
105
10
1010
01100110
66
102
11
1011
01100101
65
101
12
1100
01011010
5A
90
13
1101
01011001
59
89
14
1110
01010110
56
86
15
1111
01010101
55
85
Rev. 0.3
209
Si102x/3x
15.2. Manchester Decoding
Two bytes of Manchester data are written to ENC0M and ENC0L sfrs. Then the DEC bit is set to initiate
decoding. After decoding the READY bit will be set. If the data is not a valid encoded Manchester data, the
ERROR bit will be set, and the output will be all FFs.
The encoding and decoding process should be symmetric. Data can be written to the ENC0L sfr, then
encoded, then decoding will give the original data.
210
Input
Decoded Output
Byte
Nibble
bin
hex
dec
dec
hex
bin
01010101
55
85
15
1111
01010110
56
86
14
1110
01011001
59
89
13
1101
01011010
5A
90
12
1100
01100101
65
101
11
1011
01100110
66
102
10
1010
01101001
69
105
1001
01101010
6A
106
1000
10010101
95
149
0111
10010110
96
150
0110
10011001
99
153
0101
10011010
9A
154
0100
10100101
A5
165
0011
10100110
A6
166
0010
10101001
A9
169
0001
10101010
AA
170
0000
Rev. 0.3
Si102x/3x
15.3. Three-out-of-Six Encoding
Three out of six encoding is similar to Manchester encoding. In Three-out-of-Six encoding a nibble is
encoded as a six-bit symbol. Four nibbles are encoded as 24-bits (three bytes).
Two bytes of data to be encoded are written to ENC0M and ENC0L. The MODE bit is set to 1 for Threeout-of-Six encoding. Setting the ENC bit will initiate encoding.
After encoding, the three encoded bytes are in ENC2-0.
Encoded Output
nibble
symbol
dec
hex
bin
bin
dec
hex
octal
0000
010110
22
16
26
0001
001101
13
0D
15
0010
001110
14
0E
16
0011
001011
11
0B
13
0100
011100
28
1C
34
0101
011001
25
19
31
0110
011010
26
1A
32
0111
010011
19
13
23
1000
101100
44
2C
54
1001
100101
37
25
45
10
1010
100110
38
26
46
11
1011
100011
35
23
43
12
1100
110100
52
34
64
13
1101
110001
49
31
61
14
1110
110010
50
32
62
15
1111
101001
41
29
51
Rev. 0.3
211
Si102x/3x
15.4. Three-out-of-Six Decoding
Three-out-of-Six decoding is a similar inverse process. Three bytes of encoded data are written to ENC20. The DEC bit is set to initiate decoding. The READY bit will be set when decoding is complete. The
ERROR bit will be set if the input date is not valid Three-out-of-Six data.
The Three-out-of-Six encoder decode process is also symmetric. Two bytes of arbitrary data may be written to ENC0M-ENC0L, then encoded, then decoding will yield the original data.
212
Input
Decoded Output
Symbol
Nibble
bin
octal
dec
dec
hex
bin
001011
13
11
0011
001101
15
13
0001
001110
16
14
0010
010011
23
19
0111
010110
26
22
0000
011001
31
25
0101
011010
32
26
0110
011100
34
28
0100
100011
43
35
11
1011
100101
45
37
1001
100110
46
38
10
1010
101001
51
41
15
1111
101100
54
44
1000
110001
61
49
13
1101
110010
62
50
14
1110
110100
64
52
12
1100
Rev. 0.3
Si102x/3x
15.5. Encoding/Decoding with SFR Access
The steps to perform a Encode/Decode operation using SFR access with the ENC0 module are as follow:
1. Clear ENC0CN by writing 0x00.
2. Write the input data to ENC0H:M:L.
3. Write the operation value to ENC0CN setting ENC, DEC, and MODE bits as desired and clearing all
other bits.
a. Write 0x10 for Manchester Decode operation.
b. Write 0x11 for Three-out-of-Six Decode operation.
c. Write 0x20 for Manchester Encode operation.
d. Write 0x21 for Three-out-of-Six Encode operation.
4. Wait on the READY bit in ENC0CN.
5. For a decode operation only, check the ERROR bit in ENC0CN for a decode error.
6. Read the results from ENC0H:M:L.
7. Repeat steps 2-6 for all remaining data.
Note that all of the ENC0 SFRs are on SFR page 0x2. The READY and ERROR must be cleared in
ENC0CN with each operation.
Rev. 0.3
213
Si102x/3x
15.7. Using the ENC0 module with the DMA
The steps for Encoding/Decoding using the DMA are as follows.
1. Clear the ENC module by writing 0x00 to the ENC0CN SFR.
2. Configure the first DMA channel for the XRAM-to-ENC0 input transfer:
a. Disable the first DMA channel by clearing the corresponding bit in DMA0EN.
b. Select the first DMA channel by writing to DMA0SEL.
c. Configure the selected DMA channel to use the XRAM-to-ENC0 input peripheral request by
writing 0x00 to DMA0NCF.
d. Set the ENDIAN bit in DMA0NCF to enable big-endian multi-byte DMA transfers.
e. Write 0 to DMA0NMD to disable wrapping.
f.
g. Write the address for the first byte of the output data to DMA0NBAH:L.
h. Write the size of the output data transfer in bytes to DMA0NSZH:L.
i.
j.
Enable the interrupt on the second channel by setting the corresponding bit in DMA0INT.
214
Rev. 0.3
Si102x/3x
Name
READY
ERROR
ENC
DEC
Typ
R/W
R/W
Zurücksetzen
DMA
ENDIAN
MODE
R/W
R/W
R/W
Bit
Name
Function
READY
Ready Flag.
ERROR
Error Flag.
ENC
Encode.
Setting this bit will initiate an Encode operation.
DEC
Decode.
Setting this bit will initiate a Decode operation.
DMA
ENDIAN
MODE
Mode.
0: Select Manchester encoding or decoding.
1:Select Three-out-of-Six encoding or decoding.
Rev. 0.3
215
Si102x/3x
SFR Definition 15.2. ENC0L: ENC0 Data Low Byte
Bit
ENC0L[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
ENC0L[7:0]
Function
ENC0M[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
ENC0M[7:0]
Function
ENC0H[7:0]
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
216
ENC0H[7:0]
Rev. 0.3
Function
Si102x/3x
16. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the Si102x/3x's resources and peripherals. The
CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as implementing
additional SFRs used to configure and access the sub-systems unique to the Si102x/3x. This allows the
addition of new functionality while retaining compatibility with the MCS-51 instruction set. Table 16.3 lists
the SFRs implemented in the Si102x/3x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing unoccupied addresses in the SFR
space will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the
data sheet, as indicated in Table 16.3, for a detailed description of each register.
Rev. 0.3
217
Si102x/3x
SFRPGCN Bit
Interrupt
Logic
SFRPAGE
CIP-51
SFRNEXT
SFRLAST
218
Rev. 0.3
Si102x/3x
16.3. SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts. In this
example, the SFR Control register is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51
is executing in-line code that is writing values to SMBus Address Register (SFR SMB0ADR, located at
address 0xF4 on SFR Page 0x0). The device is also using the SPI peripheral (SPI0) and the Programmable Counter Array (PCA0) peripheral to generate a PWM output. The PCA is timing a critical control function in its interrupt service routine, and so its associated ISR is set to high priority. At this point, the SFR
page is set to access the SMB0ADR SFR (SFRPAGE = 0x0). See Figure 16.2.
SFR Page
Stack SFR's
0x0F
SFRPAGE
(SMB0ADR)
SFRNEXT
SFRLAST
Figure 16.2. SFR Page Stack While Using SFR Page 0x0 To Access SMB0ADR
While CIP-51 executes in-line code (writing a value to SMB0ADR in this example), the SPI0 Interrupt
occurs. The CIP-51 vectors to the SPI0 ISR and pushes the current SFR Page value (SFR Page 0x0F) into
SFRNEXT in the SFR Page Stack. SFRPAGE is considered the top of the SFR Page Stack. Software
may switch to any SFR Page by writing a new value to the SFRPAGE register at any time during the SPI0
ISR. See Figure 16.3.
Rev. 0.3
219
Si102x/3x
SFR Page 0x00
Automatically
pushed on stack in
SFRPAGE on SPI0
interrupt
0x00
SFRPAGE
SFRPAGE
pushed to
SFRNEXT
(SPI0)
0x0F
SFRNEXT
(SMB0ADR)
SFRLAST
220
Rev. 0.3
Si102x/3x
0x00
SFRPAGE
SFRPAGE
pushed to
SFRNEXT
(PCA0)
0x00
SFRNEXT
SFRNEXT
pushed to
SFRLAST
(SPI0)
0x0F
SFRLAST
(SMB0ADR)
Figure 16.4. SFR Page Stack Upon PCA Interrupt Occurring During a SPI0 ISR
On exit from the PCA interrupt service routine, the CIP-51 will return to the SPI0 ISR. On execution of the
RETI instruction, SFR Page All Pages used to access the PCA registers will be automatically popped off of
the SFR Page Stack, and the contents of the SFRNEXT register will be moved to the SFRPAGE register.
Software in the SPI0 ISR can continue to access SFRs as it did prior to the PCA interrupt. Likewise, the
contents of SFRLAST are moved to the SFRNEXT register. Recall this was the SFR Page value 0x0F
being used to access SMB0ADR before the SPI0 interrupt occurred. See Figure 16.5.
Rev. 0.3
221
Si102x/3x
SFR Page 0x00
Automatically
popped off of the
stack on return from
interrupt
0x00
SFRPAGE
SFRNEXT
popped to
SFRPAGE
(SPI0)
0x0F
SFRNEXT
SFRLAST
popped to
SFRNEXT
(SMB0ADR)
SFRLAST
Figure 16.5. SFR Page Stack Upon Return From PCA Interrupt
On the execution of the RETI instruction in the SPI0 ISR, the value in SFRPAGE register is overwritten
with the contents of SFRNEXT. The CIP-51 may now access the SMB0ADR register as it did prior to the
interrupts occurring. See Figure 16.6.
222
Rev. 0.3
Si102x/3x
0x0F
SFRPAGE
SFRNEXT
popped to
SFRPAGE
(SMB0ADR)
SFRNEXT
SFRLAST
Figure 16.6. SFR Page Stack Upon Return From SPI0 Interrupt
In the example above, all three bytes in the SFR Page Stack are accessible via the SFRPAGE, SFRNEXT,
and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is possible to
return to a different SFR Page upon interrupt exit than selected prior to the interrupt call. Direct access to
the SFR Page stack can be useful to enable real-time operating systems to control and manage context
switching between multiple tasks.
Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on
interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation
of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic
Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFR0CN). See SFR Definition 16.1.
Rev. 0.3
223
Si102x/3x
SFR Definition 16.1. SFRPGCN: SFR Page Control
Bit
Name
0
SFRPGEN
Typ
R/W
Zurücksetzen
Unused
Function
224
Rev. 0.3
Si102x/3x
Name
SFRPAGE[7:0]
Typ
R/W
Zurücksetzen
SFRPAGE[7:0]
Function
Rev. 0.3
225
Si102x/3x
SFR Definition 16.3. SFRNEXT: SFR Next
Bit
Name
SFRNEXT[7:0]
Typ
R/W
Zurücksetzen
SFRNEXT[7:0]
Function
226
Rev. 0.3
Si102x/3x
Name
SFRLAST[7:0]
Typ
R/W
Zurücksetzen
SFRLAST[7:0]
Function
Rev. 0.3
227
Si102x/3x
Table 16.1. SFR Map (0xC00xFF)
Addr.
Page
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
0xF8
0x0
SPI0CN
PCA0L
PCA0H
PCA0CPL0
PCA0CPH0
PCA0CPL4
PCA0CPH4
VDM0CN
0x2
SPI1CN
PC0DCL
PC0DCH
PC0INT0
PC0INT1
DC0RDY
0xF
P4MDOUT
P5MDOUT
P6MDOUT
P7MDOUT
CLKMODE
PCLKEN
0x0
P0MDIN
P1MDIN
P2MDIN
SMB0ADR
SMB0ADM
EIP1
EIP2
0x2
PC0CMP1L
PC0CMP1M
PC0CMP1H
PC0HIST
AES0YOUT
0xF
P3MDIN
P4MDIN
P5MDIN
P6MDIN
PCLKACT
PCA0CPL1
PCA0CPH1
PCA0CPL2
PCA0CPH2
PCA0CPL3
PCA0CPH3
RSTSRC
0x2
AES0BCFG
AES0DCFG
AES0BIN
AES0XIN
AES0KIN
0xF
DEVICEID
REVID
XBR0
XBR1
XBR2
IT01CF
EIE1
EIE2
0x2
PC0CMP0L
PC0CMP0M
PC0CMP0H
PC0TH
0xF
XBR0
XBR1
XBR2
IT01CF
PCA0MD
PCA0CPM0
PCA0CPM1
PCA0CPM2
PCA0CPM3
PCA0CPM4
PCA0PWM
0x2
PC0MD
PC0CTR0L
PC0TRML
PC0CTR0H
PC0CTR1L
PC0TRMH
PC0CTR1H
0xF
P4
P5
P6
P7
REF0CN
PCA0CPL5
PCA0CPH5
P0SKIP
P1SKIP
P2SKIP
P0MAT
DMA0SEL
DMA0EN
DMA0INT
DMA0MINT
DMA0BUSY
DMA0NMD
PC0PCF
REG0CN
TMR2RLL
TMR2RLH
TMR2L
TMR2H
PCA0CPM5
P1MAT
DMA0NCF
DMA0NBAL
DMA0NBAH
DMA0NAOL
DMA0NAOH
DMA0NSZL
DMA0NSZH
SMB0CF
SMB0DAT
ADC0GTL
ADC0GTH
ADC0LTL
ADC0LTH
P0MASK
PC0STAT
ENC0L
ENC0M
ENC0H
ENC0CN
VREGINSDL
VREGINSDH
0xF0
0xE8
0xE0
0xD8
0xD0
0x0
0x0
0x0
0x0
ADC0CN
ACC
PCA0CN
PSW
0x2
0xF
0xC8
0x0
TMR2CN
0x2
0xF
0xC0
0x0
0x2
SMB0CN
0xF
228
Rev. 0.3
Si102x/3x
Table 16.2. SFR Map (0x800xBF)
Addr. Page
0xB8
0xB0
0xA8
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
IP
IREF0CN
ADC0AC
ADC0MX
ADC0CF
ADC0L
ADC0H
P1MASK
0x2
CRC1IN
CRC1OUTL
CRC1OUTH
CRC1POLL
CRC1POLH
CRC1CN
0xF
IREF0CF
ADC0PWR
ADC0TK
TOFFL
TOFFH
OSCXCN
OSCICN
PMU0MD
PMU0CF
PMU0FL
0x2
DC0CN
DC0CF
DC0MD
LCD0CHPCN
LCD0BUFMD
0xF
P3MDOUT
OSCIFL
OSCICL
CLKSEL
EMI0CN
EMI0CF
RTC0ADR
RTC0DAT
LCD0MSCN
LCD0MSCF
LCD0CHPCF
0x0
0x0
0x0
P3
IE
0x2
LCD0CLKDIVL LCD0CLKDIVH
0xF
0xA0
0x98
EMI0TC
LCD0CHPMD LCD0VBMCF
P7DRV
LCD0BUFCF
SPI0CFG
SPI0CKR
SPI0DAT
P0MDOUT
P1MDOUT
P2MDOUT
0x2
SPI1CFG
SPI1CKR
SPI1DAT
LCD0PWR
LCD0CF
LCD0VBMCN
0xF
P3DRV
P4DRV
P5DRV
P0DRV
P1DRV
P2DRV
SBUF0
CPT1CN
CPT0CN
CPT1MD
CPT0MD
CPT1MX
CPT0MX
LCD0DD
LCD0DE
LCD0DF
LCD0CNTRST
LCD0CN
LCD0BLINK
LCD0TOGR
LCD0DB
LCD0DC
CRC0AUTO
CRC0CNT
PSCTL
0x0
0x0
P2
SCON0
0x0
TMR3CN
TMR3RLL
TMR3RLH
TMR3L
TMR3H
0x2
LCD0D6
LCD0D7
LCD0D8
LCD0D9
LCD0DA
0xF
CRC0DAT
CRC0CN
CRC0IN
CRC0FLIP
TMOD
TL0
TL1
TH0
TH1
CKCON
LCD0D0
LCD0D1
LCD0D2
LCD0D3
LCD0D4
LCD0D5
0x0
P1
TCON
0xF
0x0
SFRPAGE
LCD0BUFCN
0x2
0x80
RTC0KEY
P6DRV
0xF
0x88
FLSCL
CLKSEL
0x2
0x90
FLKEY
SFRPGCN
P0
SP
DPL
DPH
PSBANK
SFRNEXT
SFRLAST
PCON
0x2
0xF
Rev. 0.3
229
Si102x/3x
Table 16.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
SFR Page
ADC0AC
0xBA
0x0
88
ADC0CF
0xBC
0x0
ADC0 Configuration
87
ADC0CN
0xE8
ADC0GTH
0xC4
0x0
92
ADC0GTL
0xC3
0x0
92
ADC0H
0xBE
0x0
ADC0 High
91
ADC0L
0xBD
0x0
ADC0 Low
91
ADC0LTH
0xC6
0x0
93
ADC0LTL
0xC5
0x0
93
ADC0MX
0xBB
0x0
ADC0 MUX
96
ADC0PWR
0xBA
0xF
89
ADC0TK
0xBB
0xF
90
AES0BCFG
0xE9
0x2
203
AES0BIN
0xEB
0x2
205
AES0DCFG
0xEA
0x2
204
AES0KIN
0xED
0x2
206
AES0XIN
0xEC
0x2
206
AES0YOUT
0xF5
0x2
AES Y Out
207
CKCON
0x8E
0x0
Clock Control
492
CLKMODE
0xFD
0xF
Clock Mode
269
CLKSEL
0xA9
0x0 and
0xF
Clock Select
298
CPT0CN
0x9B
0x0
Comparator0 Control
106
CPT0MD
0x9D
0x0
107
CPT0MX
0x9F
0x0
113
CPT1CN
0x9A
0x0
Comparator1 Control
108
CPT1MD
0x9C
0x0
109
CPT1MX
0x9E
0x0
114
CRC0AUTO
0x96
0xF
167
CRC0CNT
0x97
0xF
167
CRC0CN
0x92
0xF
CRC0 Control
165
CRC0DAT
0x91
0xF
CRC0 Data
166
CRC0FLIP
0x94
0xF
CRC0 Flip
168
CRC0IN
0x93
0xF
CRC0 Input
166
230
Description
Rev. 0.3
Page
86
Si102x/3x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
SFR Page
Description
CRC1CN
0xBE
0x2
CRC1 Control
173
CRC1IN
0xB9
0x2
CRC1 In
174
CRC1OUTH
0xBB
0x2
175
CRC1OUTL
0xBA
0x2
175
CRC1POLH
0xBD
0x2
174
CRC1POLL
0xBC
0x2
174
DC0CF
0xB2
0x2
DC0 Configuration
281
DC0CN
0xB1
0x2
DC0 Control
280
DC0MD
0xB3
0x2
DC0 Mode
282
DC0RDY
0xFD
0x2
DC0 Ready
283
DEVICEID
0xE9
0xF
Device ID
255
DMA0BUSY
0xD5
0x2
DMA0 Busy
154
DMA0EN
0xD2
0x2
DMA0 Enable
151
DMA0INT
0xD3
0x2
DMA0 Interrupt
152
DMA0MINT
0xD4
0x2
153
DMA0NAOH
0xCD
0x2
159
DMA0NAOL
0xCC
0x2
159
DMA0NBAH
0xCB
0x2
158
DMA0NBAL
0xCA
0x2
158
DMA0NCF
0xC9
0x2
DMA0 Configuration
157
DMA0NMD
0xD6
0x2
156
DMA0NSZH
0xCF
0x2
160
DMA0NSZL
0xCE
0x2
160
DMA0SEL
0xD1
0x2
155
DPH
0x83
121
DPL
0x82
121
EIE1
0xE6
244
EIE2
0xE7
246
EIP1
0xF6
245
EIP2
0xF7
247
EMI0CF
0xAB
0x0
EMIF Configuration
134
EMI0CN
0xAA
0x0
EMIF Control
133
EMI0TC
0xAF
0x0
139
ENC0CN
0xC5
0x2
ENC0 Control
215
Rev. 0.3
Page
231
Si102x/3x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
SFR Page
ENC0H
0xC4
0x2
ENC0 High
216
ENC0L
0xC2
0x2
ENC0 Low
216
ENC0M
0xC3
0x2
ENC0 Middle
216
FLKEY
0xB7
FLSCL
0xB6
0xF
262
FLWR
0xE5
0x0
262
FRBCN
0xB5
0xF
263
IE
0xA8
242
IP
0xB8
243
IREF0CF
0xB9
0xF
111
IREF0CN
0xB9
0x0
110
IT01CF
0xE4
0x0 and
0xF
INT0/INT1 Configuration
249
LCD0BLINK
0x9E
0x2
353
LCD0BUFCF
0xAC
0xF
357
LCD0BUFCN
0x9C
0xF
356
LCD0BUFMD
0xB6
0x2
357
LCD0CF
0xA5
0x2
LCD0 Configuration
355
LCD0CHPCF
0xAD
0x2
356
LCD0CHPCN
0xB5
0x2
355
LCD0CHPMD
0xAE
0x2
356
LCD0CLKDIVH
0xAA
0x2
352
LCD0CLKDIVL
0xA9
0x2
352
LCD0CN
0x9D
0x2
LCD0 Control
344
LCD0CNTRST
0x9C
0x2
LCD0 Contrast
348
LCD0D0
0x89
0x2
LCD0 Data 0
342
LCD0D1
0x8A
0x2
LCD0 Data 1
342
LCD0D2
0x8B
0x2
LCD0 Data 2
342
LCD0D3
0x8C
0x2
LCD0 Data 3
342
LCD0D4
0x8D
0x2
LCD0 Data 4
342
LCD0D5
0x8E
0x2
LCD0 Data 5
342
LCD0D6
0x91
0x2
LCD0 Data 6
342
LCD0D7
0x92
0x2
LCD0 Data 7
342
LCD0D8
0x93
0x2
LCD0 Data 8
342
232
Description
Rev. 0.3
Page
261
Si102x/3x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
SFR Page
Description
LCD0D9
0x94
0x2
LCD0 Data 9
342
LCD0DA
0x95
0x2
LCD0 Data A
342
LCD0DB
0x96
0x2
LCD0 Data B
342
LCD0DC
0x97
0x2
LCD0 Data C
342
LCD0DD
0x99
0x2
LCD0 Data D
342
LCD0DE
0x9A
0x2
LCD0 Data E
342
LCD0DF
0x9B
0x2
LCD0 Data F
342
LCD0MSCF
0xAC
0x2
350
LCD0MSCN
0xAB
0x2
349
LCD0PWR
0xA4
0x2
LCD0 Power
350
LCD0TOGR
0x9F
0x2
354
LCD0VBMCF
0xAF
0x2
357
LCD0VBMCN
0xA6
0x2
351
OSCICL
0xB3
0xF
300
OSCICN
0xB2
0x0
299
OSCXCN
0xB1
0x0
301
P0DRV
0xA4
0xF
373
P0MASK
0xC7
0x0
Port 0 Mask
368
P0MAT
0xD7
0x0
Port 0 Match
368
P0MDIN
0xF1
0x0
372
P0MDOUT
0xA4
0x0
372
P0SKIP
0xD4
0x0
Port 0 Skip
371
P0
0x80
P1DRV
0xA5
0xF
375
P1MASK
0xBF
0x0
Port 1 Mask
369
P1MAT
0xCF
0x0
Port 1 Match
369
P1MDIN
0xF2
0x0
374
P1MDOUT
0xA5
0x0
375
P1SKIP
0xD5
0x0
Port 1 Skip
374
P1
0x90
P2DRV
0xA6
0xF
378
P2MDIN
0xF3
0x0
377
P2MDOUT
0xA6
0x0
377
P2SKIP
0xD6
0x0
Port 2 Skip
376
Rev. 0.3
Page
371
373
233
Si102x/3x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
P2
0xA0
P3DRV
0xA1
0xF
380
P3MDIN
0xF1
0xF
379
P3MDOUT
0xB1
0xF
P3 Mode Out
379
P3
0xB0
P4DRV
0xA2
0xF
382
P4MDIN
0xF2
0xF
381
P4MDOUT
0xF9
0xF
P4 Mode Out
381
P4
0xD9
0xF
Port 4 Latch
380
P5DRV
0xA3
0xF
384
P5MDIN
0xF3
0xF
383
P5MDOUT
0xFA
0xF
P5 Mode Out
383
P5
0xDA
0xF
Port 5 Latch
382
P6DRV
0xAA
0xF
386
P6MDIN
0xF4
0xF
385
P6MDOUT
0xFB
0xF
P6 Mode Out
385
P6
0xDB
0xF
Port 6 Latch
384
P7DRV
0xAB
0xF
387
P7MDOUT
0xFC
0xF
P7 Mode Out
387
P7
0xDC
0xF
Port 7 Latch
386
PC0CMP0H
0xE3
0x2
336
PC0CMP0L
0xE1
0x2
336
PC0CMP0M
0xE2
0x2
336
PC0CMP1H
0xF3
0x2
337
PC0CMP1L
0xF1
0x2
337
PC0CMP1M
0xF2
0x2
337
PC0CTR0H
0xDC
0x2
334
PC0CTR0L
0xDA
0x2
334
PC0CTR0M
0xD8
0x2
334
PC0CTR1H
0xDF
0x2
335
PC0CTR1L
0xDD
0x2
335
PC0DCH
0xFA
0x2
332
PC0DCL
0xF9
0x2
333
PC0HIST
0xF4
0x2
PC0 History
338
234
SFR Page
Description
Rev. 0.3
Page
376
378
Si102x/3x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
SFR Page
PC0INT0
0xFB
0x2
PC0 Interrupt 0
339
PC0INT1
0xFC
0x2
PC0 Interrupt 1
340
PC0MD
0xD9
0x2
PC0 Mode
328
PC0PCF
0xD7
0x2
329
PC0STAT
0xC1
0x2
PC0 Status
331
PC0TH
0xE4
0x2
PC0 Threshold
330
PCA0CN
0xD8
PCA0CPH0
0xFC
0x0
532
PCA0CPH1
0xEA
0x0
532
PCA0CPH2
0xEC
0x0
532
PCA0CPH3
0xEE
0x0
532
PCA0CPH4
0xFE
0x0
532
PCA0CPH5
0xD3
0x0
532
PCA0CPL0
0xFB
0x0
532
PCA0CPL1
0xE9
0x0
532
PCA0CPL2
0xEB
0x0
532
PCA0CPL3
0xED
0x0
532
PCA0CPL4
0xFD
0x0
532
PCA0CPL5
0xD2
0x0
532
PCA0CPM0
0xDA
0x0
530
PCA0CPM1
0xDB
0x0
530
PCA0CPM2
0xDC
0x0
530
PCA0CPM3
0xDD
0x0
530
PCA0CPM4
0xDE
0x0
530
PCA0CPM5
0xCE
0x0
530
0x0
531
PCA0H
Description
Page
527
PCA0L
0xF9
0x0
531
PCA0MD
0xD9
0x0
PCA0 Mode
528
PCA0PWM
0xDF
0x0
529
PCLKACT
0xF5
0xF
267
PCLKEN
0xFE
0xF
268
PCON
0x87
PMU0CF
0xB5
0x0
PMU0 Configuration 0
272
PMU0FL
0xB6
0x0
PMU0 flag
273
Rev. 0.3
275
235
Si102x/3x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
236
Register
Address
SFR Page
PMU0MD
0xB3
0x0
PSBANK
Description
Page
274
0x84
127
PSCTL
0x8F
260
PSW
0xD0
123
REF0CN
0xD1
0x0
102
REG0CN
0xC9
0x0
284
REVID
0xEA
0xF
Revision ID
256
RSTSRC
0xEF
0x0
292
RTC0ADR
0xAC
0x0
RTC0 Address
305
RTC0DAT
0xAD
0x0
RTC0 Data
306
RTC0KEY
0xAE
0x0
RTC0 Key
305
SBUF0
0x99
0x0
415
SCON0
0x98
414
SFRLAST
0x86
227
SFRNEXT
0x85
226
SFRPAGE
0xA7
225
SFRPGCN
0x8E
0xF
224
SMB0ADM
0xF5
0x0
399
SMB0ADR
0xF4
0x0
398
SMB0CF
0xC1
0x0
SMBus0 Configuration
394
SMB0CN
0xC0
SMB0DAT
0xC2
0x0
SMBus0 Data
400
SPI0CFG
0xA1
0x0
SPI0 Configuration
425
SPI0CKR
0xA2
0x0
427
SPI0CN
0xF8
0x0
SPI0 Control
426
SPI0DAT
0xA3
0x0
SPI0 Data
427
SPI1CFG
0xA1
0x2
SPI1 Configuration
438
SPI1CKR
0xA2
0x2
440
SPI1CN
0xF8
0x2
SPI1 Control
439
SPI1DAT
0xA3
0x2
SPI1 Data
440
SP
0x81
122
TCON
0x88
497
TH0
0x8C
0x0
Timer/Counter 0 High
500
TH1
0x8D
0x0
Timer/Counter 1 High
500
Rev. 0.3
396
Si102x/3x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
SFR Page
Description
TL0
0x8A
0x0
Timer/Counter 0 Low
499
TL1
0x8B
0x0
Timer/Counter 1 Low
499
TMOD
0x89
0x0
Timer/Counter Mode
498
TMR2CN
0xC8
TMR2H
0xCD
0x0
Timer/Counter 2 High
506
TMR2L
0xCC
0x0
Timer/Counter 2 Low
506
TMR2RLH
0xCB
0x0
505
TMR2RLL
0xCA
0x0
505
TMR3CN
0x91
0x0
Timer/Counter 3 Control
510
TMR3H
0x95
0x0
Timer/Counter 3 High
512
TMR3L
0x94
0x0
Timer/Counter 3 Low
512
TMR3RLH
0x93
0x0
511
TMR3RLL
0x92
0x0
511
TOFFH
0xBB
0xF
99
TOFFL
0xBD
0xF
99
VDM0CN
0xFF
XBR0
0xE1
0x0 and
0xF
365
XBR1
0xE2
0x0 and
0xF
366
XBR2
0xE3
0x0 and
0xF
367
Rev. 0.3
Page
504
289
237
Si102x/3x
17. Interrupt Handler
The Si102x/3x microcontroller family includes an extended interrupt system supporting multiple interrupt
sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Refer to Table 17.1, Interrupt Summary, on page 240 for a detailed listing of all interrupt sources supported by the device. Refer to the data
sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR or an indirect register. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. If both global interrupts and the specific interrupt source is enabled, a
CPU interrupt request is generated when the interrupt-pending flag is set.
As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Some interrupt-pending flags are automatically cleared by hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
238
Rev. 0.3
Si102x/3x
17.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. If a high priority interrupt preempts a low priority interrupt, the low priority interrupt will finish
execution after the high priority interrupt completes. Each interrupt has an associated interrupt priority bit in
in the Interrupt Priority and Extended Interrupt Priority registers used to configure its priority level. Low priority is the default.
If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both
interrupts have the same priority level, a fixed priority order is used to arbitrate. See Table 17.1 on
page 240 to determine the fixed priority order used to arbitrate between simultaneously recognized interrupts.
Rev. 0.3
239
Si102x/3x
Interrupt Priority
Vector Order
Pending Flag
Cleared by HW?
Interrupt Source
Bit addressable?
Always
Enabled
Always
Highest
Zurücksetzen
0x0000
Top
None
0x0003
IE0 (TCON.1)
EX0 (IE.0)
PX0 (IP.0)
Timer 0 Overflow
0x000B
TF0 (TCON.5)
ET0 (IE.1)
PT0 (IP.1)
0x0013
IE1 (TCON.3)
EX1 (IE.2)
PX1 (IP.2)
Timer 1 Overflow
0x001B
TF1 (TCON.7)
ET1 (IE.3)
PT1 (IP.3)
UART0
0x0023
RI0 (SCON0.0)
TI0 (SCON0.1)
ES0 (IE.4)
PS0 (IP.4)
Timer 2 Overflow
0x002B
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
ET2 (IE.5)
PT2 (IP.5)
SPI0
0x0033
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0
0x003B
SI (SMB0CN.0)
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
SmaRTClock Alarm
0x0043
ALRM (RTC0CN.2)*
EARTC0
(EIE1.1)
PARTC0
(EIP1.1)
0x004B
AD0WINT
(ADC0CN.3)
EWADC0
(EIE1.2)
PWADC0
(EIP1.2)
0x0053
10
AD0INT (ADC0STA.5)
EADC0
(EIE1.3)
PADC0
(EIP1.3)
Programmable Counter
Array
0x005B
11
CF (PCA0CN.7)
CCFn (PCA0CN.n)
EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
Comparator0
0x0063
12
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
ECP0
(EIE1.5)
PCP0
(EIP1.5)
Comparator1
0x006B
13
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
ECP1
(EIE1.6)
PCP1
(EIP1.6)
Timer 3 Overflow
0x0073
14
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
ET3
(EIE1.7)
PT3
(EIP1.7)
0x007B
15
VDDOK (VDM0CN.5)1
VBOK (VDM0CN.2)1
EWARN
(EIE2.0)
PWARN
(EIP2.0)
Port Match
0x0083
16
None
EMAT
(EIE2.1)
PMAT
(EIP2.1)
240
Rev. 0.3
N/A N/A
Enable
Flag
Si102x/3x
Bit addressable?
Cleared by HW?
SmaRTClock Oscillator
Fail
0x008B
17
OSCFAIL
(RTC0CN.5)2
ERTC0F
(EIE2.2)
PFRTC0F
(EIP2.2)
SPI1
0x0093
18
SPIF (SPI1CN.7)
WCOL (SPI1CN.6)
MODF (SPI1CN.5)
RXOVRN (SPI1CN.4)
ESPI1
(EIE2.3)
PSPI1
(EIP2.3)
Pulse Counter
0x009B
19
C0ZF (PC0CN.4)
C1ZF (PC0CN.6)
EPC0
(EIE2.4)
PPC0
(EIP2.4)
DMA0
0x00A3
20
DMAINT0...7
DMAMINT0...7
EDMA0
(EIE2.5)
PDMA0
(EIP2.5)
Encoder0
0x00AB
21
ENCERR(ENCCN.6)
EENC0
(EIE2.6)
PENC0
(EIP2.6)
AES
0x00B3
22
AESDONE
(AESBCF.5)
EAES0
(EIE2.7)
PAES0
(EIP2.7)
Interrupt Source
Interrupt Priority
Vector Order
Pending Flag
Priority
Control
Notes:
1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
Rev. 0.3
241
Si102x/3x
SFR Definition 17.1. IE: Interrupt Enable
Bit
Name
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
242
Rev. 0.3
Si102x/3x
Name
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Unused
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Rev. 0.3
243
Si102x/3x
SFR Definition 17.3. EIE1: Extended Interrupt Enable 1
Bit
Name
ET3
ECP1
ECP0
EPCA0
EADC0
EWADC0
ERTC0A
ESMB0
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Function
ET3
ECP1
ECP0
EPCA0
EADC0
ERTC0A
ESMB0
244
Rev. 0.3
Si102x/3x
Name
PT3
PCP1
PCP0
PPCA0
PADC0
PWADC0
PRTC0A
PSMB0
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Function
PT3
PCP1
PCP0
PPCA0
PADC0
PRTC0A
PSMB0
Rev. 0.3
245
Si102x/3x
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2
Bit
Name
EAES0
EENC0
EDMA0
EPC0
ESPI1
ERTC0F
EMAT
EWARN
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Function
EENC0
EPC0
ESPI1
EMAT
This bit sets the masking of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: Disable the VDD/DC+ Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by VDD/DC+ Supply Monitor.
246
Rev. 0.3
Si102x/3x
Name
PAES0
PENC0
PDMA0
PPC0
PSPI1
PRTC0F
PMAT
PWARN
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
Function
PPC0
PSPI0
Rev. 0.3
247
Si102x/3x
17.6. External Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section 33.1. Timer 0 and Timer 1 on page 493) select level or
edge sensitive. The table below lists the possible configurations.
IT0
IN0PL
INT0 Interrupt
IT1
IN1PL
INT1 Interrupt
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 17.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section 27.3. Priority Crossbar
Decoder on page 362 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
248
Rev. 0.3
Si102x/3x
Name
IN1PL
IN1SL[2:0]
IN0PL
IN0SL[2:0]
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
Name
IN1PL
6:4
2:0
Function
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
Rev. 0.3
249
Si102x/3x
18. Flash Memory
On-chip, re-programmable flash memory is included for program code and non-volatile data storage. The
flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by software using the MOVX write instruction. Once cleared to logic 0, a flash bit must be erased to set it back to
logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and
erase operations are automatically timed by hardware for proper execution; data polling to determine the
end of the write/erase operations is not required. Code execution is stalled during flash write/erase operations. Refer to Table 4.8 for complete flash memory electrical characteristics.
Rev. 0.3
Si102x/3x
9. Restore previous interrupt state.
Steps 47 must be repeated for each 1024-byte page to be erased.
Notes:
1. Flash security settings may prevent erasure of some flash pages, such as the reserved area and the page
containing the lock bytes. For a summary of flash security settings and restrictions affecting flash erase
operations, please see Section 18.3. Security Options on page 253.
2. 8-bit MOVX instructions cannot be used to erase or write to flash memory at addresses higher than 0x00FF.
Rev. 0.3
251
Si102x/3x
18.1.4. Flash Write Optimization
The flash write procedure includes a block write option to optimize the time to perform consecutive byte
writes. When block write is enabled by setting the CHBLKW bit (FLRBCN.0), writes to flash will occur in
blocks of 4 bytes and require the same amount of time as a single byte write. This is performed by caching
the bytes whose address end in 00b, 01b, and 10b that is written to flash and then committing all four bytes
to flash when the byte with address 11b is written. When block writes are enabled, if the write to the byte
with address 11b does not occur, the other three data bytes written is not committed to flash.
A write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in flash. The Flash Block to be programmed should be erased before a new value is written.
The recommended procedure for writing a 4-byte flash block is as follows:
1. Save current interrupt state and disable interrupts.
2. Set the CHBLKW bit (register FLRBCN).
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. If writing to an address in Banks 1, 2, or 3, set the COBANK[1:0] bits (register PSBANK) for the
appropriate bank
6. Write the first key code to FLKEY: 0xA5.
7. Write the second key code to FLKEY: 0xF1.
8. Using the MOVX instruction, write the first data byte to the desired location within the 1024-byte
sector whose address ends in 00b.
9. Write the first key code to FLKEY: 0xA5.
10. Write the second key code to FLKEY: 0xF1.
11. Using the MOVX instruction, write the second data byte to the next higher flash address ending in
01b.
12. Write the first key code to FLKEY: 0xA5.
13. Write the second key code to FLKEY: 0xF1.
14. Using the MOVX instruction, write the third data byte to the next higher flash address ending in 10b.
15. Write the first key code to FLKEY: 0xA5.
16. Write the second key code to FLKEY: 0xF1.
17. Using the MOVX instruction, write the final data byte to the next higher flash address ending in 11b.
18. Clear the PSWE bit.
19. Clear the CHBLKW bit.
20. Restore previous interrupt state.
Steps 517 must be repeated for each flash block to be written.
Notes:
1. Flash security settings may prevent writes to some areas of flash, such as the reserved area. For a summary of
flash security settings and restrictions affecting flash write operations, please see Section 18.3. Security
Options on page 253.
2. 8-bit MOVX instructions cannot be used to erase or write to flash memory at addresses higher than 0x00FF.
252
Rev. 0.3
Si102x/3x
18.2. Non-volatile Data Storage
The flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
11111101b
ones Complement:
00000010b
Reserved Area
Locked when
any other FLASH
pages are locked
Lock Byte
Lock Byte Page
Rev. 0.3
253
Si102x/3x
The level of flash security depends on the flash access method. The three flash access methods that can
be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 18.1 summarizes the flash security
features of the Si102x/3x devices.
C2 Debug
Interface
a locked page
Permitted
Permitted
Permitted
Not Permitted
Permitted
Permitted
Permitted
Permitted
Not Permitted
Permitted
Permitted
Permitted
Permitted
Not Permitted
Permitted
Permitted
Not Permitted
Not Permitted
Not Permitted
C2 Device EraseErases all flash pages including the page containing the Lock Byte.
Flash Error ResetNot permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after
reset).
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
254
Rev. 0.3
Si102x/3x
18.4. Determining the Device Part Number at Run Time
In many applications, user software may need to determine the MCU part number at run time in order to
determine the hardware capabilities. The part number can be determined by reading the value of the
DEVICEID Special Function Register.
0xE0Si1020
0xE1Si1021
0xE2Si1022
0xE3Si1023
0xE4Si1024
0xE5Si1025
0xE6Si1026
0xE7Si1027
0xE8Si1030
0xE9Si1031
0xEASi1032
0xEBSi1033
0xECSi1034
0xEDSi1035
0xEESi1036
0xEFSi1037
Name
DEVICEID[7:0]
Typ
R/W
Zurücksetzen
DEVICEID[7:0]
Function
Device Identification.
These bits contain a value that can be decoded to determine the device part
number.
Rev. 0.3
255
Si102x/3x
SFR Definition 18.2. REVID: Revision Identification
Bit
Name
REVID[7:0]
Typ
R/W
Zurücksetzen
REVID[7:0]
Function
Revision Identification.
These bits contain a value that can be decoded to determine the silicon
revision. For example, 0x00 for Rev A and 0x01 for Rev B, etc.
256
Rev. 0.3
Si102x/3x
On Si102x/3x devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a reset
source inside the functions that write and erase flash memory. The VDD Monitor enable instructions
should be placed just after the instruction to set PSWE to a 1, but before the flash write or erase
operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas to
check are initialization code which enables other reset sources, such as the Missing Clock Detector
or Comparator, for example, and instructions which force a Software Reset. A global search on
"RSTSRC" can quickly verify this.
Rev. 0.3
257
Si102x/3x
18.5.2. PSWE Maintenance
1. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should
be exactly one routine in code that sets PSWE to a 1 to write flash bytes and one routine in code that
sets both PSWE and PSEE both to a 1 to erase flash pages.
2. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can
be found in AN201: Writing to Flash from Firmware," available from the Silicon Laboratories web
site.
3. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
reset to 0. Any interrupts posted during the flash write or erase operation will be serviced in priority
order after the flash operation has been completed and interrupts have been re-enabled by software.
4. Make certain that the flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different
memory areas.
5. Add address bounds checking to the routines that write or erase flash memory to ensure that a
routine called with an illegal address does not result in modification of the flash.
18.5.3. System Clock
1. If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
2. If operating from the external oscillator, switch to the internal oscillator during flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the flash operation has completed.
Additional flash recommendations and example code can be found in AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
258
Rev. 0.3
Si102x/3x
18.6. Minimizing Flash Read Current
The flash memory in the Si102x/3x devices is responsible for a substantial portion of the total digital supply
current when the device is executing code. Below are suggestions to minimize flash read current.
1. Use idle, low power idle, suspend, or sleep modes while waiting for an interrupt, rather than polling
the interrupt flag. Idle mode and low power idle mode is particularly well-suited for use in
implementing short pauses, since the wake-up time is no more than three system clock cycles. See
the Power Management chapter for details on the various low-power operating modes.
2. The flash memory is organized in 4-byte words starting with a byte with address ending in 00b and
ending with a byte with address ending in 11b. A 4-byte pre-fetch buffer is used to read 4 bytes of
flash in a single read operation. Short loops that straddle word boundaries or have an instruction byte
with address ending in 11b should be avoided when possible. If a loop executes in 20 or more clock
cycles, any resulting increase in operating current due to mis-alignment will be negligible.
3. To minimize the power consumption of small loops, it is best to locate them such that the number of
4-byte words to be fetched from flash is minimized. Consider a 2-byte, 3-cycle loop (e.g., SJMP $, or
while(1);). The flash read current of such a loop will be minimized if both address bytes are contained
in the first 3 bytes of a single 4-byte word. Such a loop should be manually located at an address
ending in 00b or the number of bytes in the loop should be increased (by padding with NOP
instructions) in order to minimize flash read current.
Rev. 0.3
259
Si102x/3x
SFR Definition 18.3. PSCTL: Program Store R/W Control
Bit
Name
PSEE
PSWE
Typ
R/W
R/W
Zurücksetzen
Unused
PSEE
Function
PSWE
260
Rev. 0.3
Si102x/3x
Name
FLKEY[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
261
Si102x/3x
SFR Definition 18.5. FLSCL: Flash Scale
Bit
Name
BYPASS
Typ
R/W
Zurücksetzen
Function
Reserved
Always Write to 0.
BYPASS
5:0
Reserved
Note: Operations which clear the BYPASS bit do not need to be immediately followed by a benign 3-byte instruction.
For code compatibility with C8051F930/31/20/21 devices, a benign 3-byte instruction whose third byte is a
don't care should follow the clear operation. See the C8051F93x-C8051F92x data sheet for more details.
Name
FLWR[7:0]
Typ
Zurücksetzen
Function
262
Rev. 0.3
Si102x/3x
Name
FRBD
CHBLKW
Typ
R/W
R/W
Zurücksetzen
Unused
FRBD
CHBLKW
Function
Rev. 0.3
263
Si102x/3x
19. Power Management
Si102x/3x devices support 6 power modes: Normal, Idle, Stop, Low Power Idle, Suspend, and Sleep. The
power management unit (PMU0) allows the device to enter and wake-up from the available power modes.
A brief description of each power mode is provided in Table 19.1. Detailed descriptions of each mode can
be found in the following sections.
Description
Wake-Up
Sources
Power Savings
K.A.
Excellent MIPS/mW
Normal
Idle
Any Interrupt.
Good
No Code Execution
Stop
Any Reset.
Good
No Code Execution
Precision Oscillator Disabled
Low Power
Idle
Any Interrupt
Very Good
No Code Execution
Selective Clock Gating
Suspend
SmaRTClock,
Port Match,
Comparator0,
RST pin,
Pulse Counter
VBAT Monitor.
Very Good
No Code Execution
All Internal Oscillators Disabled
System Clock Gated
Sleep
SmaRTClock,
Port Match,
Comparator0,
RST pin,
Pulse Counter
VBAT Monitor.
Excellent
Power Supply Gated
All Oscillators except SmaRTClock Disabled
In battery powered systems, the system should spend as much time as possible in sleep mode in order to
preserve battery life. When a task with a fixed number of clock cycles needs to be performed, the device
should switch to normal mode, finish the task as quickly as possible, and return to sleep mode. Idle mode,
low power idle mode, and suspend mode provide a very fast wake-up time; however, the power savings in
these modes will not be as much as in sleep Mode. Stop Mode is included for legacy reasons; the system
will be more power efficient and easier to wake up when idle, low power idle, suspend, or sleep mode is
used.
Although switching power modes is an integral part of power management, enabling/disabling individual
peripherals as needed will help lower power consumption in all power modes. Each analog peripheral can
be disabled when not in use or placed in a low power mode. Digital peripherals such as timers or serial
busses draw little power whenever they are not in use. Digital peripherals draw no power in Sleep Mode.
264
Rev. 0.3
Si102x/3x
19.1. Normal Mode
The MCU is fully functional in Normal Mode. Figure 19.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBAT, DCOUT, and the
1.8 V internal core supply (output of VREG0). All analog peripherals are directly powered from the VBAT
pin. All digital peripherals and the CIP-51 core are powered from the 1.8 V internal core supply (output of
VREG0). The Pulse counter, RAM, PMU0, and the SmaRTClock are powered from the internal core supply
when the device is in normal mode. The input to VREG0 is controlled by software and depends on the settings of the power select switch. The power select switch may be configured to power VREG0 from VBAT
or from the output of the DC0.
IND
VDC
VBAT
1.8 to 3.6 V
VIO
VBATDC
GNDDC
1.9 V
DC0
Buck
Converter
Analog Peripherals
Power
Select
VREF
A
M
U
X
ADC
Pulse
Counter
PMU0
TEMP
SENSOR
Sleep
RAM
LCD
+
VOLTAGE
COMPARATORS
VIORF
VREG0
Digital Peripherals
Active/Idle/ 1.8 V
Stop/Suspend
SmaRTClock
CIP-51
Core
Flash
UART
AES
SPI
Timers
SMBus
Rev. 0.3
265
Si102x/3x
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section 22.6. PCA Watchdog Timer
Reset on page 290 for more information on the use and configuration of the WDT.
System
Clock
SmaRTClock
Pulse Counter
PMU0
CPU
Timer 0, 1, 2
CRC0
ADC0
PCA0
UART0
Timer 3
SPI0
SMBus
266
Rev. 0.3
Si102x/3x
Name
PCLKACT[3:0]
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
Unused
R/W
0
Function
PCLKACT3 Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to the SmaRTClock, Pulse Counter, and PMU0 revert to the PCLKEN setting in Low Power Active Mode.
1: Enable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Active
Mode.
PCLKACT2 Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to Timer 0, Timer 1, Timer 2, and CRC0 revert to the PCLKEN setting in Low
Power Active Mode.
1: Enable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Active Mode.
PCLKACT1 Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to ADC0 and PCA0 revert to the PCLKEN setting in Low Power Active
Mode.
1: Enable clocks to ADC0 and PCA0 in Low Power Active Mode.
PCLKACT0 Clock Enable Controls for Peripherals in Low Power Active Mode.
0: Clocks to UART0, Timer 3, SPI0, and the SMBus revert to the PCLKEN setting in
Low Power Active Mode.
1: Enable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Active
Mode.
Rev. 0.3
267
Si102x/3x
SFR Definition 19.2. PCLKEN: Peripheral Clock Enable
Bit
Name
Type
PCLKEN[3:0]
R/W
R/W
R/W
R/W
R/W
Reset
SFR Page = 0xF; SFR Address = 0xFE
Bit
Name
7:4
Unused
Function
PCLKEN3 Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Idle
Mode.
1: Enable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Idle
Mode.
PCLKEN2 Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Idle Mode.
1: Enable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Idle Mode.
PCLKEN1 Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disableclocks to ADC0 and PCA0 in Low Power Idle Mode.
1: Enable clocks to ADC0 and PCA0 in Low Power Idle Mode.
PCLKEN0 Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Idle Mode.
1: Enable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Idle Mode.
268
Rev. 0.3
Si102x/3x
Name
Reserved
Reserved
Reserved
Reserved
Reserved
LPMEN
Reserved
Reserved
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Reserved
LPMEN
Reserved
Reserved
Function
Rev. 0.3
269
Si102x/3x
19.5. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. The system clock source must be set to the low power internal oscillator or the precision oscillator prior to entering Suspend Mode. All digital logic (timers, communication peripherals, interrupts, CPU, etc.) stops functioning until one of the enabled wake-up sources occurs.
The following wake-up sources can be configured to wake the device from Suspend Mode:
Note: Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the PMU0CF wakeup flags. All flags will read back a value of '0' during the first two system clocks following a wake-up from
suspend mode.
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 s. The PMU0CF register may be checked to determine if the wakeup was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 kW
pullup resistor to VDD is recommend for RST to prevent noise glitches from waking the device.
270
Rev. 0.3
Si102x/3x
The following wake-up sources can be configured to wake the device from sleep mode:
Rev. 0.3
271
Si102x/3x
SFR Definition 19.4. PMU0CF: Power Management Unit Configuration1,2,3
Bit
Name
SLEEP
SUSPEND
CLEAR
RSTWK
RTCFWK
RTCAWK
PMATWK
CPT0WK
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
Varies
Varies
Varies
Varies
Varies
SLEEP
SUSPEND
Write
Lesen
K.A.
K.A.
CLEAR
K.A.
RSTWK
K.A.
RTCFWK
SmaRTClock Oscillator
Fail Wake-up Source
Enable and Flag
0: Disable wake-up on
SmaRTClock Osc. Fail.
1: Enable wake-up on
SmaRTClock Osc. Fail.
RTCAWK
SmaRTClock Alarm
Wake-up Source Enable
and Flag
0: Disable wake-up on
SmaRTClock Alarm.
1: Enable wake-up on
SmaRTClock Alarm.
Set to 1 if a SmaRTClock
Alarm has occurred.
PMATWK
0: Disable wake-up on
Port Match Event.
1: Enable wake-up on
Port Match Event.
CPT0WK
Comparator0 Wake-up
Source Enable and Flag
0: Disable wake-up on
Comparator0 rising edge.
1: Enable wake-up on
Comparator0 rising edge.
Set to 1 if Comparator0
rising edge has occurred.
Notes:
1. Read-modify-write operations (ORL, ANL, etc.) should not be used on this register. Wake-up sources must
be re-enabled each time the SLEEP or SUSPEND bits are written to 1.
2. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in Suspend or Sleep
Mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
3. PMU0 requires two system clocks to update the wake-up source flags after waking from Suspend mode. The
wake-up source flags will read 0 during the first two system clocks following the wake from Suspend mode.
272
Rev. 0.3
Si102x/3x
Name
BATMWK
Reserved
PC0WK
Typ
R/W
R/W
R/W
Zurücksetzen
Varies
Unused
Write
Lesen
Unused
Dont Care.
0000000
BATMWK
0: Disable wake-up on
Set to 1 if VBAT Monitor
VBAT Monitor event.
event caused the last
1: Enable wake-up on CS0 wake-up.
event.
Reserved
Reserved
Must write 0.
CS0WK
0: Disable wake-up on
Set to 1 if PC0 event
PC0 event.
caused the last wake-up.
1: Enable wake-up on PC0
event.
Always reads 0.
Notes:
1. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in suspend or sleep
mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
2. PMU0 requires two system clocks to update the wake-up source flags after waking from suspend mode. The
wake-up source flags will read 0 during the first two system clocks following the wake from suspend mode.
Rev. 0.3
273
Si102x/3x
SFR Definition 19.6. PMU0MD: Power Management Unit Mode
Bit
Name RTCOE
WAKEOE
MONDIS
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
RTCOE
Function
WAKEOE
MONDIS
4:0
274
Unused
Rev. 0.3
Si102x/3x
Name
GF[4:0]
PWRSEL
STOP
IDLE
Typ
R/W
R/W
Zurücksetzen
GF[5:0]
PWRSEL
1
0
Write
Lesen
Power Select
STOP
K.A.
IDLE
K.A.
Rev. 0.3
275
Si102x/3x
20. On-Chip DC-DC Buck Converter (DC0)
Si102x/3x devices include an on-chip step down dc-dc converter to efficiently utilize the energy stored in
the battery, thus extending the operational life time. The dc-dc converter is a switching buck converter with
an input supply of 1.8 to 3.8 V and an output that is programmable from 1.8 to 3.5 V in steps of 0.1 V. The
battery voltage should be at least 0.4 V higher than the programmed output voltage. The programmed output voltage has a default value of 1.9 V. The dc-dc converter can supply up to 250 mW. The dc-dc converter can be used to power the MCU and/or external devices in the system (e.g., an RF transceiver).
The dc-dc converter has a built in voltage reference and oscillator, and will automatically limit or turn off the
switching activity in case the peak inductor current rises beyond a safe limit or the output voltage rises
above the programmed target value. This allows the dc-dc converter output to be safely overdriven by a
secondary power source (when available) in order to preserve battery life. When enabled, the dc-dc converter can source current into the output capacitor, but cannot sink current. The dc-dc converters settings
can be modified using SFR registers described in Section 20.8.
Figure 20.1 shows a block diagram of the buck converter.
DC/DC Converter
VBAT
IND
M1
VBATDC
4.7 uF
+ 0.1uF
+ 0.01uF
0.56 uH
MBYP
VDC
Control Logic
SFR
Control
Voltage
Reference
2.2 uF
+0.1uF
+0.01uF
Local
Oscillator
GNDDC
GND
276
Rev. 0.3
Iload
Si102x/3x
20.1. Startup Behavior
The dc-dc converter is enabled by setting bit DC0EN (DC0MD.0) to logic 1. When first enabled, the M1
switch turns on and continues to supply current into the output capacitor through the inductor until the VDC
output voltage reaches the programmed level set by by the VSEL bits (DC0CF.[6:3]).
The peak transient current in the inductor is limited for safe operation. The peak inductor current is programmable using the ILIMIT bits (DC0MD.[6:4]). The peak inductor current, size of the output capacitor
and the amount of dc load current present during startup will determine the length of time it takes to charge
the output capacitor. The RDYH and RDYL bits (DC0RDY.7 and DC0DRY.6) may be used to determine
when the output voltage is within approximately 100 mV of the programmed voltage.
In order to ensure reliable startup of the dc-dc converter, the following restrictions have been imposed:
The maximum dc load current allowed during startup is given in Table 4.20 on page 69. If the dc-dc
converter is powering external sensors or devices through the VDC pin, then the current supplied to
these sensors or devices is counted towards this limit. The in-rush current into capacitors does not
count towards this limit.
The maximum total output capacitance is given in Table 4.20 on page 69. This value includes the
required 2.2 F ceramic output capacitor and any additional capacitance connected to the VDC pin.
The peak inductor current limit is programmable by software as shown in Table 20.1. Limiting the peak
inductor current can allow the dc-dc converter to start up using a high impedance power source (such as
when a battery is near its end of life) or allow inductors with a low current rating to be utilized. By default,
the peak inductor current is set to 500 mA.
.
001
200
010
300
011
400
100
500
101
600
The peak inductor current is dependent on several factors including the dc load current and can be estimated using following equation:
Rev. 0.3
277
Si102x/3x
20.2. High Power Applications
The dc-dc converter is designed to provide the system with 150 mW of output power. At high output power,
an inductor with low DC resistance should be chosen in order to minimize power loss and maximize efficiency. At load currents higher than 20 mA, efficiency improvents may be achieved by placing a schottky
diode (e.g. MBR052LT1) between the IND pin and GND in parallel with the internal diode (see
Figure 20.1).
Place the input capacitor stack as close as possible to the VBATDC pin. The smallest capacitors in the
stack should be placed closest to the VBATDC pin.
Place the output capacitor stack as close as possible to the VDC pin. The smallest capacitors in the
stack should be placed closest to the VDC pin.
Minimize the trace length between the IND pin, the inductor, and the VDC pin.
278
Rev. 0.3
Si102x/3x
20.7. Bypass Mode
The dc-dc converter has a bypass switch (MBYP), see Figure 20.1, which allows the output voltage (VDC)
to be directly tied to the input supply (VBATDC), bypassing the dc-dc converter. The bypass switch may be
used independently from the dc-dc converter. For example, applications that need to power the VDC supply in the lowest power Sleep mode can turn on the bypass switch prior to turning off the dc-dc converter in
order to avoid powering down the external circuitry connected to VDC.
There are two ways to close the bypass switch. Using the first method, Forced Bypass Mode, the FORBYP
bit is set to a logic 1 forcing the bypass switch to close. Clearing the FORBYP bit to logic 0 will allow the
switch to open if it is not being held closed using Automatic Bypass Mode.
The Automatic Bypass Mode, enabled by setting the AUTOBYP to logic 1, closes the bypass switch when
the difference between VBATDC and the programmed output voltage is less than approximately 0.4 V.
Once the difference exceeds approximately 0.5 V, the bypass switch is opened unless being held closed
by Forced Bypass Mode. In most systems, Automatic Bypass Mode will be left enabled, and the Forced
Bypass Mode will be used to close the switch as needed by the system.
Rev. 0.3
279
Si102x/3x
SFR Definition 20.1. DC0CN: DC-DC Converter Control
Bit
Name
CLKSEL
Typ
R/W
Zurücksetzen
AD0CKINV
CLKINV
ILIMIT
R/W
R/W
R/W
R/W
CLKDIV[1:0]
MIN_PW[1:0]
R/W
1
Name
CLKSEL
Function
DC-DC Converter Clock Source Select.
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
6:5
CLKINV
SYNC
1:0
280
Rev. 0.3
Si102x/3x
Name
BYPASS
VSEL[3:0]
OSCDIS
Typ
R/W
R/W
Zurücksetzen
BYPASS
SWSEL[1:0]
Function
6:3
VSEL[3:0]
VSEL[2:0]
1:0
Rev. 0.3
281
Si102x/3x
SFR Definition 20.3. DC0MD: DC-DC Converter Mode
Bit
Name Reserved
Type
R/W
Zurücksetzen
ILIMIT
Reserved
6:4
ILIMIT
R/W
R/W
FORBYP
AUTOBYP
Reserved
DC0EN
282
Rev. 0.3
DC0EN
R/W
Function
R/W
0
R/W
1
Si102x/3x
Name
RDYH
RDYL
Reserved
Typ
R/W
Zurücksetzen
RDYH
Function
RDYL
5:0
Reserved
Rev. 0.3
283
Si102x/3x
21. Voltage Regulator (VREG0)
Si102x/3x devices include an internal voltage regulator (VREG0) to regulate the internal core supply to
1.8 V from a VDD/DC+ supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are specified in the Electrical Specifications chapter.
The REG0CN register allows the Precision Oscillator Bias to be disabled, reducing supply current in all
non-sleep power modes. This bias should only be disabled when the precision oscillator is not being used.
The internal regulator (VREG0) is disabled when the device enters sleep mode and remains enabled when
the device enters suspend mode. See Section 19. Power Management on page 264 for complete details
about low power modes.
Name
OSCBIAS
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Bit
7:5
4
Name
Function
3:0
284
Rev. 0.3
Si102x/3x
22. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
Supply
Monitor
+
-
VDC
VBAT
VBAT
Enable
switch
Comparator 0
+
-
SmaRTClock
(wired-OR)
RST
'0'
Enable
C0RSEF
RTC0RE
Missing
Clock
Detector
(oneshot)
EN
Reset
Funnel
PCA
WDT
(Software Reset)
SWRSF
EN
MCD
Enable
Px.x
+
-
System
Clock
Illegal Flash
Operation
WDT
Enable
Px.x
Power On
Reset
Supply
Monitor
CIP-51
Microcontroller
Core
System Reset
System Reset
Power Management
Block (PMU0)
Power-On Reset
Reset
Extended Interrupt
Handler
Rev. 0.3
285
Si102x/3x
22.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin voltage tracks the supply voltage
(through a weak pull-up) until the device is released from reset. After the supply settles above VPOR, a
delay occurs before the device is released from reset; the delay decreases as the supply ramp time
increases (ramp time is defined as how fast the supply ramps from 0 V to VPOR). Figure 22.2 plots the
power-on and supply monitor reset timing. For valid ramp times (less than 3 ms), the power-on reset delay
(TPORDelay) is typically 7 ms (VDD = 1.8 V) or 15 ms (VDD = 3.6 V).
Note: The maximum supply ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before the supply reaches the VPOR level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
volts
The POR supply monitor will continue to monitor the VBAT supply, even in Sleep Mode, to reset the system if the supply voltage drops below VPOR. It can be disabled to save power by writing 1 to the MONDIS
(PMU0MD.5) bit. When the POR supply monitor is disabled, all reset sources will trigger a full POR and will
re-enable the POR supply monitor.
Supply voltage
Su
pp
ly
Vo
lt
ag
e
VPOR
See specification
table for min/max
voltages.
Logic HIGH
RST
TPORDelay
TPORDelay
Logic LOW
Power-On
Reset
Power-On
Reset
286
Rev. 0.3
Si102x/3x
22.2. Power-Fail Reset
Si102x/3x devices have two Active Mode Supply Monitors that can hold the system in reset if the supply
voltage drops below VRST. The first of the two identical supply monitors is connected to the output of the
supply select switch (which chooses the VBAT or VDC pin as the source of the digital supply voltage) and
is enabled and selected as a reset source after each power-on or power-fail reset. This supply monitor will
be referred to as the digital supply monitor. The second supply monitor is connected directly to the VBAT
pin an is disabled after each power-on or power-fail reset. This supply monitor will be referred to as the
analog supply monitor. The analog supply monitor should be enabled any time the supply select switch is
set to the VDC pin to ensure that the VBAT supply does not drop below VRST .
When enabled and selected as a reset source, any power down transition or power irregularity that causes
the monitored supply voltage to drop below VRST will cause the RST pin to be driven low and the CIP-51
will be held in a reset state (see Figure 22.2). When the supply voltage returns to a level above VRST, the
CIP-51 will be released from the reset state.
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the digital supply monitor is enabled and selected as a reset source. The enable state of either supply monitor and its selection as
a reset source is only altered by power-on and power-fail resets. For example, if the supply monitor is deselected as a reset source and disabled by software, then a software reset is performed, the supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the batterys usable
life if the device is placed in Sleep Mode prior to a power-fail reset occurring. When the device is in Sleep
Mode, the power-fail reset is automatically disabled, both active mode supply monitors are turned off, and
the contents of RAM are preserved as long as the supply does not fall below VPOR. A large capacitor can
be used to hold the power supply voltage above VPOR while the user is replacing the battery. Upon waking
from Sleep mode, the enable and reset source select state of the VDD supply monitor are restored to the
value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the supply falls below the VWARN threshold. The VDDOK bit can be configured to generate an interrupt.
Each of the active mode supply montiors have their independent VDDOK and VWARN flags. See Section
17. Interrupt Handler on page 238 for more details.
Important Note: To protect the integrity of Flash contents, the active mode supply monitor(s) must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the digital supply monitor is not enabled, any erase or write performed on Flash memory will
cause a Flash Error device reset.
Rev. 0.3
287
Si102x/3x
Important Notes:
The Power-on Reset (POR) delay is not incurred after a supply monitor reset. See Section 4. Electrical
Characteristics on page 50 for complete electrical characteristics of the active mode supply monitors.
Software should take care not to inadvertently disable the supply monitor as a reset source when
writing to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC
should explicitly set PORSF to 1 to keep the supply monitor enabled as a reset source.
The supply monitor must be enabled before selecting it as a reset source. Selecting the supply monitor
as a reset source before it has stabilized may generate a system reset. In systems where this reset
would be undesirable, a delay should be introduced between enabling the supply monitor and selecting
it as a reset source. See Section 4. Electrical Characteristics on page 50 for minimum supply monitor
turn-on time. No delay should be introduced in systems where software contains routines that
erase or write Flash memory. The procedure for enabling the VDD supply monitor and selecting it as a
reset source is shown below:
1. Enable the Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the Supply Monitor to stabilize (optional).
3. Select the Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
288
Rev. 0.3
Si102x/3x
Name
VDMEN
VDDSTAT
VDDOK
VDDOKIE
VBMEN
VBSTAT
VBOK
VBOKIE
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
Varies
Varies
VDMEN
Function
VDDSTAT
VDDOK
VDDOKIE
VBMEN
VBSTAT
VBOK
VBOKIE
Rev. 0.3
289
Si102x/3x
22.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 4.6 for complete RST pin specifications. The external reset remains functional even when the device is in the low power suspend and
sleep modes. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
290
Rev. 0.3
Si102x/3x
22.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the Lock Byte address.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
18.3. Security Options on page 253).
A Flash write or erase is attempted while the VDD Monitor is disabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
Rev. 0.3
291
Si102x/3x
SFR Definition 22.2. RSTSRC: Reset Source
Bit
Name
RTC0RE
FERROR
C0RSEF
SWRSF
WDTRSF
MCDRSF
PORSF
PINRSF
Typ
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Write
Lesen
0: Disable SmaRTClock
Set to 1 if SmaRTClock
as a reset source.
alarm or oscillator fail
1: Enable SmaRTClock as caused the last reset.
a reset source.
K.A.
SWRSF
Set to 1 if Flash
read/write/erase error
caused the last reset.
PORSF
Power-On / Power-Fail
Reset Flag, and Power-Fail
Reset Enable.
0: Disable the VDD Supply Set to 1 anytime a powerMonitor as a reset source. on or VDD monitor reset
2
1: Enable the VDD Supply occurs.
Monitor as a reset
source.3
PINRSF
K.A.
Notes:
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD Supply Monitor is stabilized may generate a system reset.
292
Rev. 0.3
Si102x/3x
23. Clocking Sources
Si102x/3x devices include a programmable precision internal oscillator, an external oscillator drive circuit,
a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 23.1. The external oscillator can be configured using the OSCXCN register. The low power internal
oscillator is automatically enabled and disabled when selected and deselected as a clock source. SmaRTClock operation is described in the SmaRTClock oscillator chapter.
The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low
power internal oscillator, low power internal oscillator divided by 8, or SmaRTClock oscillator. The global
clock divider can generate a system clock that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected
input clock source. Oscillator electrical specifications can be found in the Electrical Specifications Chapter.
OSCICL
OSCICN
CLKSEL
VDD
XTAL2
CLKSL1
CLKSL0
CLKRDY
CLKDIV2
CLKDIV1
CLKDIV0
Option 3
IOSCEN
IFRDY
Option 2
XTAL2
EN
Precision
Internal Oscillator
Option 1
CLKRDY
XTAL1
External Oscillator
External
Oscillator
Drive Circuit
10M
SYSCLK
XTAL2
Option 4
XTAL2
Clock Divider
XFCN2
XFCN1
XFCN0
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
SmaRTClock Oscillator
Low Power
Internal Oscillator
SmaRTClock
Oscillator
OSCXCN
Rev. 0.3
293
Si102x/3x
23.1. Programmable Precision Internal Oscillator
All Si102x/3x devices include a programmable precision internal oscillator that may be selected as the system clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Section 4. Electrical Characteristics on page 50 for complete oscillator specifications.
The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency is
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 384
(63.8 kHz using the factory calibration). The deviation from the nominal oscillator frequency is +0%, 1.6%,
and the step size is typically 0.26% of the nominal frequency. When using this mode, the typical average
oscillator frequency is lowered from 24.5 MHz to 24.3 MHz.
294
Rev. 0.3
Si102x/3x
15 pF
XTAL1
10 Mohm
25 MHz
XTAL2
15 pF
Figure 23.2. 25 MHz External Crystal Example
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by software for Crystal Oscillator Mode or Crystal Oscillator Mode with divide by 2 stage. The divide by 2 stage ensures that the
clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator Frequency Control value (XFCN) must also be specified based on the crystal frequency. The selection should be based on
Table 23.1. For example, a 25 MHz crystal requires an XFCN setting of 111b.
Crystal Frequency
Bias Current
000
f 20 kHz
0.5 A
001
20 kHz f 58 kHz
1.5 A
010
4.8 A
011
14 A
28 A, f = 400 kHz
100
40 A
71 A, f = 400 kHz
101
120 A
110
550 A
940 A, f = 8 MHz
111
2.6 mA
When the crystal oscillator is first enabled, the external oscillator valid detector allows software to determine when the external system clock has stabilized. Switching to the external oscillator before the crystal
oscillator has stabilized can result in unpredictable behavior. The recommended procedure for starting the
crystal is as follows:
1. Configure XTAL1 and XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
3. Poll for XTLVLD => 1.
4. Switch the system clock to the external oscillator.
Rev. 0.3
295
Si102x/3x
23.3.2. External RC Mode
If an RC network is used as the external oscillator, the circuit should be configured as shown in
Figure 23.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured for
analog I/O with the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The resistor should be no smaller than
10 k. The oscillation frequency can be determined by the following equation:
3
1.23 10
f = ------------------------RC
where
f = frequency of clock in MHzR = pull-up resistor value in k
VDD = power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register,
first select the RC network value to produce the desired frequency of oscillation. For example, if the frequency desired is 100 kHz, let R = 246 k and C = 50 pF:
3
1.23 10
1.23 10
f = ------------------------- = ------------------------- = 100 kHz
RC
246 50
where
f = frequency of clock in MHz
VDD = power supply voltage in Volts
Approximate
Frequency Range (RC
and C Mode)
K Factor (C Mode)
000
f 25 kHz
K Factor = 0.87
3.0 A, f = 11 kHz, C = 33 pF
001
25 kHz f 50 kHz
K Factor = 2.6
5.5 A, f = 33 kHz, C = 33 pF
010
K Factor = 7.7
13 A, f = 98 kHz, C = 33 pF
011
K Factor = 22
32 A, f = 270 kHz, C = 33 pF
100
K Factor = 65
82 A, f = 310 kHz, C = 46 pF
101
K Factor = 180
110
K Factor = 664
111
K Factor = 1590
When the RC oscillator is first enabled, the external oscillator valid detector allows software to determine
when oscillation has stabilized. The recommended procedure for starting the RC oscillator is as follows:
1. Configure XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
3. Poll for XTLVLD > 1.
4. Switch the system clock to the external oscillator.
296
Rev. 0.3
Si102x/3x
23.3.3. External Capacitor Mode
If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 23.1,
Option 3. The capacitor should be added to XTAL2, and XTAL2 should be configured for analog I/O with
the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The oscillation frequency and the required
External Oscillator Frequency Control value (XFCN) in the OSCXCN Register can be determined by the
following equation:
KF
f = --------------------C V DD
where
f = frequency of clock in MHzR = pull-up resistor value in k
VDD = power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
Below is an example of selecting the capacitor and finding the frequency of oscillation Assume VDD = 3.0 V
and f = 150 kHz:
KF
f = --------------------C V DD
KF
0.150 MHz = ----------------C 3.0
Since a frequency of roughly 150 kHz is desired, select the K Factor from Table 23.2 as KF = 22:
22
0.150 MHz = ----------------------C 3.0 V
22
C = ----------------------------------------------0.150 MHz 3.0 V
C = 48.8 pF
Therefore, the XFCN value to use in this example is 011 and C is approximately 50 pF.
The recommended startup procedure for C mode is the same as RC mode.
23.3.4. External CMOS Clock Mode
If an external CMOS clock is used as the external oscillator, the clock should be directly routed into XTAL2.
The XTAL2 pin should be configured as a digital input. XTAL1 is not used in external CMOS clock mode.
The external oscillator valid detector will always return zero when the external oscillator is configured to
External CMOS Clock mode.
Rev. 0.3
297
Si102x/3x
23.4. Special Function Registers for Selecting and Configuring the System Clock
The clocking sources on Si102x/3x devices are enabled and configured using the OSCICN, OSCICL,
OSCXCN and the SmaRTClock internal registers. See Section 24. SmaRTClock (Real Time Clock) on
page 302 for SmaRTClock register descriptions. The system clock source for the MCU can be selected
using the CLKSEL register. To minimize active mode current, the oneshot timer which sets Flash read time
should by bypassed when the system clock is greater than 10 MHz. See the FLSCL register description for
details.
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching
between two clock divide values, the transition may take up to 128 cycles of the undivided clock source.
The CLKRDY flag can be polled to determine when the new clock divide value has been applied. The clock
divider must be set to "divide by 1" when entering Suspend or Sleep Mode.
The system clock source may also be switched on-the-fly. The switchover takes effect after one clock
period of the slower oscillator.
Name
CLKRDY
CLKDIV[2:0]
Typ
R/W
Zurücksetzen
CLKSEL[2:0]
R/W
1
R/W
0
Name
CLKRDY
6:4
3
2:0
298
CLKDIV[2:0]
Unused
CLKSEL[2:0]
Function
Rev. 0.3
Si102x/3x
Name
IOSCEN
IFRDY
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Varies
Varies
Varies
Varies
Varies
Varies
Name
IOSCEN
Function
Internal Oscillator Enable.
0: Internal oscillator disabled.
1: Internal oscillator enabled.
IFRDY
5:0
Notes:
1. Read-modify-write operations such as ORL and ANL must be used to set or clear the enable bit of this
register.
2. OSCBIAS (REG0CN.4) must be set to 1 before enabling the precision internal oscillator.
Rev. 0.3
299
Si102x/3x
SFR Definition 23.3. OSCICL: Internal Oscillator Calibration
Bit
Name
SSE
Typ
R/W
R/W
R/W
Zurücksetzen
Varies
Varies
Varies
R/W
R/W
R/W
R/W
Varies
Varies
Varies
Varies
OSCICL[6:0]
Name
SSE
Function
Spread Spectrum Enable.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
6:0
OSCICL
Note: If the Precision Internal Oscillator is selected as the system clock, the following procedure should be used
when changing the value of the internal oscillator calibration bits.
1. Switch to a different clock source.
2. Disable the oscillator by writing OSCICN.7 to 0.
3. Change OSCICL to the desired setting.
4. Enable the oscillator by writing OSCICN.7 to 1.
300
Rev. 0.3
Si102x/3x
Name XCLKVLD
XOSCMD[2:0]
XFCN[2:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Function
6:4
3
2:0
Rev. 0.3
301
Si102x/3x
24. SmaRTClock (Real Time Clock)
Si102x/3x devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with alarm.
The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a crystal.
No external resistor or loading capacitors are required. The on-chip loading capacitors are programmable
to 16 discrete levels allowing compatibility with a wide range of crystals. The SmaRTClock can operate
directly from a 1.83.6 V battery voltage and remains operational even when the device goes into its lowest power down mode. The SmaRTClock output can be buffered and routed to a GPIO pin to provide an
accurate, low frequency clock to other devices while the MCU is in its lowest power down mode (see
PMU0MD: Power Management Unit Mode on page 274 for more details). Si102x/3x devices also support
an ultra low power internal LFO that reduces sleep mode current.
The SmaRTClock allows a maximum of 36 hour 32-bit independent time-keeping when used with a
32.768 kHz Watch Crystal. The SmaRTClock provides an Alarm and Missing SmaRTClock events, which
could be used as reset or wakeup sources. See Section 22. Reset Sources on page 285 and Section
19. Power Management on page 264 for details on reset sources and low power mode wake-up sources,
respectively.
XTAL3
XTAL4
RTCOUT
SmaRTClock
LFO
Programmable Load Capacitors
SmaRTClock Oscillator
CIP-51 CPU
32-Bit
SmaRTClock
Timer
Internal
Registers
CAPTUREn
RTC0CN
RTC0XCN
RTC0XCF
RTC0CF
ALARMnBn
Interface
Registers
RTC0KEY
RTC0ADR
RTC0DAT
302
Power/
Clock
Mgmt
Rev. 0.3
Si102x/3x
24.1. SmaRTClock Interface
The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These interface registers are located on the CIP-51s SFR map and provide access to the SmaRTClock internal registers listed in Table 24.1. The SmaRTClock internal registers can only be accessed indirectly through the
SmaRTClock Interface.
Register Name
Description
0x000x03
CAPTUREn
SmaRTClock Capture
Registers
0x04
RTC0CN
SmaRTClock Control
Register
0x05
RTC0XCN
SmaRTClock Oscillator
Control Register
0x06
RTC0XCF
SmaRTClock Oscillator
Configuration Register
0x07
RTC0CF
SmaRTClock
Configuration Register
0x080x0B
ALARM0Bn
SmaRTClock Alarm
Registers
0x0C0x0F
ALARM1Bn
SmaRTClock Alarm
Registers
0x100x13
ALARM2Bn
SmaRTClock Alarm
Registers
Rev. 0.3
303
Si102x/3x
24.1.1. SmaRTClock Lock and Key Functions
The SmaRTClock Interface has an RTC0KEY register for legacy reasons, however, all writes to this register are ignored. The SmaRTClock interface is always unlocked on Si102x/3x.
24.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The
RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or
writes. A SmaRTClock Write operation is initiated by writing to the RTC0DAT register. Below is an example
of writing to a SmaRTClock internal register.
1. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address 0x05.
2. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
A SmaRTClock Read operation is initiated by writing the register address to RTC0ADR and reading from
RTC0DAT. Below is an example of reading a SmaRTClock internal register.
1. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address 0x05.
2. Read data from RTC0DAT. This data is a copy of the RTC0CN register.
24.1.3. SmaRTClock Interface Autoread Feature
When Autoread is enabled, each read from RTC0DAT initiates the next indirect read operation on the
SmaRTClock internal register selected by RTC0ADR. Software should set the register address once at the
beginning of each series of consecutive reads. Autoread is enabled by setting AUTORD (RTC0ADR.6) to
logic 1.
24.1.4. RTC0ADR Autoincrement Feature
For ease of reading and writing the 32-bit CAPTURE and ALARM values, RTC0ADR automatically increments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of setting
an alarm or reading the current SmaRTClock timer value. Autoincrement is always enabled.
Recommended Instruction Timing for a multi-byte register read with auto read enabled:
mov
mov
mov
mov
mov
RTC0ADR, #040h
A, RTC0DAT
A, RTC0DAT
A, RTC0DAT
A, RTC0DAT
304
RTC0ADR,
RTC0DAT,
RTC0DAT,
RTC0DAT,
RTC0DAT,
#010h
#05h
#06h
#07h
#08h
Rev. 0.3
Si102x/3x
Name
RTC0ST[7:0]
Typ
R/W
Zurücksetzen
RTC0ST
Function
Name
AUTORD
ADDR[4:0]
Typ
R/W
Zurücksetzen
R/W
0
4:0
Unused
Function
Note: The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMnBn
internal SmaRTClock register.
Rev. 0.3
305
Si102x/3x
SFR Definition 24.3. RTC0DAT: SmaRTClock Data
Bit
Name
RTC0DAT[7:0]
Typ
R/W
Zurücksetzen
Function
Note: Read-modify-write instructions (orl, anl, etc.) should not be used on this register.
306
Rev. 0.3
Si102x/3x
24.2. SmaRTClock Clocking Sources
The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The
SmaRTClock timebase can be derived from an external CMOS clock, the internal LFO, or the SmaRTClock oscillator circuit, which has two modes of operation: Crystal Mode, and Self-Oscillate Mode. The
oscillation frequency is 32.768 kHz in Crystal Mode and can be programmed in the range of 10 kHz to
40 kHz in Self-Oscillate Mode. The internal LFO frequency is 16.4 kHz 20%. The frequency of the
SmaRTClock oscillator can be measured with respect to another oscillator using an on-chip timer. See
Section 33. Timers on page 491 for more information on how this can be accomplished.
Note: The SmaRTClock timebase can be selected as the system clock and routed to a port pin. See Section
23. Clocking Sources on page 293 for information on selecting the system clock source and Section 27. Port
Input/Output on page 358 for information on how to route the system clock to a port pin. The SmaRTClock
timebase can also be routed to a port pin while the device is in its ultra low power sleep mode. See the
PMU0MD register description for details.
24.2.1. Using the SmaRTClock Oscillator with a Crystal or External CMOS Clock
When using Crystal Mode, a 32.768 kHz crystal should be connected between XTAL3 and XTAL4. No
other external components are required. The following steps show how to start the SmaRTClock crystal
oscillator in software:
1. Configure the XTAL3 and XTAL4 pins for Analog I/O.
2. Set SmaRTClock to Crystal Mode (XMODE = 1).
3. Disable Automatic Gain Control (AGCEN) and enable Bias Doubling (BIASX2) for fast crystal startup.
4. Set the desired loading capacitance (RTC0XCF).
5. Enable power to the SmaRTClock oscillator circuit (RTC0EN = 1).
6. Wait 20 ms.
7. Poll the SmaRTClock Clock Valid Bit (CLKVLD) until the crystal oscillator stabilizes.
8. Poll the SmaRTClock Load Capacitance Ready Bit (LOADRDY) until the load capacitance reaches
its programmed value.
9. Enable Automatic Gain Control (AGCEN) and disable Bias Doubling (BIASX2) for maximum power
savings.
10. Enable the SmaRTClock missing clock detector.
11. Wait 2 ms.
12. Clear the PMU0CF wake-up source flags.
In Crystal Mode, the SmaRTClock oscillator may be driven by an external CMOS clock. The CMOS clock
should be applied to XTAL3. XTAL34 should be left floating. In this mode, the external CMOS clock is ac
coupled into the SmaRTClock and should have a minimum voltage swing of 400 mV. The CMOS clock signal voltage should not exceed VDD or drop below GND. Bias levels closer to VDD will result in lower I/O
power consumption because the XTAL3 pin has a built-in weak pull-up. The SmaRTClock oscillator should
be configured to its lowest bias setting with AGC disabled. The CLKVLD bit is indeterminate when using a
CMOS clock, however, the OSCFAIL bit may be checked 2 ms after SmaRTClock oscillator is powered on
to ensure that there is a valid clock on XTAL3. The CLKVLD bit is forced low when BIASX2 is disabled.
Rev. 0.3
307
Si102x/3x
24.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode
When using Self-Oscillate Mode, the XTAL3 and XTAL4 pins are internally shorted together. The following
steps show how to configure SmaRTClock for use in Self-Oscillate Mode:
1. Configure the XTAL3 and XTAL4 pins for analog I/O and disable the digital driver.
2. Set SmaRTClock to Self-Oscillate Mode (XMODE = 0).
3. Set the desired oscillation frequency:
For oscillation at about 20 kHz, set BIASX2 = 0.
For oscillation at about 40 kHz, set BIASX2 = 1.
4. The oscillator starts oscillating instantaneously.
5. Fine tune the oscillation frequency by adjusting the load capacitance (RTC0XCF).
24.2.3. Using the Low Frequency Oscillator (LFO)
The low frequency oscillator provides an ultra low power, on-chip clock source to the SmaRTClock. The
typical frequency of oscillation is 16.4 kHz 20%. No external components are required to use the LFO and
the XTAL3 and XTAL4 pins may be used for general purpose I/O without any effect on the LFO.
The following steps show how to configure SmaRTClock for use with the LFO:
1. Enable and select the Low Frequency Oscillator (LFOEN = 1).
2. The LFO starts oscillating instantaneously.
When the LFO is enabled, the SmaRTClock oscillator increments bit 1 of the 32-bit timer (instead of bit 0).
This effectively multiplies the LFO frequency by 2, making the RTC timebase behave as if a 32.768 kHz
crystal is connected at the output.
24.2.4. Programmable Load Capacitance
The programmable load capacitance has 16 values to support crystal oscillators with a wide range of recommended load capacitance. If Automatic Load Capacitance Stepping is enabled, the crystal load capacitors start at the smallest setting to allow a fast startup time, then slowly increase the capacitance until the
final programmed value is reached. The final programmed loading capacitor value is specified using the
LOADCAP bits in the RTC0XCF register. The LOADCAP setting specifies the amount of on-chip load
capacitance and does not include any stray PCB capacitance. Once the final programmed loading capacitor value is reached, the LOADRDY flag will be set by hardware to logic 1.
When using the SmaRTClock oscillator in Self-Oscillate mode, the programmable load capacitance can be
used to fine tune the oscillation frequency. In most cases, increasing the load capacitor value will result in
a decrease in oscillation frequency.Table 24.2 shows the crystal load capacitance for various settings of
LOADCAP.
308
Rev. 0.3
Si102x/3x
Table 24.2. SmaRTClock Load Capacitance Settings
LOADCAP
0000
4.0 pF
8.0 pF
0001
4.5 pF
9.0 pF
0010
5.0 pF
10.0 pF
0011
5.5 pF
11.0 pF
0100
6.0 pF
12.0 pF
0101
6.5 pF
13.0 pF
0110
7.0 pF
14.0 pF
0111
7.5 pF
15.0 pF
1000
8.0 pF
16.0 pF
1001
8.5 pF
17.0 pF
1010
9.0 pF
18.0 pF
1011
9.5 pF
19.0 pF
1100
10.5 pF
21.0 pF
1101
11.5 pF
23.0 pF
1110
12.5 pF
25.0 pF
1111
13.5 pF
27.0 pF
24.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling
Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in
order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects
when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it
may be enabled during crystal startup. It is recommended to enable Automatic Gain Control in most systems which use the SmaRTClock oscillator in Crystal Mode. The following are recommended crystal specifications and operating conditions when Automatic Gain Control is enabled:
ESR < 50 k
Load Capacitance < 10 pF
Supply Voltage < 3.0 V
Temperature > 20 C
When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure
that the chosen crystal will oscillate under the worst case condition to which the system will be exposed.
The worst case condition that should result in the least robust oscillation is at the following system conditions: lowest temperature, highest supply voltage, highest ESR, highest load capacitance, and lowest bias
current (AGC enabled, Bias Double Disabled).
To perform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as
the system clock source. Next, the SYSCLK signal should be routed to a port pin configured as a push-pull
digital output. The positive duty cycle of the output clock can be used as an indicator of oscillation robust-
Rev. 0.3
309
Si102x/3x
ness. As shown in Figure 24.2, duty cycles less than TBD% indicate a robust oscillation. As the duty cycle
approaches TBD%, oscillation becomes less reliable and the risk of clock failure increases. Increasing the
bias current (by disabling AGC) will always improve oscillation robustness and will reduce the output
clocks duty cycle. This test should be performed at the worst case system conditions, as results at very
low temperatures or high supply voltage will vary from results taken at room temperature or low supply
voltage.
25%
TBD%
Duty Cycle
TBD%
Self-Oscillate
310
Setting
Power
Consumption
Lowest
Niedrig
Hoch
Highest
Niedrig
Bias Double On
Hoch
Rev. 0.3
Si102x/3x
24.2.6. Missing SmaRTClock Detector
The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN.6) to 1.
When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if
SmaRTClock oscillator remains high or low for more than 100 s.
A SmaRTClock Missing Clock detector timeout can trigger an interrupt, wake the device from a low power
mode, or reset the device. See Section 17. Interrupt Handler on page 238, Section 19. Power Management on page 264, and Section 22. Reset Sources on page 285 for more information.
Note: The SmaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in
RTC0XCN.
Rev. 0.3
311
Si102x/3x
running (RTC0TR = 1) in order to set or capture the main timer. The transfer can take up to 2 smaRTClock
cycles to complete.
24.3.3. Software Considerations for using the SmaRTClock Timer and Alarm
The SmaRTClock timer and alarm have two operating modes to suit varying applications. The two modes
are described below:
Mode 1:
The first mode uses the SmaRTClock timer as a perpetual timebase which is never reset to zero. Every 36
hours, the timer is allowed to overflow without being stopped or disrupted. The alarm interval is software
managed and is added to the ALRMnBn registers by software after each alarm. This allows the alarm
match value to always stay ahead of the timer by one software managed interval. If software uses 32-bit
unsigned addition to increment the alarm match value, then it does not need to handle overflows since
both the timer and the alarm match value will overflow in the same manner.
This mode is ideal for applications which have a long alarm interval (e.g., 24 or 36 hours) and/or have a
need for a perpetual timebase. An example of an application that needs a perpetual timebase is one
whose wake-up interval is constantly changing. For these applications, software can keep track of the
number of timer overflows in a 16-bit variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year)
perpetual timebase.
Mode 2:
The second mode uses the SmaRTClock timer as a general purpose up counter which is auto reset to zero
by hardware after each alarm 0 event. The alarm interval is managed by hardware and stored in the
ALRM0Bn registers. Software only needs to set the alarm interval once during device initialization. After
each alarm 0 event, software should keep a count of the number of alarms that have occurred in order to
keep track of time. Alarm 1 and alarm 2 events do not trigger the auto reset.
This mode is ideal for applications that require minimal software intervention and/or have a fixed alarm
interval. This mode is the most power efficient since it requires less CPU time per alarm.
312
Rev. 0.3
Si102x/3x
Name
RTC0EN
MCLKEN
OSCFAIL
RTC0TR
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Varies
Function
RTC0EN
SmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
RTC0TR
Rev. 0.3
313
Si102x/3x
Internal Register Definition 24.5. RTC0XCN: SmaRTClock Oscillator Control
Bit
Name
AGCEN
XMODE
BIASX2
CLKVLD
LFOEN
Typ
R/W
R/W
R/W
Zurücksetzen
R/W
Function
AGCEN
XMODE
BIASX2
CLKVLD
LFOEN
2:0
Unused
314
Rev. 0.3
Si102x/3x
Name AUTOSTP
LOADRDY
LOADCAP
Typ
R/W
Zurücksetzen
R/W
Varies
Varies
Varies
Varies
Function
AUTOSTP
LOADRDY
5:4
Unused
3:0
LOADCAP
Rev. 0.3
315
Si102x/3x
Internal Register Definition 24.7. RTC0CF: SmaRTClock Configuration
Bit
Name
ALRM2
ALRM1
ALRM0
AUTORST
RTC2EN
RTC1EN
RTC0EN
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Function
ALRM2
ALRM1
ALRM0
316
Rev. 0.3
Si102x/3x
Name
CAPTURE[31:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
SmaRTClock Addresses: CAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02; CAPTURE3: 0x03.
Bit
Name
Function
7:0
Note: The least significant bit of the timer capture value is CAPTURE0.0.
Name
ALARM0[31:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
SmaRTClock Address: ALARM0B0 = 0x08; ALARM0B1 = 0x09; ALARM0B2 = 0x0A; ALARM0B3 = 0x0B
Bit
Name
Function
7:0
Note: The least significant bit of the alarm programmed value is ALARM0B0.0.
Rev. 0.3
317
Si102x/3x
Internal Register Definition 24.10. ALARM1Bn: SmaRTClock Alarm 1 Match Value
Bit
Name
ALARM1[31:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
SmaRTClock Address: ALARM1B0 = 0x0C; ALARM1B1 = 0x0D; ALARM1B2 = 0x0E; ALARM1B3 = 0x0F
Bit
Name
Function
7:0
Note: The least significant bit of the alarm programmed value is iALARM1B0.0.
Name
ALARM2[31:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
SmaRTClock Address: ALARM2B0 = 0x10; ALARM2B1 = 0x11; ALARM2B2 = 0x12; ALARM2B3 = 0x13
Bit
Name
Function
7:0
Note: The least significant bit of the alarm programmed value is ALARM2B0.0.
318
Rev. 0.3
Si102x/3x
25. Low-Power Pulse Counter
The Si102x/3x family of microcontrollers contains a low-power pulse counter module with advanced features, such as ultra low power input comparators with programmable thresholds, a wide range of pull up
values with a self calibration engine, asymmetrical integrators for low pass filtering and switch debounce,
single, dual, and quadrature modes of operation, two 24-bit counters, and a variety of interrupt and sleep
wake-up capabilities. This combination of features provides water, gas, and heat metering system designers with an optimal tool for saving power while collecting meter usage data.
Comparator 0
VBAT
PC0DCH
PC0CMP0H:M:L
PC0DCL
24
PC0PCF
PC0
debounce
Counter 0
Logic
PC1
debounce
PC0CTR0H:M:L
Counter 1
PC0CTR1H:M:L
PC0MD
24
PC0TH
Comparator 1
PC0CMP1H:M:L
PC0INT0
Rev. 0.3
319
Si102x/3x
25.1. Counting Modes
The pulse counter supports three different counting modes: single counter mode, dual counter mode, and
quadrature counter mode. Figure 25.2 illustrates the three counter modes.
counter-clockwise
clockwise
PC1
PC0
Figure 25.2. Mode Examples
The single counter mode uses only one pulse counter pin PC0 (P1.0) to count pulses from a single input
channel. This mode uses only Counter 0 and Comparator 0. (Counter 1 and Comparator 1 are not used.)
The single counter mode supports only one meter-encoder with a single-channel output. A single-channel
encoder is an effective solution when the metered fluid flows only in one direction. A single-channel
encoder does not provide any direction information and does not support bidirectional fluid metering.
The dual counter mode supports two independent single-channel meters. Each meter has its own independent counter and comparator. Some of the global configuration settings apply to both channels, such as
pull-up current, sampling rate, and debounce time. The dual mode may also be used for a redundant count
using a two-channel non-quadrature encoder.
Quadrature counter mode supports a single two-channel quadrature meter encoder. The quadrature counter mode supports bidirectional encoders and applications with bidirectional fluid flow. In quadrature counter mode, clockwise counts will increment Counter 0, while counterclockwise counts will increment Counter
1. Subtracting Counter 1 from Counter 0 will yield the net position. If the normal fluid flow is clockwise, then
320
Rev. 0.3
Si102x/3x
the counterclockwise Counter 1 value represents the cumulative backflow. Firmware may use the backflow
counter with the corresponding comparator to implement a backflow alarm. The clockwise sequence is
(LL-HL-HH-LH), and the counterclockwise sequence is (LL-LH-HH-HL). (For this sequence LH means PC1
= Low and PC0 = High.)
Firmware cannot write to the counters. The counters are reset when PC0MD is written and have their
counting enabled when the PC0MD[7:6] mode bits are set to either single, dual, or quadrature modes. The
counters only increment and will roll over to 0x000000 after reaching 0xFFFFFF. For single mode, the PC0
input connects to Counter 0. In dual mode, the PC0 input connects to Counter 0 while the PC1 input connects to Counter 1. In Quadrature mode, clockwise counts are sent to Counter 0 while counterclockwise
counts are sent to Counter 1.
VBAT
Form A
PC0
pull-up required
Form C
VBAT
no pull-up
PC0
Rev. 0.3
321
Si102x/3x
25.3. Programmable Pull-Up Resistors
The pulse counter features low-power pull-up resistors with a programmable resistance and duty-cycle.
The average pull-up current will depend on the selected resistor, sample rate, and pull-up duty-cycle multiplier. Example code is available that will calculate the values for the pull-up configuration SFR (PC0PCF).
Table 25.1through Table 25.3 are used with Equation 25.1 to calculate the average pull-up resistor current.
Table 25.4through Table 25.7 give the average current for all combinations.
I pull-up = I R D SR D PU
IR
000
001
010
011
100
101
110
111
0
1 A
4 A
16 A
64 A
256 A
1 mA
4 mA
DSR
00
01
10
11
1
1/2
1/4
1/8
322
PC0PCF[1:0]
DPU
00
01
10
11
1/4
3/8
1/2
3/4
Rev. 0.3
Si102x/3x
Table 25.4. Average Pull-Up Current (Sample Rate = 250 s)
PC0PCF[4:2]
Duty
Cycle
PC0PCF[1:0]
000
001
010
011
100
101
110
111
00
disabled
250 nA
1.0 A
4.0 A
16 A
64 A
250 A
1000 A
25%
01
disabled
375 nA
1.5 A
6.0 A
24 A
96 A
375 A
1500 A
37.5%
10
disabled
500 nA
2.0 A
8.0 A
32 A
128 A
500 A
2000 A
50%
11
disabled
750 nA
3.0 A
12.0 A
48 A
192 A
750 A
3000 A
75%
Duty
Cycle
PC0PCF[1:0]
000
001
010
011
100
101
110
111
00
disabled
125 nA
0.50 A
2.0 A
8 A
32 A
125 A
500 A
12.5%
01
disabled
188 nA
0.75 A
3.0 A
12 A
48 A
188 A
750 A
18.8%
10
disabled
250 nA
1.0 A
4.0 A
16 A
64 A
250 A
1000 A
25%
11
disabled
375 nA
1.5 A
6.0 A
24 A
96 A
375 A
1500 A
37.5%
Duty
Cycle
PC0PCF[1:0]
000
001
010
011
100
101
110
111
00
disabled
63 nA
250 nA
1.0 A
4 A
16 A
63 A
250 A
6.3%
01
disabled
94 nA
375 nA
1.5 A
6 A
24 A
94 A
375 A
9.4%
10
disabled
125 nA
500 nA
2.0 A
8 A
32 A
125 A
500 A
12.5%
11
disabled
188 nA
750 nA
3.0 A
12 A
48 A
188 A
750 A
18.8%
00
000
disabled
001
31 nA
010
125 nA
PC0PCF[4:2]
011
100
0.50 A 2.0 A
101
8 A
110
31 A
111
125 A
01
disabled
47 nA
188 nA
0.75 A
3.0 A
12 A
47 A
188 A
4.7%
10
disabled
63 nA
250 nA
1.0 A
4.0 A
16 A
63 A
250 A
6.3%
11
disabled
94 nA
375 nA
1.5 A
6.0 A
24 A
94 A
375 A
9.4%
PC0PCF[1:0]
Rev. 0.3
Duty
Cycle
3.1%
323
Si102x/3x
25.4. Automatic Pull-Up Resistor Calibration
The pulse counter includes an automatic calibration engine which can automatically determine the minimum pull-up current for a particular application. The automatic calibration is especially useful when the
load capacitance of field wiring varies from one installation to another.
The automatic calibration uses one of the pulse counter inputs (PC0 or PC1) for calibration. The CALPORT bit in the PC0PCF SFR selects either PC0 or PC1 for calibration. The reed switch on the selected
input should be in the open state to allow the node to charge during calibration. The calibration engine can
calibrate the pull-ups with the meter connected normally, provided that the reed switch is open during calibration. During calibration, the integrators will ignore the input comparators, and the counters will not be
incremented. Using a 250 s sample rate and a 32 kHz RTCCLK, the calibration time will be 21 ms (28
tests @ 750 s each) or shorter depending on the pull up strength selected. The calibration will fail if the
reed switch remains closed during this entire period. If the reed switch is both opened and closed during
the calibration period, the value written into PCCF[4:0] may be larger than what is actually required. The
transition flag in the PC0INT1 can detect when the reed switch opens, and most systems with a wheel
rotation of 10 Hz or slower should have sufficient high time for the calibration to complete before the next
closing of the reed switch. Slowing the sample rate will also increase the calibration time. The same drive
strength will used for both PC0 and PC1.
The example code for the pulse counter includes code for managing the automatic calibration engine.
25.6. Debounce
Like most mechanical switches, reed switches exhibit switch bouncing that could potentially result in false
counts or quadrature errors. The pulse counter includes digital debounce logic using a digital integrator
that can eliminate false counts due to switch bounce. The input of the integrator connects to the pulse
counter inputs with the programmable pull-ups. The output connects to the counters.
The debounce integrator has two independent programmable thresholds: one for the rising edge
(Debounce High) and one for the falling edge (Debounce Low). The PC0DCH (PC0 Debounce Config
High) SFR sets the threshold for the rising edge. This SFR sets the number of cumulative high samples
required to output a logic high to the counter. The PC0DCL (PC0 Debounce Config Low) SFR sets the
threshold for the falling edge. This SFR sets the number of cumulative low samples required to output a
logic low to the counter.
Note that the debounce does count consecutive samples. Requiring consecutive samples would be susceptible to noise. The digital integrator inherently filters out noise.
The system designer should carefully consider the maximum anticipated counter frequency and duty-cycle
when setting the debounce time. If the debounce configuration is set too large, the pulse counter will not
count short pulses. The debounce-high configuration should be set to less than one-half the minimum
input pulse high-time. Similarly, the debounce-low configuration should be set to less than one-half the
minimum input pulse low-time.
Figure 25.4 illustrates the operation of the debounce integrator. The top waveform is the representation of
the reed switch (high: open, low: closed) which shows some random switch bounce. The bottom waveform
is the final signal that goes into the counter which has the switch bounce removed. Based on the actual
reed switch used and sample rate, the switch bounce time may appear shorter in duration than the example in Figure 25.4. The second waveform is the pull-up resistor enable signal. The enable signal enables
324
Rev. 0.3
Si102x/3x
the pull-up resistor when high and disables when low. PC0 is the line to the reed switch. On the right side
of PC0 waveform, the line voltage is decreasing towards ground when the pull-up resistors are disabled.
Beneath the charging waveform, the arrows represent the sample points. The pulse counter samples the
PC0 voltage once the charging completes. The sensed ones and zeros are the sampled data. Finally the
integrator waveform illustrates the output of the digital integrator. The integrator is set to 4 initially and
counts to down to 0 before toggling the output low. Once the integrator reaches the low state, it needs to
count up to 4 before toggling its output to the high state. The debounce logic filters out switch bounce or
noise that appears for a short duration.
Debounce
Debounce
Switch
Charging
Samples
PC0
Sensed
Integrator
(set to 4)
Integrator
Integrator Output
Rev. 0.3
325
Si102x/3x
To enable the pulse counter as a wake up source, enable the source in the PC0INT0/1 SFRs and enable
the pulse counter as a wake-up source by setting bit 0 (PC0WK) to 1 in the PMU0FL SFR. Upon waking,
firmware should read the PMCU0CF and PMU0FL SFRs to determine the wake-up source. If the PC0WK
bit is set indicating that the pulse counter has woke the MCU, firmware should read the flag bits PC0INT0/1
SFRs to determine the pulse counter wake-up source and clear the flag bits before going back to sleep.
PC0INT0 includes the more common interrupt and wake-up sources. These include comparator match,
counter overflow, and quadrature direction change. PC0INT1 includes interrupt and wake-up sources for
the advanced features, including flutter detection and quadrature error.
PC0STAT
PC0HIST
PC0INT0
PC0INT1
PC0CTR0L
PC0CTC1L
The 24-bit counters are three-byte real-time read-only registers that require a special access method for
reading. Firmware must read the low-byte (PC0CTR0L and PC0CTR1L) first and qualify using the read
valid bit. Reading the low-byte latches the middle and high bytes. If the read valid bit is 0, the read is invalid
and firmware must read the low-byte and check the read valid bit again. If the read valid bit is set, the read
is valid and the middle and high bytes are also safe to read. Firmware should read the middle and high
bytes only after reading the low byte and qualifying with the read valid bit.
The 24-bit compators are three-byte real-time read-write registers that require a special access method for
writing. Firmware must write the low-byte last. After writing the low-byte, it might take up to two RTC clock
cycles for the new comparator value to take effect. System designers should consider the synchronization
delay when setting the comparator value. The counter may be incremented before new comparator value
takes effect. Setting the comparator to at least 2 counts above the current count will eliminate the chance
of missing the comparator match during synchronization.
Example code is provided with accessor functions for all the real-time pulse counter registers.
326
Rev. 0.3
Si102x/3x
25.10.2. Flutter Detection
The flutter detection can be used with either quadrature counter mode or dual counter mode when the two
inputs are expected to be in step. Flutter refers to the case where one input continues toggling while the
other input stops toggling. This may indicate a broken reed switch or a pressure oscillation when the wheel
magnet stops at just the right distance from the reed switch. If a pressure oscillation causes a slight rotational oscillation in the wheel, it could cause a number of pulses on one of the inputs, but not on the other.
All four edges are checked by the flutter detection feature (PC1 positive, PC1 negative, PC0 positive, and
PC0 negative).When enabled, Flutter detection may be used as an interrupt or wake-up source.
0
+1
+2
+3
+4
PC1
PC0
Next expected pulse
Next expected pulse with direction change
Flutter detected
Rev. 0.3
327
Si102x/3x
SFR Definition 25.1. PC0MD: PC0 Mode Configuration
Bit
Name
PCMODE[1:0]
PCRATE[1:0]
DUALCMPL
STPCNTFLTR
DUALSTCH
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
Function
3
2
DUALSTCH
Reserved
Note that writing to this register will clear the counter registers PC0CTR0H:M:L and PC0CTR1H:M:L.
328
Rev. 0.3
Si102x/3x
Name
PUCAL
CALRES
CALPORT
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
PUCAL
RES[2:0]
0
DUTY[1:0]
Function
CALRES
CALPORT
Calibration Result
0: Fail (switch may be closed preventing detection of pull ups).
Writes value of 0x11111 to PC0PCF[4:0]
1: Pass (writes calibrated value into PC0PCF[4:0]).
Calibration Port
0: Calibration on PC0 only.
1: Calibration on PC1 only.
4:2
RES[2:0]
1:0
DUTY[1:0]
Rev. 0.3
329
Si102x/3x
SFR Definition 25.3. PC0TH: PC0 Threshold Configuration
Bit
Name
PCTTHRESHI[1:0]
PCTHRESLO[1:0]
PDOWN
PUP
Typ
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
PCTTHRESHI[1:0]
RDVALID
Function
5:4
PCTHRESLO[1:0]
PDOWN
PUP
Force Pull-Up
0: PC0 and PC1 pull-up not forced on continuously. See PC0PCF[1:0] for
duty cycle.
1: PC0 and PC1 pulled high continuously to the PC0PCF[4:2] setting.
PDOWN overrides PUP setting.
Reserved
RDVALID
Read Valid
Holds the status of the last read for real-time registers PC0STAT, PC0HIST,
PC0CTR0L, PC0CTR1L, PC0INT0, and PC0INT1.
0: The last read was invalid.
1: The last read was valid.
RDVALID is set back to 1 upon reading.
330
Rev. 0.3
Si102x/3x
Name FLUTTER
DIRECTION
STATE[1:0]
PC1PREV
PC0PREV
PC1
PC0
RO
RO
RO
RO
RO
Typ
RO
RO
Zurücksetzen
FLUTTER
Function
Flutter
During quadrature mode, a disparity may occur between the number of negative edges of PC1 and PC0 or the number of positive edges of PC1 and
PC0. This could indicate flutter on one reed switch or one reed switch may
be faulty.
0: No flutter detected.
1: Flutter detected.
DIRECTION
Direction
Only applicable for quadrature mode.
(First letter is PC1; second letter is PC0)
0: Counter clock-wise - (LL-LH-HH-HL)
1: Clock-wise - (LL-HL-HH-LH)
5:4
STATE[1:0]
PC0 State
Current State of Internal State Machine.
PC1PREV
PC1 Previous
Previous Output of PC1 Integrator.
PC0PREV
PC0 Previous
Previous Output of PC0 Integrator.
PC1
PC1
Current Output of PC1 Integrator.
PC0
PC0
Current Output of PC0 Integrator.
Rev. 0.3
331
Si102x/3x
SFR Definition 25.5. PC0DCH: PC0 Debounce Configuration High
Bit
Name
PC0DCH[7:0]
Typ
R/W
Zurücksetzen
PC0DCH[7:0]
Function
332
Rev. 0.3
Si102x/3x
Name
PC0DCL[7:0]
Typ
R/W
Zurücksetzen
PC0DCL[7:0]
Function
Rev. 0.3
333
Si102x/3x
SFR Definition 25.7. PC0CTR0H: PC0 Counter 0 High (MSB)
Bit
Name
PC0CTR0H[23:16]
Typ
Zurücksetzen
PC0CTR0H[23:16]
Function
Name
PC0CTR0M[15:8]
Typ
Zurücksetzen
PC0CTR0M[15:8]
Function
Name
PC0CTR0L[7:0]
Typ
Zurücksetzen
PC0CTR0L[7:0]
Function
Note: PC0CTR0L must be read before PC0CTR0M and PC0CTR0H to latch the count for reading. PC0CTRL must
be qualified using the RDVALID bit (PC0TH[0]).
334
Rev. 0.3
Si102x/3x
Name
PC0CTR1H[23:16]
Typ
Zurücksetzen
PC0CTR1H[23:16]
Function
Name
PC0CTR1M[15:8]
Typ
Zurücksetzen
PC0CTR1M[15:8]
Function
Name
PC0CTR1L[7:0]
Typ
Zurücksetzen
PC0CTR1L[7:0]
Function
Note: PC0CTR1L must be read before PC0CTR1M and PC0CTR1H to latch the count for reading.
Rev. 0.3
335
Si102x/3x
SFR Definition 25.13. PC0CMP0H: PC0 Comparator 0 High (MSB)
Bit
Name
PC0CMP0H[23:16]
Typ
R/W
Zurücksetzen
PC0CMP0H[23:16]
Function
Name
PC0CMP0M[15:8]
Typ
R/W
Zurücksetzen
PC0CMP0M[15:8]
Function
Name
PC0CMP0L[7:0]
Typ
R/W
Zurücksetzen
PC0CMP0L[7:0]
Function
Note: PC0CMP0L must be written last after writing PC0CMP0M and PC0CMP0H. After writing PC0CMP0L, the
synchronization into the PC clock domain can take 2 RTC clock cycles.
336
Rev. 0.3
Si102x/3x
Name
PC0CMP1H[23:16]
Typ
R/W
Zurücksetzen
PC0CMP1H[23:16]
Function
Name
PC0CMP1M[15:8]
Typ
R/W
Zurücksetzen
PC0CMP1M[15:8]
Function
Name
PC0CMP1L[7:0]
Typ
R/W
Zurücksetzen
PC0CMP1L[7:0]
Function
Note: PC0CMP1L must be written last after writing PC0CMP1M and PC0CMP1H. After writing PC0CMP1L the
synchronization into the PC clock domain can take 2 RTC clock cycles.
Rev. 0.3
337
Si102x/3x
SFR Definition 25.19. PC0HIST: PC0 History
Bit
Name
PC0HIST[7:0]
Typ
Zurücksetzen
PC0HIST[7:0]
Function
PC0 History.
Contains the last 8 recorded directions (1: clock-wise, 0: counter clock-wise)
on the previous 8 counts. Values of 0x55 or 0xAA may indicate flutter during
quadrature mode.
338
Rev. 0.3
Si102x/3x
Name
CMP1F
CMP1EN
CMP0F
CMP0EN
OVRF
OVREN
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
CMP1F
CMP1EN
CMP0F
CMP0EN
OVRF
OVREN
DIRCHGF
DIRCHGEN
DIRCHGF DIRCHGEN
Function
Comparator 1 Flag
0: Counter 1 did not match comparator 1 value.
1: Counter 1 matched comparator 1 value.
Comparator 1 Interrupt/Wake-up Source Enable
0:CMP1F not enabled as interrupt or wake-up source.
1:CMP1F enabled as interrupt or wake-up source.
Comparator 0 Flag
0: Counter 0 did not match comparator 0 value.
1: Counter 0 matched comparator 0 value.
Comparator 0 Interrupt/Wake-up Source Enable
0:CMP0F not enabled as interrupt or wake-up source.
1:CMP0F enabled as interrupt or wake-up source.
Counter Overflow Flag
1:Neither of the counters has overflowed.
1:One of the counters has overflowed.
Counter Overflow Interrupt/Wake-up Source Enable
0:OVRF not enabled as interrupt or wake-up source.
1:OVRF enabled as interrupt or wake-up source.
Direction Change Flag
Direction changed for quadrature mode only.
0:No change in direction detected.
1:Direction Change detected.
Direction Change Interrupt/Wake-up Source Enable
0:DIRCHGF not enabled as interrupt or wake-up source.
1:DIRCHGF enabled as interrupt or wake-up source.
Rev. 0.3
339
Si102x/3x
SFR Definition 25.21. PC0INT1: PC0 Interrupt 1
Bit
FLTRSTPEN
ERRORF
ERROREN
TRANSF TRANSEN
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Function
FLTRSTRF
FLTRSTREN
FLTRSTPF
FLTRSTPEN
ERRORF
ERROREN
TRANSF
TRANSEN
340
Rev. 0.3
Si102x/3x
26. LCD Segment Driver (Si102x Only)
Si102x devices contain an LCD segment driver and on-chip bias generation that supports static, 2-mux, 3mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output voltage
allows software contrast control which is independent of the supply voltage. LCD timing is derived from the
SmaRTClock oscillator to allow precise control over the refresh rate.
The Si102x uses special function registers (SFRs) to store the enabled/disabled state of individual LCD
segments. All LCD waveforms are generated on-chip based on the contents of the LCD0Dn registers. An
LCD blinking function is also supported. A block diagram of the LCD segment driver is shown in
Figure 26.1.
10 uF
VLCD
VBAT
Charge
Pump
SmaRTClock
Clock
Divider
Power
Management
LCD Clock
Bias
Generator
32 Segment
Pins
Port
Drivers
Configuration
Registers
Data Registers
4 COM Pins
Rev. 0.3
341
Si102x/3x
LCD0CF register.
8. Set the LCD contrast using the LCD0CNTRST register.
9. Set the desired threshold for the VBAT supply monitor.
10. Set the LCD refresh rate using the LCD0DIVH:LCD0DIVL registers.
11. Write a pattern to the LCD0Dn registers.
12. Enable the LCD by setting bit 0 of LCD0MSCN to logic 1 (LCD0MSCN |= 0x01).
Name
LCD0Dn
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
7:0
LCD0Dn
Function
LCD Data.
Each nibble controls one LCD pin.
See 26.2. Mapping Data Registers to LCD Pins on page 342 for additonal
informatoin.
342
Rev. 0.3
Si102x/3x
0
LCD0DF
(Pins: LCD31, LCD30)
LCD0DE
(Pins: LCD29, LCD28)
LCD0DD
(Pins: LCD27, LCD26)
LCD0DC
(Pins: LCD25, LCD24)
LCD0DB
(Pins: LCD23, LCD22)
LCD0DA
(Pins: LCD21, LCD20)
LCD0D9
(Pins: LCD19, LCD18)
LCD0D8
(Pins: LCD17, LCD16)
LCD0D7
(Pins: LCD15, LCD14)
LCD0D6
(Pins: LCD13, LCD12)
LCD0D5
(Pins: LCD11, LCD10)
LCD0D4
(Pins: LCD9, LCD8)
LCD0D3
(Pins: LCD7, LCD6)
LCD0D2
(Pins: LCD5, LCD4)
LCD0D1
(Pins: LCD3, LCD2)
COM0
COM1
COM2
COM3
COM0
COM1
COM2
LCD0D0
(Pins: LCD1, LCD0)
COM3
Bit:
Rev. 0.3
343
Si102x/3x
SFR Definition 26.2. LCD0CN: LCD0 Control Register
Bit
Name
CLKDIV[1:0]
BLANK
SIZE
MUXMD[1:0]
BIAS
R/W
R/W
Typ
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Function
SIZE
Selects whether 16 or 32 segment pins will be used for the LCD function.
0: P0 and P1 are used as LCD segment pins.
1: P0, P1, P2, and P3 are used as LCD segment pins.
2:1
Bias Select.
Selects between 1/2 Bias and 1/3 Bias. This bit is ignored if Static mode is
selected.
0: LCD0 is configured for 1/3 Bias.
1: LCD0 is configured for 1/2 Bias.
344
Rev. 0.3
Si102x/3x
26.3. LCD Contrast Adjustment
The LCD Bias voltages which determine the LCD contrast are generated using the VBAT supply voltage or
the on-chip charge pump. There are four contrast control modes to accomodate a wide variety of applications and supply voltages. The target contrast voltage is programmable in 60 mV steps from 1.9 to 3.72 V.
The LCD contrast voltage is controlled by the LCD0CNTRST register and the contrast control mode is
selected by setting the appropriate bits in the LCD0MSCN, LCD0MSCF, LCD0PWR, and LCD0VBMCN
registers.
Note: An external 10 F decoupling capacitor is required on the VLCD pin to create a charge reservoir at the output of
the charge pump.
LCD0MSCN.2
LCD0MSCF.0
LCD0PWR.3
LCD0VBMCN.7
1*
1*
VBAT
VLCD
Rev. 0.3
345
Si102x/3x
26.3.2. Contrast Control Mode 2 (Minimum Contrast Mode)
In Contrast Control Mode 2, a minimum contrast voltage is maintained, as shown in Figure 26.4. The
VLCD supply is powered directly from VBAT as long as VBAT is higher than the programmable VBAT monitor threshold voltage. As soon as the VBAT supply monitor detects that VBAT has dropped below the programmed value, the charge pump will be automatically enabled in order to acheive the desired minimum
contrast voltage on VLCD. Minimum Contrast Mode is selected using the following procedure:
1. Clear Bit 2 of the LCD0MSCN register to 0b (LCD0MSCN &= ~0x04)
2. Set Bit 0 of the LCD0MSCF register to 1b (LCD0MSCF |= 0x01)
3. Set Bit 3 of the LCD0PWR register to 1b (LCD0PWR |= 0x08)
4. Set Bit 7 of the LCD0VBMCN register to 1b (LCD0VBMCN |= 0x80)
VBAT
VLCD
VBAT
VLC D
346
Rev. 0.3
Si102x/3x
26.3.4. Contrast Control Mode 4 (Auto-Bypass Mode)
In Contrast Control Mode 4, behavior is identical to Constant Contrast Mode as long as VBAT is greater
than the VBAT monitor threshold voltage. When VBAT drops below the programmed threshold, the device
automatically enters bypass mode powering VLCD directly from VBAT. The charge pump is always disabled in this mode. Auto-Bypass Mode is selected using the following procedure:
1. Set Bit 2 of the LCD0MSCN register to 1b (LCD0MSCN |= 0x04)
2. Clear Bit 0 of the LCD0MSCF register to 0b (LCD0MSCF &= ~0x01)
3. Clear Bit 3 of the LCD0PWR register to 0b (LCD0PWR &= ~0x08)
4. Set Bit 7 of the LCD0VBMCN register to 1b (LCD0VBMCN |= 0x80)
VBAT
VLC D
Rev. 0.3
347
Si102x/3x
SFR Definition 26.3. LCD0CNTRST: LCD0 Contrast Adjustment
Bit
Name
Reserved
Reserved
Reserved
CNTRST
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
7:5
4:0
348
Name
Function
Rev. 0.3
Si102x/3x
Name
BIASEN
DCBIASOE
CLKOE
LOWDRV
LCDRST
LCDEN
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Reserved
BIASEN
Function
DCBIASOE
CLKOE
3
2
Reserved
LOWDRV
LCDRST
LCD0 Reset.
Writing a 1 to this bit will clear all the LCD0Dn registers to 0x00. This bit must be
cleared by software.
LCDEN
LCD0 Enable.
0: LCD0 is disabled.
1: LCD0 is enabled.
Note 1: To same bias generator is shared by the dc-dc converter and LCD0.
Rev. 0.3
349
Si102x/3x
SFR Definition 26.5. LCD0MSCF: LCD0 Master Configuration
Bit
DCENSLP CHPBYP
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Reserved
DCENSLP
Function
CHPBYP
MODE
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Unused
MODE
2:0
Reserved
350
Function
Rev. 0.3
Si102x/3x
26.4. Adjusting the VBAT Monitor Threshold
The VBAT monitor is used primarily for the contrast control function, to detect when VBAT has fallen below
a specific threshold. The VBAT monitor threshold may be set independently of the contrast setting or it may
be linked to the contrast setting. When the VBAT monitor threshold is linked to the contrast setting, an offset (in 60mV steps) may be configured so that the VBAT monitor generates a VBAT low condition prior to
VBAT dropping below the programmed contrast voltage. The LCD0VBMCN register is used to enable and
configure the VBAT monitor. The VBAT monitor may be enabled as a wake-up source to wake up the
device from Sleep mode when the battery is getting low. See 19. Power Management on page 264 for
more details.
Name VBATMEN
OFFSET
THRLD[4:0]
Typ
R/W
R/W
R/W
Zurücksetzen
R/W
0
Name
Function
OFFSET
5
4:0
Unused
Read = 0. Write = Dont Care.
THRLD[4:0] VBAT Monitor Threshold
If OFFSET is set to 0b, this bit field has the same defintion as the CNTRST bit field
and can be programmed independently of the contrast.
If OFFSET is set to 1b, this bit field is interpreted as an offset to the currently programmed contrast setting. The LCD0CNTRST register should be written before
setting OFFSET to logic 1 and should not be changed as long as VBAT Monitor Offset is enabled. When THRLD[4:0] is set to 00000b, the VBAT monitor
threshold is equal to the contrast voltage. When THRLD[4:0] is set to 00001b, the
VBAT monitor threshold is one step higher than the contrast voltage. The step size
is equal to the step size of the CNTRST bit field.
Rev. 0.3
351
Si102x/3x
26.5. Setting the LCD Refresh Rate
The clock to the LCD0 module is derived from the SmaRTClock and may be divided down according to the
settings in the LCD0CN register. The LCD refresh rate is derived from the LCD0 clock and can be programmed using the LCD0DIVH:LCD0DIVL registers. The LCD mux mode must be taken into account
when determining the prescaler value. See the LCD0DIVH/LCD0DIVL register descriptions for more
details. For maximum power savings, choose a slow LCD refresh rate and the minimum LCD0 clock frequency. For the least flicker, choose a fast LCD refresh rate.
SFR Definition 26.8. LCD0CLKDIVH: LCD0 Refresh Rate Prescaler High Byte
Bit
Name
LCD0DIV[9:8]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
R/W
0
7:2
1:0
Name
Function
Unused
Read = 000000. Write = Dont Care.
LCD0DIV[9:8] LCD Refresh Rate Prescaler.
Sets the LCD refresh rate according to the following equation:
LCD0 Clock Frequency
LCD Refresh Rate = ----------------------------------------------------------------------------------4 mux_mode LCD0DIV + 1
SFR Definition 26.9. LCD0CLKDIVL: LCD Refresh Rate Prescaler Low Byte
Bit
Name
LCD0DIV[7:0]
Typ
R/W
Zurücksetzen
7:0
Name
Function
352
Rev. 0.3
Si102x/3x
26.6. Blinking LCD Segments
The LCD driver supports blinking LCD applications such as clock applications where the : separator toggles on and off once per second. If the LCD is only displaying the hours and minutes, then the device only
needs to wake up once per minute to update the display. The once per second blinking is automatically
handled by the Si102x/3x.
The LCD0BLINK register can be used to enable blinking on any LCD segment connected to the LCD0 or
LCD1 segment pin. In static mode, a maximum of 2 segments can blink. In 2-mux mode, a maximum of 4
segments can blink; in 3-mux mode, a maximum of 6 segments can blink; and in 4-mux mode, a maximum
of 8 segments can blink. The LCD0BLINK mask register targets the same LCD segments as the LCD0D0
register. If an LCD0BLINK bit corresponding to an LCD segment is set to 1, then that segment will toggle at
the frequency set by the LCD0TOGR register without any software intervention.
Name
LCD0BLINK[7:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
7:0
Name
Function
Rev. 0.3
353
Si102x/3x
SFR Definition 26.11. LCD0TOGR: LCD0 Toggle Rate
Bit
Name
1
TOGR[3:0]
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
R/W
0
Name
7:4
Unused
TOGR[3:0]
3:0
Function
354
Rev. 0.3
Si102x/3x
26.7. Advanced LCD Optimizations
The special function registers described in this section should be left at their reset value for most systems.
Some systems with specific low power or large load requirments will benefit from tweaking the values in
these registers to achieve minimum power consumption or maximum drive level.
CMPBYP
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Reserved
CMPBYP
Function
4 :0
Reserved
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Reserved
Function
Rev. 0.3
355
Si102x/3x
SFR Definition 26.14. LCD0CHPCF: LCD0 Charge Pump Configuration
Bit
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Reserved
Function
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Reserved
Function
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
356
Reserved
Function
Rev. 0.3
Si102x/3x
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Reserved
Function
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Reserved
Function
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
Reserved
Function
Rev. 0.3
357
Si102x/3x
27. Port Input/Output
Digital and analog resources are available through 53 I/O pins. Port pins are organized as eight byte-wide
ports. Port pins can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P7.0 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See
Section 35. C2 Interface on page 533 for more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See
Section 27.3 for more information on the Crossbar.
For port I/Os configured as push-pull outputs, current is sourced from the VIO or VIORF supply pin. See
Section 27.1 for more information on port I/O operating modes and the electrical specifications chapter for
detailed electrical specifications.
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Highest
Priority
UART
Priority
Decoder
PnMDOUT,
PnMDIN Registers
SPI0
SPI1
P1
I/O
Cells
SMBus
8
CP0
CP1
Outputs
Digital
Crossbar
8
SYSCLK
7
2
T0, T1
P0
(Port Latches)
P0
I/O
Cells
8
P6
(P6.0-P6.7)
1
P7
(P7.0)
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
P2
I/O
Cells
P3
I/O
Cells
P4
I/O
Cells
P5
I/O
Cells
P6
I/O
Cells
P7
To EMIF
358
External Interrupts
EX0 and EX1
P0.0
P0.7
P1.0
P1.7
PCA
Lowest
Priority
XBR0, XBR1,
XBR2, PnSKIP
Registers
Rev. 0.3
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6.7
P7.0
To LCD
Si102x/3x
27.1. Port I/O Modes of Operation
Port pins P0.0P6.7 use the port I/O cell shown in Figure 27.2. The supply pin for P1.4 - P2.3 is VIORF
and the supply for all other GPIOs is VIO. Each port I/O cell can be configured by software for analog I/O or
digital I/O using the PnMDIN registers. P7.0 can only be used for digital functtons and is shared with the
C2D signal. On reset, all port I/O cells default to a digital high impedance state with weak pull-ups enabled.
27.1.1. Port Pins Configured for Analog I/O
Any pins to be used as comparator or ADC input, external oscillator input/output, or AGND, VREF, or current reference output should be configured for analog I/O (PnMDIN.n = 0). When a pin is configured for
analog I/O, its weak pullup and digital receiver are disabled. In most cases, software should also disable
the digital output drivers. port pins configured for analog I/O will always read back a value of 0 regardless
of the actual voltage on the pin.
Configuring pins as analog I/O saves power and isolates the port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recommended and may result in measurement errors.
27.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture functions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the port pad to the supply or GND rails based on the output logic
value of the port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive the
port pad to GND when the output logic value is 0 and become high impedance inputs (both high and low
drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to
the supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled when
the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to 1. The user must ensure that digital I/O are always internally or externally pulled or driven to
a valid logic state. Port pins configured for digital I/O always read back the logic state of the port pad,
regardless of the output logic value of the port pin.
WEAKPUD
(Weak Pull-Up Disable)
PnMDOUT.x
(1 for push-pull)
(0 for open-drain)
Supply
XBARE
(Crossbar
Enable)
Supply
(WEAK)
PORT
PAD
Pn.x Output
Logic Value
(Port Latch or
Crossbar)
PnMDIN.x
(1 for digital)
(0 for analog)
To/From Analog
Peripheral
GND
Rev. 0.3
359
Si102x/3x
27.1.3. Interfacing Port I/O to High Voltage Logic
All port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage up to VIO + 2 V. An external pull-up resistor to the higher supply voltage is typically
required for most systems.
27.1.4. Increasing Port I/O Drive Strength
Port I/O output drivers support a high and low drive strength; the default is low drive strength. The drive
strength of a port I/O can be configured using the PnDRV registers. See Section 4. Electrical Characteristics on page 50 for the difference in output drive strength between the two modes.
360
Potentially
Assignable Port Pins
ADC Input
P0.0P0.7,
P1.4P2.3
ADC0MX, PnSKIP
Comparator0 Input
P0.0P0.7,
P1.4P2.3
CPT0MX, PnSKIP
Comparator1 Input
P0.0P0.7,
P1.4P2.3
CPT1MX, PnSKIP
P2.4P6.7
PnMDIN, PnSKIP
P1.0, P1.1
P1MDIN, PnSKIP
P0.0
REF0CN, PnSKIP
P0.1
REF0CN, PnSKIP
P0.7
IREF0CN, PnSKIP
P0.2
OSCXCN, PnSKIP
P0.3
OSCXCN, PnSKIP
P1.2
P1MDIN, PnSKIP
P1.3
P1MDIN, PnSKIP
Rev. 0.3
Si102x/3x
27.2.2. Assigning Port I/O Pins to Digital Functions
Any port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the crossbar for pin assignment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. Port pins used by these digital functions
and any port pins selected for use as GPIO should have their corresponding bit in PnSKIP set to 1.
Table 27.2 shows all available digital functions and the potential mapping of port I/O to each digital function.
P0.0P7.0
P0SKIP, P1SKIP,
P2SKIP
P3.6P6.7
EMI0CF
27.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the crossbar (PnSKIP
= 0). External digital even capture functions cannot be used on pins configured for analog I/O. Table 27.3
shows all available external digital event capture functions.
Table 27.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function
External Interrupt 0
IT01CF
External Interrupt 1
IT01CF
P0.0P1.7
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Rev. 0.3
361
Si102x/3x
27.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a port I/O pin to each software selected digital function using the
fixed peripheral priority order shown in Figure 27.3. The registers XBR0, XBR1, and XBR2 defined in SFR
Definition 27.1, SFR Definition 27.2, and SFR Definition 27.3 are used to select digital functions in the
crossbar. The port pins available for assignment by the crossbar include all port pins (P0.0P2.6) which
have their corresponding bit in PnSKIP set to 0.
From Figure 27.3, the highest priority peripheral is UART0. If UART0 is selected in the crossbar (using the
XBRn registers), then P0.4 and P0.5 will be assigned to UART0. The next highest priority peripheral is
SPI1. If SPI1 is selected in the crossbar, then P2.0P2.2 will be assigned to SPI1. P2.3 will be assigned if
SPI1 is configured for 4-wire mode. The user should ensure that the pins to be assigned by the crossbar
have their PnSKIP bits set to 0.
For all remaining digital functions selected in the crossbar, starting at the top of Figure 27.3 going down,
the least-significant unskipped, unassigned port pin(s) are assigned to that function. If a port pin is already
assigned (e.g., UART0 or SPI1 pins), or if its PnSKIP bit is set to 1, then the crossbar will skip over the pin
and find next available unskipped, unassigned port pin. All port pins used for analog functions, GPIO, or
dedicated digital functions such as the EMIF should have their PnSKIP bit set to 1.
Figure 27.3 shows the crossbar decoder priority with no port pins skipped (P0SKIP, P1SKIP, P2SKIP =
0x00); Figure 27.4 shows the crossbar decoder priority with the external oscillator pins (XTAL1 and XTAL2)
skipped (P0SKIP = 0x0C).
Important Notes:
The crossbar must be enabled (XBARE = 1) before any port pin is used as a digital output. Port output
drivers are disabled while the crossbar is disabled.
When SMBus is selected in the crossbar, the pins associated with SDA and SCL will automatically be
forced into open-drain output mode regardless of the PnMDOUT setting.
SPI0 can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1NSSMD0 bits in register SPI0CN. The NSS signal is only routed to a port pin when 4-wire mode is
selected. When SPI0 is selected in the crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout
of all digital functions lower in priority than SPI0.
For given XBRn, PnSKIP, and SPInCN register settings, one can determine the I/O pin-out of the
device using Figure 27.3 and Figure 27.4.
362
Rev. 0.3
Si102x/3x
XTAL1
XTAL2
IREF0
AGND
PIN I/O
P1
CNVSTR
SF Signals
VREF
P0
P2
1 2
4 5 6 7
0 0
0 0 0 0
TX0
RX0
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
(*4-Wire SPI Only)
NSS* (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0)
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
Rev. 0.3
363
Si102x/3x
XTAL1
XTAL2
IREF0
AGND
PIN I/O
P1
CNVSTR
SF Signals
VREF
P0
P2
0 1 2 3
4 5 6 7
0 0 0 0
0 0 0 0
TX0
RX0
SCK (SPI1)
MISO (SPI1)
MOSI (SPI1)
(*4-Wire SPI Only)
NSS* (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0)
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
364
Rev. 0.3
Si102x/3x
Name
CP1AE
CP1E
CP0AE
CP0E
SYSCKE
SMB0E
SPI0E
URT0E
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
CP1AE
Function
CP1E
CP0AE
CP0E
SMB0E
SPI0E
URT0E
Rev. 0.3
365
Si102x/3x
SFR Definition 27.2. XBR1: Port I/O Crossbar Register 1
Bit
Name
SPI1E
T1E
T0E
ECIE
PCA0ME[2:0]
R/W
Typ
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Unused
SPI1E
Function
T1E
T0E
ECIE
2:0
366
Rev. 0.3
Si102x/3x
Name
WEAKPUD
XBARE
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Function
XBARE
Crossbar Enable
0: Crossbar disabled.
1: Crossbar enabled.
5:0
Unused
Note: The Crossbar must be enabled (XBARE = 1) to use any Port pin as a digital output.
Rev. 0.3
367
Si102x/3x
27.4. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A software controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A port mismatch event occurs if the logic levels of the ports input pins no longer match the software controlled value. This allows software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMAT registers. A port mismatch event is generated if (P0 & P0MASK) does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode.
See Section 17. Interrupt Handler on page 238 and Section 19. Power Management on page 264 for
more details on interrupt and wake-up sources.
Name
P0MASK[7:0]
Typ
R/W
Zurücksetzen
Function
Name
P0MAT[7:0]
Typ
R/W
Zurücksetzen
Function
368
Rev. 0.3
Si102x/3x
Name
P1MASK[7:0]
Typ
R/W
Zurücksetzen
Function
Note:
Name
P1MAT[7:0]
Typ
R/W
Zurücksetzen
Function
Note:
Rev. 0.3
369
Si102x/3x
27.5. Special Function Registers for Accessing and Configuring Port I/O
All port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a port, the value written to the SFR is latched to maintain
the output data value at each pin. When reading, the logic levels of the port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the crossbar, the
port register can always read its corresponding port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a port latch register as the destination. The read-modify-write
instructions when operating on a port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each port has a corresponding PnSKIP register which allows its individual port pins to be assigned to digital functions or skipped by the crossbar. All port pins used for analog functions, GPIO, or dedicated digital
functions such as the EMIF should have their PnSKIP bit set to 1.
The port input mode of the I/O pins is defined using the port Input Mode registers (PnMDIN). Each port cell
can be configured for analog or digital I/O. This selection is required even for the digital resources selected
in the XBRn registers, and is not automatic. The only exception to this is P2.7, which can only be used for
digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each port output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
The drive strength of the output drivers are controlled by the Port Drive Strength (PnDRV) registers. The
default is low drive strength. See Section 4. Electrical Characteristics on page 50 for the difference in output drive strength between the two modes.
370
Rev. 0.3
Si102x/3x
Name
P0[7:0]
Typ
R/W
Zurücksetzen
P0[7:0]
Port 0 Data.
Sets the port latch logic
value or reads the port pin
logic state in port cells configured for digital I/O.
Lesen
Name
P0SKIP[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
371
Si102x/3x
SFR Definition 27.10. P0MDIN: Port0 Input Mode
Bit
Name
P0MDIN[7:0]
Typ
R/W
Zurücksetzen
P0MDIN[7:0]
Function
Name
P0MDOUT[7:0]
Typ
R/W
Zurücksetzen
Function
372
Rev. 0.3
Si102x/3x
Name
P0DRV[7:0]
Typ
R/W
Zurücksetzen
Function
Name
P1[7:0]
Typ
R/W
Zurücksetzen
P1[7:0]
Port 1 Data.
Sets the port latch logic
value or reads the port pin
logic state in port cells configured for digital I/O.
Rev. 0.3
Read
0: P1.n port pin is logic
LOW.
1: P1.n port pin is logic
HIGH.
373
Si102x/3x
SFR Definition 27.14. P1SKIP: Port1 Skip
Bit
Name
P1SKIP[7:0]
Typ
R/W
Zurücksetzen
Function
Name
P1MDIN[7:0]
Typ
R/W
Zurücksetzen
P1MDIN[7:0]
Function
374
Rev. 0.3
Si102x/3x
Name
P1MDOUT[7:0]
Typ
R/W
Zurücksetzen
Function
Name
P1DRV[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
375
Si102x/3x
SFR Definition 27.18. P2: Port2
Bit
Name
P2[7:0]
Typ
R/W
Zurücksetzen
Name
7:0
P2[7:0]
Description
Port 2 Data.
Sets the port latch logic
value or reads the port pin
logic state in port cells configured for digital I/O.
Lesen
Write
Name
P2SKIP[7:0]
Typ
R/W
Zurücksetzen
Name
7:0
P2SKIP[7:0]
Description
Lesen
Write
376
Rev. 0.3
Si102x/3x
Name
P2MDIN[6:0]
Type
Reset
R/W
1
Reserved
6:0
P2MDIN[6:0]
Function
Name
P2MDOUT[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
377
Si102x/3x
SFR Definition 27.22. P2DRV: Port2 Drive Strength
Bit
Name
P2DRV[7:0]
Typ
R/W
Zurücksetzen
P2DRV[7:0]
Function
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P2.n output has low output drive strength.
1: Corresponding P2.n output has high output drive strength.
Name
P3[7:0]
Typ
R/W
Zurücksetzen
Name
7:0
P3[7:0]
Description
Port 3 Data.
Sets the port latch logic
value or reads the port pin
logic state in port cells configured for digital I/O.
378
Lesen
Rev. 0.3
Write
Si102x/3x
Name
P3MDIN[7:0]
Typ
R/W
Zurücksetzen
P3MDIN[7:0]
Function
Name
P3MDOUT[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
379
Si102x/3x
SFR Definition 27.26. P3DRV: Port3 Drive Strength
Bit
Name
P3DRV[7:0]
Typ
R/W
Zurücksetzen
P3DRV[7:0]
Function
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P3.n output has low output drive strength.
1: Corresponding P3.n output has high output drive strength.
Name
P4[7:0]
Typ
R/W
Zurücksetzen
Name
7:0
P4[7:0]
Description
Port 4 Data.
Sets the port latch logic
value or reads the port pin
logic state in port cells configured for digital I/O.
380
Lesen
Rev. 0.3
Write
Si102x/3x
Name
P4MDIN[7:0]
Typ
R/W
Zurücksetzen
P4MDIN[7:0]
Function
Name
P4MDOUT[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
381
Si102x/3x
SFR Definition 27.30. P4DRV: Port4 Drive Strength
Bit
Name
P4DRV[7:0]
Typ
R/W
Zurücksetzen
P4DRV[7:0]
Function
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P4.n output has low output drive strength.
1: Corresponding P4.n output has high output drive strength.
Name
P5[7:0]
Typ
R/W
Zurücksetzen
Name
7:0
P5[7:0]
Description
Port 5 Data.
Sets the port latch logic
value or reads the port pin
logic state in port cells configured for digital I/O.
382
Lesen
Rev. 0.3
Write
Si102x/3x
Name
P5MDIN[7:0]
Typ
R/W
Zurücksetzen
P5MDIN[7:0]
Function
Note:
Name
P5MDOUT[7:0]
Typ
R/W
Zurücksetzen
Function
Note:
Rev. 0.3
383
Si102x/3x
SFR Definition 27.34. P5DRV: Port5 Drive Strength
Bit
Name
P5DRV[7:0]
Typ
R/W
Zurücksetzen
P5DRV[7:0]
Function
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P5.n output has low output drive strength.
1: Corresponding P5.n output has high output drive strength.
Name
P6[7:0]
Typ
R/W
Zurücksetzen
Name
7:0
P6[7:0]
Description
Port 6 Data.
Sets the port latch logic
value or reads the port pin
logic state in port cells configured for digital I/O.
384
Lesen
Rev. 0.3
Write
Si102x/3x
Name
P6MDIN[7:0]
Typ
R/W
Zurücksetzen
P6MDIN[7:0]
Function
Name
P6MDOUT[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
385
Si102x/3x
SFR Definition 27.38. P6DRV: Port6 Drive Strength
Bit
Name
P6DRV[7:0]
Typ
R/W
Zurücksetzen
P6DRV[7:0]
Function
Configures digital I/O port cells to high or low output drive strength.
0: Corresponding P6.n output has low output drive strength.
1: Corresponding P6.n output has high output drive strength.
Name
P7.0
Typ
R/W
Zurücksetzen
Name
7:1
Unused
P7.0
Description
Write
386
Lesen
Rev. 0.3
Si102x/3x
Name
P7MDOUT
Typ
R/W
Zurücksetzen
Function
7:1
Unused
P7MDOUT.0
Name
P7DRV
Typ
R/W
Zurücksetzen
Unused
P7DRV.0
Function
Configures digital I/O port cells to high or low output drive strength.
0: P7.0 output has low output drive strength.
1: P7.0 output has high output drive strength.
Rev. 0.3
387
Si102x/3x
28. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification Version 1.1 and compatible with the I2C serial bus. Reads and writes to the
interface by the system controller are byte oriented with the SMBus interface autonomously controlling the
serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or slave
(this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block diagram of the SMBus peripheral and the associated SFRs is shown in Figure 28.1.
SMB0CN
M T S S A A A S
A X T T C R C I
SMAO K B K
T O
R L
E D
QO
R E
S
T
SMB0CF
E I B E S S S S
N N U X MMMM
S H S T B B B B
M Y H T F C C
B
OO T S S
L E E 1 0
D
Interrupt
Request
00
T0 Overflow
01
T1 Overflow
10
TMR2H Overflow
11
TMR2L Overflow
SCL
Control
S
L
V
5
S
L
V
4
S
L
V
3
S
L
V
2
S
L
V
1
SMB0ADR
SG
L C
V
0
S S S S S S S
L L L L L L L
V V V V V V V
MMMMMMM
6 5 4 3 2 1 0
SMB0ADM
SDA
FILTER
E
H
A
C
K
N
388
C
R
O
S
S
B
A
R
SDA
Control
SMB0DAT
7 6 5 4 3 2 1 0
S
L
V
6
SCL
FILTER
Rev. 0.3
Port I/O
Si102x/3x
28.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus SpecificationVersion 2.0, Philips Semiconductor.
3. System Management Bus SpecificationVersion 1.1, SBS Implementers Forum.
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Rev. 0.3
389
Si102x/3x
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 28.3 illustrates a typical
SMBus transaction.
SCL
SDA
SLA6
START
SLA5-0
R/W
D7
ACK
D6-0
Data Byte
NACK
STOP
390
Rev. 0.3
Si102x/3x
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
28.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 s, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only implementation.
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data, receiving
an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled,
these interrupts are always generated after the ACK cycle. See Section 28.5 for more details on transmission sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 28.4.2;
Table 28.5 provides a quick SMB0CN decoding reference.
28.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
Rev. 0.3
391
Si102x/3x
Table 28.1. SMBus Clock Source Selection
SMBCS1
0
0
1
1
SMBCS0
0
1
0
1
The SMBCS10 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 28.1. The
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section 33. Timers on page 491.
1
T HighMin = T LowMin = ---------------------------------------------f ClockSourceOverflow
Equation 28.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 28.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 28.1.
f ClockSourceOverflow
BitRate = ---------------------------------------------3
Equation 28.2. Typical SMBus Bit Rate
Figure 28.4 shows the typical SCL generation described by Equation 28.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by Equation 28.2.
Timer Source
Overflows
SCL
TLow
THigh
392
Rev. 0.3
Si102x/3x
3 system clocks
or
1 system clock + s/w delay*
11 system clocks
12 system clocks
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section 28.3.4. SCL Low Timeout on page 390). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 28.4).
Rev. 0.3
393
Si102x/3x
SFR Definition 28.1. SMB0CF: SMBus Clock/Configuration
Bit
Name
ENSMB
INH
BUSY
Typ
R/W
R/W
R/W
Zurücksetzen
EXTHOLD SMBTOE
ENSMB
SMBFTE
SMBCS[1:0]
R/W
R/W
R/W
Function
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
INH
BUSY
EXTHOLD
SMBTOE
SMBFTE
1 :0
394
Rev. 0.3
Si102x/3x
28.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 28.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 28.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
28.4.2.1. Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incoming slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
28.4.2.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK generation is enabled. More detail about automatic slave address recognition can be found in Section 28.4.3.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 28.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 28.5 for SMBus status decoding using the SMB0CN register.
Rev. 0.3
395
Si102x/3x
SFR Definition 28.2. SMB0CN: SMBus Control
Bit
Name
MASTER
TXMODE
STA
STO
ACKRQ
ARBLOST
ACK
SI
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
Write
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
K.A.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
K.A.
STA
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
STO
0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pending (if in Master Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmitted after the next ACK
cycle.
Cleared by Hardware.
ACKRQ
SMBus Acknowledge
Request.
0: No Ack requested
1: ACK requested
K.A.
0: No arbitration error.
1: Arbitration Lost
K.A.
ACK
SMBus Acknowledge.
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
SI
0: No interrupt pending
396
Rev. 0.3
Si102x/3x
Table 28.3. Sources for Hardware Changes to SMB0CN
Bit
MASTER
A START is generated.
TXMODE
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
STA
STO
ACKRQ
ARBLOST
ACK
SI
Rev. 0.3
397
Si102x/3x
Table 28.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
SLV[6:0]
GC bit
0x34
0x7F
0x34
0x34
0x7F
0x34
0x7E
0x34, 0x35
0x34
0x7E
0x70
0x73
Name
SLV[6:0]
GC
Typ
R/W
R/W
Zurücksetzen
SLV[6:0]
Function
GC
398
Rev. 0.3
Si102x/3x
Name
SLVM[6:0]
EHACK
Typ
R/W
R/W
Zurücksetzen
SLVM[6:0]
Function
EHACK
Rev. 0.3
399
Si102x/3x
28.4.4. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
Name
SMB0DAT[7:0]
Typ
R/W
Zurücksetzen
Function
400
Rev. 0.3
Si102x/3x
Figure 28.5 shows a typical master write sequence. Two transmit data bytes are shown, though any number of bytes may be transmitted. All data byte transferred interrupts occur after the ACK cycle in this
mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
SLA
Data Byte
Data Byte
Received by SMBus
Interface
Transmitted by
SMBus Interface
Rev. 0.3
401
Si102x/3x
Interrupts with Hardware ACK Enabled (EHACK = 1)
SLA
Data Byte
Data Byte
Received by SMBus
Interface
Transmitted by
SMBus Interface
402
Rev. 0.3
Si102x/3x
Interrupts with Hardware ACK Enabled (EHACK = 1)
SLA
Data Byte
Data Byte
Received by SMBus
Interface
Transmitted by
SMBus Interface
Rev. 0.3
403
Si102x/3x
Interrupts with Hardware ACK Enabled (EHACK = 1)
SLA
Data Byte
Data Byte
Received by SMBus
Interface
Transmitted by
SMBus Interface
404
Rev. 0.3
Si102x/3x
1100
0
1000
STO
ARBLOST
0 X
ACKRQ
0
ACK
Status
Vector
Mode
Master Transmitter
Master Receiver
1110
0 X
1100
0 X
1110
1 X
0 X
1100
1 X
1 X
0 X
1110
0 X
1000
1000
1110
1110
1110
1100
1100
A master data or address byte End transfer with STOP and start
1
1 was transmitted; ACK
another transfer.
received.
Send repeated START.
1
0 X
ACK
Values to
Write
Values Read
Next Status
Vector Expected
Table 28.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Rev. 0.3
405
Si102x/3x
Values to
Write
STA
STO
0 X
0001
0 X
0100
1 X
0 X
0001
0 X
0000
0100
0000
0100
1110
0 X
Slave Receiver
0010
Clear STO.
0 X
0000
0 X
0 X
1110
0 X
1110
1 X
0001
0000
ACK
ACK
0101
ARBLOST
Status
Vector
0100
ACKRQ
Slave Transmitter
Mode
Values Read
Next Status
Vector Expected
Table 28.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
0010
1 X
0001
1 X
0 X
0000
1 X
1110
Rev. 0.3
Si102x/3x
1100
0
Master Receiver
0 X
1100
0 X
1110
1 X
0 X
1100
1 X
1 X
0 X
1110
1000
1000
STO
ARBLOST
0 X
ACKRQ
0
ACK
Status
Vector
Mode
Master Transmitter
1110
ACK
Values to
Write
Values Read
Next Status
Vector Expected
Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
1000
1000
1110
0 X
1100
1110
1110
0 X
1100
Rev. 0.3
407
Si102x/3x
Values to
Write
STA
STO
0 X
0001
0 X
0100
1 X
0 X
0001
0 X
0000
0 X
0100
0000
0 X
0100
0 X
1110
Clear STO.
0 X
0000
0000
0 X
0 X
1110
0 X
0 X
Slave Receiver
0010
0
1 X
0001
0000
ACK
ACK
0101
ARBLOST
Status
Vector
0100
ACKRQ
Slave Transmitter
Mode
Values Read
Next Status
Vector Expected
Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
0010
1 X
0001
1 X
0 X
1110
0000
1 X
0 X
0 X
1110
Rev. 0.3
Si102x/3x
29. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section 29.1. Enhanced Baud Rate Generation on page 410). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SBUF
(TX Shift)
SET
D
TX
CLR
Crossbar
Zero Detector
Stop Bit
Shift
Start
Data
Tx Control
Tx Clock
Send
Tx IRQ
SCON
TI
Serial
Port
Interrupt
MCE
REN
TB8
RB8
TI
RI
SMODE
UART Baud
Rate Generator
Port I/O
RI
Rx IRQ
Rx Clock
Rx Control
Start
Shift
0x1FF
RB8
Load
SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX
Crossbar
Rev. 0.3
409
Si102x/3x
29.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 29.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
UART
Overflow
TX Clock
Overflow
RX Clock
TH1
Start
Detected
RX Timer
1
UartBaudRate = --- T1_Overflow_Rate
2
B)
T1 CLK
T1_Overflow_Rate = -------------------------256 TH1
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section 33.1. Timer 0 and Timer 1 on
page 493. A quick reference for typical baud rates and system clock frequencies is given in Table 29.1
through Table 29.2. Note that the internal oscillator may still generate the system clock when the external
oscillator is driving Timer 1.
410
Rev. 0.3
Si102x/3x
29.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
TX
RS-232
LEVEL
XLTR
RS-232
RX
C8051Fxxx
OR
TX
TX
RX
RX
MCU
C8051Fxxx
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP
BIT
BIT TIMES
BIT SAMPLING
Rev. 0.3
411
Si102x/3x
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP
BIT
BIT TIMES
BIT SAMPLING
412
Rev. 0.3
Si102x/3x
Master
Device
Slave
Device
Slave
Device
Slave
Device
V+
RX
TX
RX
TX
RX
TX
RX
TX
Rev. 0.3
413
Si102x/3x
SFR Definition 29.1. SCON0: Serial Port 0 Control
Bit
Name
S0MODE
Typ
R/W
Zurücksetzen
MCE0
REN0
TB80
RB80
TI0
RI0
R/W
R/W
R/W
R/W
R/W
R/W
Name
Function
Unused
MCE0
REN0
Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80
RB80
TI0
RI0
414
Rev. 0.3
Si102x/3x
Name
SBUF0[7:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Name
7:0
SBUF0
Function
Serial Data Buffer Bits 7:0 (MSBLSB).
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Rev. 0.3
415
Si102x/3x
Table 29.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
SYSCLK from
Internal Osc.
Baud Rate
% Error
Oscillator Divide
Factor
Timer Clock
Source
SCA1SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
230400
0.32%
106
SYSCLK
XX2
0xCB
115200
0.32%
212
SYSCLK
XX
0x96
57600
0.15%
426
SYSCLK
XX
0x2B
28800
0.32%
848
SYSCLK/4
01
0x96
14400
0.15%
1704
SYSCLK/12
00
0xB9
9600
0.32%
2544
SYSCLK/12
00
0x96
2400
0.32%
10176
SYSCLK/48
10
0x96
1200
0.15%
20448
SYSCLK/48
10
0x2B
SCA1SCA0
(pre-scale
select)1
T1M1
Timer 1
Reload
Value (hex)
Notes:
1. SCA1SCA0 and T1M bit definitions can be found in Section 33.1.
2. X = Dont care.
SYSCLK from
External Osc.
416
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
0.00%
96
SYSCLK
XX2
0xD0
115200
0.00%
192
SYSCLK
XX
0xA0
57600
0.00%
384
SYSCLK
XX
0x40
28800
0.00%
768
SYSCLK / 12
00
0xE0
14400
0.00%
1536
SYSCLK / 12
00
0xC0
9600
0.00%
2304
SYSCLK / 12
00
0xA0
2400
0.00%
9216
SYSCLK / 48
10
0xA0
1200
0.00%
18432
SYSCLK / 48
10
0x40
Rev. 0.3
Si102x/3x
Table 29.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
SYSCLK from
Internal Osc.
T1M1
Timer 1
Reload
Value (hex)
EXTCLK / 8
11
0xFA
192
EXTCLK / 8
11
0xF4
0.00%
384
EXTCLK / 8
11
0xE8
28800
0.00%
768
EXTCLK / 8
11
0xD0
14400
0.00%
1536
EXTCLK / 8
11
0xA0
9600
0.00%
2304
EXTCLK / 8
11
0x70
Target
Baud Rate
(bps)
Baud Rate
% Error
230400
0.00%
96
115200
0.00%
57600
Notes:
1. SCA1SCA0 and T1M bit definitions can be found in Section 33.1.
2. X = Dont care.
Rev. 0.3
417
Si102x/3x
30. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SYSCLK
SPI0CN
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
SPIF
WCOL
MODF
RXOVRN
NSSMD1
NSSMD0
TXBMT
SPIEN
SPI0CFG
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CKR
Clock Divide
Logic
SPI IRQ
Pin Interface
Control
MOSI
Tx Data
SPI0DAT
SCK
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Pin
Control
Logic
MISO
NSS
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
418
Rev. 0.3
C
R
O
S
S
B
A
R
Port I/O
Si102x/3x
30.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
30.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
30.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
30.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
30.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for pointto-point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This
configuration should only be used when operating SPI0 as a master device.
See Figure 30.2, Figure 30.3, and Figure 30.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section 27. Port Input/Output on page 358 for general purpose
port I/O and crossbar information.
Rev. 0.3
419
Si102x/3x
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 30.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 30.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 30.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
420
Rev. 0.3
Si102x/3x
Master
Device 1
NSS
GPIO
MISO
MISO
MOSI
MOSI
SCK
SCK
GPIO
NSS
Master
Device 2
Master
Device
MISO
MISO
MOSI
MOSI
SCK
SCK
Slave
Device
Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Master
Device
GPIO
MISO
MISO
MOSI
MOSI
SCK
SCK
NSS
NSS
MISO
MOSI
Slave
Device
Slave
Device
SCK
NSS
Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
Rev. 0.3
421
Si102x/3x
the SPI will load the shift register with the transmit buffers contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 30.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 30.3 shows a connection diagram between a slave device in 3wire slave mode and a master device.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
422
Rev. 0.3
Si102x/3x
wire slave mode), and the serial input data synchronously with the slaves system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slaves
system clock.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MISO
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 0.3
423
Si102x/3x
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
MISO
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
424
Rev. 0.3
Si102x/3x
Name
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
Typ
R/W
R/W
R/W
Zurücksetzen
SPIBSY
Function
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 30.1 for timing parameters.
Rev. 0.3
425
Si102x/3x
SFR Definition 30.2. SPI0CN: SPI0 Control
Bit
Name
SPIF
WCOL
MODF
RXOVRN
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
SPIF
NSSMD[1:0]
TXBMT
SPIEN
R/W
R/W
Function
WCOL
MODF
RXOVRN
3:2
NSSMD[1:0]
TXBMT
SPIEN
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
426
Rev. 0.3
Si102x/3x
Name
SCR[7:0]
Typ
R/W
Zurücksetzen
SCR[7:0]
Function
SYSCLK
f SCK = ----------------------------------------------------------2 SPI0CKR[7:0] + 1
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
2000000
f SCK = -------------------------2 4 + 1
f SCK = 200kHz
Name
SPI0DAT[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
427
Si102x/3x
SCK*
T
MCKH
MCKL
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
SCK*
T
MCKH
MCKL
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
428
Rev. 0.3
Si102x/3x
NSS
T
SE
CKL
SD
SCK*
T
CKH
SIS
SIH
MOSI
SEZ
SOH
SDZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
NSS
T
SE
CKL
SD
SCK*
T
CKH
SIS
SIH
MOSI
SEZ
SOH
SLH
SDZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Rev. 0.3
429
Si102x/3x
Table 30.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
1 x TSYSCLK
ns
TMCKL
1 x TSYSCLK
ns
TMIS
1 x TSYSCLK + 20
ns
TMIH
ns
2 x TSYSCLK
ns
TSD
2 x TSYSCLK
ns
TSEZ
4 x TSYSCLK
ns
TSDZ
4 x TSYSCLK
ns
TCKH
5 x TSYSCLK
ns
TCKL
5 x TSYSCLK
ns
TSIS
2 x TSYSCLK
ns
TSIH
2 x TSYSCLK
ns
TSOH
4 x TSYSCLK
ns
TSLH
6 x TSYSCLK
8 x TSYSCLK
ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
430
Rev. 0.3
Si102x/3x
31. EZRadioPRO Serial Interface
The EZRadioPRO serial interface (SPI1) provides access to the EZRadioPRO peripheral registers from
software executing on the MCU core. The serial interface consists of two SPI peripherals: a dedicated SPI
Master accessible from the MCU core and a dedicated SPI Slave residing inside the EZRadioPRO
peripheral. The SPI1 peripheral on the MCU core side can only be used in master mode to communicate
with the EZRadioPRO slave device in three-wire mode. NSS for the EZRadioPRO is provided using Port
2.3, which is internally routed to the EZRadioPRO peripheral.
SFR Bus
SYSCLK
SPI0CN
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
SPIF
WCOL
MODF
RXOVRN
NSSMD1
NSSMD0
TXBMT
SPIEN
SPI0CFG
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CKR
Clock Divide
Logic
SPI IRQ
Pin Interface
Control
MOSI
Tx Data
SPI0DAT
SCK
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Write
SPI0DAT
Pin
Control
Logic
MISO
C
R
O
S
S
B
A
R
Port I/O
NSS
Read
SPI0DAT
SFR Bus
Figure 31.1. SPI Block Diagram
Rev. 0.3
431
Si102x/3x
31.1. Signal Descriptions
The four signals used by SPI1 (MOSI, MISO, SCK, NSS) are described below.
31.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output to the MCU core. Data
is transferred most-significant bit first. MOSI is driven by the MSB of the shift register.
31.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the EZRadioPRO to the MCU core. This signal is an input when
SPI1 is operating as a master and an output when SPI1 is operating as a slave. Data is transferred mostsignificant bit first. The MISO pin is placed in a high-impedance state when the SPI1 module is disabled.
31.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to the EZRadioPRO. It is
used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI1
generates this signal.
31.1.4. Slave Select (NSS)
To interface to the EZRadioPRO, SPI1 operates in three-wire mode. The NSS functionality built into the
SPI state machine is not used. Instead, the port pin P2.3 must be configured to control the chip select on
the EZRadioPRO peripheral under software control.
432
Rev. 0.3
Si102x/3x
31.2. SPI1 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI1 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI1CN.6). Writing a byte of data to the SPI1 data register (SPI1DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI1 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI1CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI1 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI1DAT.
The SPI Interrupt Flag, SPIF (SPI1CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI1 modes.
The Write Collision Flag, WCOL (SPI1CN.6) is set to logic 1 if a write to SPI1DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI1DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI1
modes.
The Mode Fault Flag MODF (SPI1CN.5) is set to logic 1 when SPI1 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI1CN are set to logic 0 to disable SPI1 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI1CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
Rev. 0.3
433
Si102x/3x
31.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI
Configuration Register (SPI1CFG). The CKPHA bit (SPI1CFG.5) selects one of two clock phases (edge
used to latch the data). The CKPOL bit (SPI1CFG.4) selects between an active-high or active-low clock.
Both CKPOL and CKPHA must be set to zero in order to communicate with the EZRadioPRO peripheral.
The SPI1 Clock Rate Register (SPI1CKR), as shown in SFR Definition 31.3, controls the master mode
serial clock frequency. When the SPI is configured as a master, the maximum data transfer rate (bits/sec)
is one-half the system clock frequency or 12.5 MHz, whichever is slower.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
434
Rev. 0.3
Bit 1
Bit 0
Si102x/3x
31.6. Using SPI1 with the DMA
SPI1 is a DMA-enabled peripheral that can provide autonomous data transfers when used with the DMA.
The SPI requires two DMA channels for a bidirectional data transfer and also supports unidirectional data
transfers using a single DMA channel.
There are no additional control bits in the SPI1 control and configuration SFRs. The configuration is the
same in DMA and non-DMA mode. While the SPIF flag and/or SPI interrupts are normally used for nonDMA SPI transfers, a DMA transfer is managed using the DMA enable and DMA full transfer complete
flags.
More information on using the SPI1 peripheral with DMA can be found in the detailed example code for
EZRadioPRO.
Rev. 0.3
435
Si102x/3x
b. Select the second DMA channel by writing to DMA0SEL.
c. Configure the selected DMA channel to use the SPI1DAT-to-XRAM peripheral request by writing
0x04 to DMA0NCF.
d. Enable DMA interrupts for the second channel by setting bit 7 of DMA0NCF.
e. Write 0 to DMA0NMD to disable wrapping.
f.
Write the address for the first byte of master input (MISO) data to DMA0NBAH:L.
Enable the interrupt on the second channel by setting the corresponding bit in DMA0INT.
j.
436
Rev. 0.3
Si102x/3x
31.9. Master Mode Unidirectional Data Transfer
A unidirectional SPI master mode DMA transfer will transfer a specified number of bytes out on the MOSI
pin. The MOSI data must be stored in XRAM before initiating the DMA transfers. The SPI1DAT-to-XRAM
peripheral request is not used. Since the DMA does not read the SPI1DAT SFR, the SPI will discard the
MISO data.
A unidirectional transfer only requires one DMA channel to transfer XRAM data to the SPI1DAT SFR. The
DMA interrupt will indicate the completion of the data transfer to the SPI1DAT SFR. When the interrupt
occurs, the DMA has written all of the data to the SPI1DAT SFR, but the SPI has not transmitted the last
byte. Firmware may poll on the SPIBSY bit to determine when the SPI has transmitted the last byte. Firmware should not deassert the NSS pin until after the SPI has transmitted the last byte.
To initiate a master mode unidirectional data transfer:
1. Configure the SPI1 SFRs normally for Master mode.
a. Enable Master mode by setting bit 6 in SPI1CFG.
b. Configure the clock polarity (CKPOL = 0) and clock phase (CKPHA = 0) as desired in SPI1CFG.
c. Configure SPI1CKR for the desired SPI clock rate.
d. Configure 3-wire master mode in SPI1CN.
e. Enable the SPI by setting bit 0 of SPI1CN.
2. Configure the desired DMA channel for the XRAM-to-SPI1DAT transfer.
a. Disable the desired DMA channel by clearing the corresponding bit in DMA0EN.
b. Select the desired DMA channel by writing to DMA0SEL.
c. Configure the selected DMA channel to use the XRAM-to-SPI1DAT XRAM peripheral request by
writing 0x03 to DMA0NCF.
d. Enable DMA interrupts for the desired channel by setting bit 7 of DMA0NCF.
e. Write 0 to DMA0NMD to disable wrapping.
f.
Write the address for the first byte of master output (MOSI) data to DMA0NBAH:L.
Enable the interrupt on the desired channel by setting the corresponding bit in DMA0INT.
j.
Rev. 0.3
437
Si102x/3x
SFR Definition 31.1. SPI1CFG: SPI1 Configuration
Bit
Name
SPIBSY
MSTEN
CKPHA
CKPOL
Typ
R/W
R/W
R/W
Zurücksetzen
SPIBSY
Function
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
MSTEN
CKPHA
CKPOL
3:0
Reserved.
Read = 0111, Write = Don't care.
Note: In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum
settling time for the slave device. See Table 31.1 for timing parameters.
438
Rev. 0.3
Si102x/3x
Name
SPIF
WCOL
MODF
Typ
R/W
R/W
R/W
R/W
Zurücksetzen
SPIF
NSSMD[1:0]
TXBMT
SPIEN
R/W
R/W
Function
WCOL
MODF
Reserved.
Read = Varies; Write = 0.
3:2
NSSMD[1:0]
TXBMT
SPIEN
SPI1 Enable.
0: SPI disabled.
1: SPI enabled.
Rev. 0.3
439
Si102x/3x
SFR Definition 31.3. SPI1CKR: SPI1 Clock Rate
Bit
Name
SCR[7:0]
Typ
R/W
Zurücksetzen
SCR[7:0]
Function
SYSCLK
f SCK = ----------------------------------------------------------2 SPI1CKR[7:0] + 1
for 0 <= SPI1CKR <= 255
Example: If SYSCLK = 2 MHz and SPI1CKR = 0x04,
2000000
f SCK = -------------------------2 4 + 1
f SCK = 200kHz
Name
SPI1DAT[7:0]
Typ
R/W
Zurücksetzen
Function
440
Rev. 0.3
Si102x/3x
SCK*
T
MCKH
MCKL
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Description
Min
Max
Units
1 x TSYSCLK
ns
TMCKL
1 x TSYSCLK
ns
TMIS
1 x TSYSCLK + 20
ns
TMIH
ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
Rev. 0.3
441
Si102x/3x
442
Rev. 0.3
Si102x/3x
32. EZRadioPRO 240960 MHz Transceiver
Si102x/3x devices include the EZRadioPRO family of ISM wireless transceivers with continuous frequency
tuning over 240960 MHz. The wide operating voltage range of 1.83.6 V and low current consumption
makes the EZRadioPRO an ideal solution for battery powered applications.
The EZRadioPRO transceiver operates as a time division duplexing (TDD) transceiver where the device
alternately transmits and receives data packets. The device uses a single-conversion mixer to downconvert the 2-level FSK/GFSK/OOK modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is converted to the digital domain by a high performance ADC
allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in DSP increasing
the receivers performance and flexibility versus analog based architectures. The demodulated signal is
then output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the
64-byte RX FIFO.
A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and receiver do not operate at the same time. The LO is generated by an integrated VCO and Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates, output frequency
and frequency deviation at any frequency between 240960 MHz. The transmit FSK data is modulated
directly into the data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted
spectral content.
The PA output power of the Si1020/21/22/23/30/31/32/33 devices can be configured between 1 and
+20 dBm in 3 dB steps, while the PA output power of the Si1024/25/26/27/34/35/36/37 devices can be
configured between 8 and +13 dBm in 3 dB steps. The PA is single-ended to allow for easy antenna
matching and low BOM cost. The PA incorporates automatic ramp-up and rampdown control to reduce
unwanted spectral spreading. The devices with +20 dBm output power can also be used to compensate
for the reduced performance of a lower cost, lower performance antenna or antenna with size constraints
due to a small form-factor. Competing solutions require large and expensive external PAs to achieve comparable performance. The EZRadioPRO transceivers support frequency hopping, TX/RX switch control,
and antenna diversity switch control to extend the link range and improve performance.
The EZRadioPRO peripheral also controls three GPIO pins: GPIO_0, GPIO_1, and GPIO_2. See Application Note AN415: EZRadioPRO Programming Guide for details on initializing and using the EZRadioPRO
peripheral.
Rev. 0.3
443
Si102x/3x
32.1. EZRadioPRO Operating Modes
The EZRadioPRO transceivers provide several operating modes which can be used to optimize the power
consumption for a given application. Depending upon the system communication protocol, an optimal
trade-off between the radio wake time and power consumption can be achieved.
Table 32.1 summarizes the operating modes of the EZRadioPRO transceivers. In general, any given operating mode may be classified as an active mode or a power saving mode. The table indicates which
block(s) are enabled (active) in each corresponding mode. With the exception of the SHUTDOWN mode,
all can be dynamically selected by sending the appropriate commands over the SPI. An X in any cell
means that, in the given mode of operation, that block can be independently programmed to be either ON
or OFF, without noticeably impacting the current consumption. The SPI circuit block includes the SPI interface hardware and the device register space. The 32 kHz OSC block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal oscillator and wake-up timer. AUX (Auxiliary Blocks) includes the temperature
sensor, general purpose ADC, and low-battery detector.
Circuit Blocks
Digital LDO
SPI
30 MHz
XTAL
PLL
PA
RX
IVDD
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15 nA
STANDBY ON (Register
contents
SLEEP
retained)
SENSOR
ON
OFF
OFF
OFF
OFF
OFF
OFF
450 nA
ON
ON
OFF
OFF
OFF
OFF
1 A
ON
ON
OFF
OFF
OFF
OFF
1 A
READY
ON
ON
OFF
OFF
OFF
600 A
TUNING
ON
ON
ON
OFF
OFF
8.5 mA
TRANSMIT
ON
ON
ON
ON
OFF
30 mA*
RECEIVE
ON
ON
ON
OFF
ON
18.5 mA
SHUTDOWN
Note: Using Si1024/25/26/27/34/35/36/37 at +13 dBm with recommended reference design. These power modes
are for the EZRadioPRO peripheral only and are independent of the MCU power modes.
444
Rev. 0.3
Si102x/3x
32.1.1. Operating Mode Control
There are four primary states in the EZRadioPRO transceiver radio state machine: SHUTDOWN, IDLE,
TX, and RX (see Figure 32.1). The SHUTDOWN state completely shuts down the radio to minimize current
consumption. There are five different configurations/options for the IDLE state which can be selected to
optimize the chip for the application. "Register 07h. Operating Mode and Function Control 1" controls
which operating mode/state is selected with the exception of SHUTDOWN which is controlled by the SDN
pin. The TX and RX state may be reached automatically from any of the IDLE states by setting the
txon/rxon bits in "Register 07h. Operating Mode and Function Control 1". Table 32.2 shows each of the
operating modes with the time required to reach either RX or TX mode as well as the current consumption
of each mode.
The transceivers include a low-power digital regulated supply (LPLDO) which is internally connected in
parallel to the output of the main digital regulator (and is available externally at the VR_DIG pin). This common digital supply voltage is connected to all digital circuit blocks including the digital modem, crystal oscillator, SPI, and register space. The LPLDO has extremely low quiescent current consumption but limited
current supply capability; it is used only in the IDLE-STANDBY and IDLE-SLEEP modes. The main digital
regulator is automatically enabled in all other modes.
SHUTDOWN
SHUT
DWN
IDLE*
RX
TX
*Five Different Options for IDLE
Response Time to
TX
RX
16.8 ms
16.8 ms
15 nA
Idle States:
Standby Mode
Sleep Mode
Sensor Mode
Ready Mode
Tune Mode
800 s
800 s
800 s
200 s
200 s
800 s
800 s
800 s
200 s
200 s
450 nA
1 A
1 A
800 A
8.5 mA
TX State
NA
200 s
30 mA @ +13 dBm
RX State
200 s
NA
18.5 mA
Rev. 0.3
445
Si102x/3x
32.1.1.1. SHUTDOWN State
The SHUTDOWN state is the lowest current consumption state of the device with nominally less than
15 nA of current consumption. The shutdown state may be entered by driving the SDN pin high. The SDN
pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents
of the registers are lost and there is no SPI access.
When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN. After
a POR, the device will be in READY mode with the buffers enabled.
32.1.1.1.1. IDLE State
There are five different modes in the IDLE state which may be selected by "Register 07h. Operating Mode
and Function Control 1". All modes have a tradeoff between current consumption and response time to
TX/RX mode. This tradeoff is shown in Table 32.2. After the POR event, SWRESET, or exiting from the
SHUTDOWN state the chip will default to the IDLE-READY mode. After a POR event the interrupt registers
must be read to properly enter the SLEEP, SENSOR, or STANDBY mode and to control the 32 kHz clock
correctly.
32.1.1.1.2. STANDBY Mode
STANDBY mode has the lowest current consumption of the five IDLE states with only the LPLDO enabled
to maintain the register values. In this mode the registers can be accessed in both read and write mode.
The STANDBY mode can be entered by writing 0h to "Register 07h. Operating Mode and Function Control
1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the
minimum current consumption. Additionally, the ADC should not be selected as an input to the GPIO in this
mode as it will cause excess current consumption.
32.1.1.1.3. SLEEP Mode
In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately
wake-up the radio at specified intervals. See Wake-Up Timer and 32 kHz Clock Source on page 479 for
more information on the Wake-Up-Timer. SLEEP mode is entered by setting enwt = 1 (40h) in "Register
07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC should not be
selected as an input to the GPIO in this mode as it will cause excess current consumption.
32.1.1.1.4. SENSOR Mode
In SENSOR mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in
"Register 07h. Operating Mode and Function Control 1". See Temperature Sensor on page 476 and Low
Battery Detector on page 478 for more information on these features. If an interrupt has occurred (i.e.,
the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption.
32.1.1.1.5. READY Mode
READY Mode is designed to give a fast transition time to TX mode with reasonable current consumption.
In this mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode
by eliminating the crystal start-up time. READY mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function Control 1". To achieve the lowest current consumption state the crystal oscillator
buffer should be disabled in Register 62h. Crystal Oscillator Control and Test. To exit READY mode,
bufovr (bit 1) of this register must be set back to 0.
32.1.1.1.6. TUNE Mode
In TUNE mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This
will give the fastest response to TX mode as the PLL will remain locked but it results in the highest current
consumption. This mode of operation is designed for frequency hopping spread spectrum systems
(FHSS). TUNE mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1". It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables
the crystal oscillator.
446
Rev. 0.3
Si102x/3x
32.1.1.2. TX State
The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h.
Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA. The following sequence of
events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit.
1. Enable the main digital LDO and the Analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO (this action is skipped when the skipvco bit is 1, default value is 0).
5. Wait until PLL settles to required transmit frequency (controlled by an internal timer).
6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer).
7. Transmit packet.
Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to
setting the txon bit. By default, the VCO and PLL are calibrated every time the PLL is enabled.
32.1.1.3. RX State
The RX state may be entered from any of the IDLE modes when the rxon bit is set to 1 in "Register 07h.
Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition from one of the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit:
1. Enable the main digital LDO and the Analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO (this action is skipped when the skipvco bit is 1, default value is 0).
5. Wait until PLL settles to required receive frequency (controlled by an internal timer).
6. Enable receive circuits: LNA, mixers, and ADC.
7. Enable receive mode in the digital modem.
Depending on the configuration of the radio all or some of the following functions will be performed automatically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet
handling (optional) including sync word, header check, and CRC.
32.1.1.4. Device Status
Add R/W
02
Function/
Description
D7
D6
D5
D4
D3
Device Status
ffovfl
ffunfl
rxffem
headerr
freqerr
D2
D1
D0
cps[1] cps[0]
POR Def.
The operational status of the EZRadioPRO peripheral can be read from "Register 02h. Device Status".
32.2. Interrupts
The EZRadioPRO peripheral is capable of generating an interrupt signal (nIRQ) when certain events
occur. The nIRQ pin is driven low to indicate a pending interrupt request. The EZRadioPRO interrupt
does not have an internal interrupt vector. To use the interrupt, the nIRQ pin must be looped back
to an external interrupt input. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low
until the Interrupt Status Register(s) (Registers 03h04h) containing the active Interrupt Status bit is read.
The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be
Rev. 0.3
447
Si102x/3x
enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h06h). All
enabled interrupt bits will be cleared when the corresponding interrupt status register is read. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status may still be read at
anytime in the Interrupt Status registers.
Important Note: The nIRQ line should not be monitored for POR after SDN or initial power up. The POR
signal is available by default on GPIO0 and GPIO1 and should be monitored as an alternative to nIRQ for
POR. As an alternative, software may wait 18 ms after SDN rising before polling the interrupt status registers in 03h and 04h to check for POR and chip ready (XTAL start-up/ready). This process may take up to
26 ms. After the initial interrupt is cleared, the operation of the nIRQ pin will be normal.
Add R/W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
03
Interrupt Status 1
ifferr
itxffafull
itxffaem
irxffafull
iext
ipksent
ipkvalid
icrcerror
04
Interrupt Status 2
iswdet
ipreaval
ipreainval
irssi
iwut
ilbd
ichiprdy
ipor
05 R/W Interrupt Enable 1 enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror
00h
01h
enrssi
enwut
enlbd
enchiprdy
enpor
See AN440: EZRadioPRO Detailed Register Descriptions for a complete list of interrupts.
TX Packet
PA RAMP DOWN
PLLTS
PRE PA RAMP
PA RAMP UP
PLL CAL
XTAL Settling
Time
PLL T0
The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow
for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting
of 100 s. The total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 s. Under certain
applications, the PLL T0 time and the PLL CAL may be skipped for faster turn-around time. Contact applications support if faster turnaround time is desired.
6us, Fixed
600us
448
Rev. 0.3
PLLTS
PLL CAL
XTAL Settling
Time
PLL T0
Si102x/3x
RX Packet
600us
f OUT 10 MHz ( N F )
The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Offset (fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the
synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming
data; this is discussed further in Frequency Deviation on page 452. Also, a fixed offset can be added to
fine-tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the
fc[15:0] register will determine the fractional component. The equation for selection of the carrier frequency
is shown below:
Rev. 0.3
449
Si102x/3x
f carrier 10 MHz (hbsel 1) ( N F )
R/W
74
R/W
75
R/W
76
R/W
77
R/W
fc[15 : 0]
)
64000
Function/
Description
D7
D6
D5
D4
D3
D2
Frequency
Offset 1
Frequency
Offset 2
Frequency Band
Select
Nominal Carrier
Frequency 1
Nominal Carrier
Frequency 0
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
D1
D0
POR Def.
fo[1] fo[0]
00h
fo[9] fo[8]
00h
sbsel
hbsel
fb[4]
fb[3]
fb[2]
fb[1] fb[0]
35h
fc[15]
fc[14]
fc[13]
fc[12]
fc[11]
fc[10]
fc[9] fc[8]
BBh
fc[7]
fc[6]
fc[5]
fc[4]
fc[3]
fc[2]
fc[1] fc[0]
80h
The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connecting a 2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h. Frequency Band Select". This effectively partitions the entire 240960 MHz frequency range into
two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of
fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer
part has a fixed offset of 24 added to it as shown in the formula above. Table 32.3 demonstrates the selection of fb[4:0] for the corresponding frequency band.
After selection of the fb (N) the fractional component may be solved with the following equation:
fTX
fb[4 : 0] 24 * 64000
fc[15 : 0]
10 MHz * (hbsel 1)
450
Frequency Band
hbsel=0
hbsel=1
24
240249.9 MHz
480499.9 MHz
25
250259.9 MHz
500519.9 MHz
26
260269.9 MHz
520539.9 MHz
27
270279.9 MHz
540559.9 MHz
28
280289.9 MHz
560579.9 MHz
29
290299.9 MHz
580599.9 MHz
30
300309.9 MHz
600619.9 MHz
31
310319.9 MHz
620639.9 MHz
32
320329.9 MHz
640659.9 MHz
Rev. 0.3
Si102x/3x
Table 32.3. Frequency Band Selection (Continued)
9
33
330339.9 MHz
660679.9 MHz
10
34
340349.9 MHz
680699.9 MHz
11
35
350359.9 MHz
700719.9 MHz
12
36
360369.9 MHz
720739.9 MHz
13
37
370379.9 MHz
740759.9 MHz
14
38
380389.9 MHz
760779.9 MHz
15
39
390399.9 MHz
780799.9 MHz
16
40
400409.9 MHz
800819.9 MHz
17
41
410419.9 MHz
820839.9 MHz
18
42
420429.9 MHz
840859.9 MHz
19
43
430439.9 MHz
860879.9 MHz
20
44
440449.9 MHz
880899.9 MHz
21
45
450459.9 MHz
900919.9 MHz
22
46
460469.9 MHz
920939.9 MHz
23
47
470479.9 MHz
940960 MHz
The chip will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz 32) to
achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in
the RX Mixing architecture; therefore, no frequency reprogramming is required when using the same TX
frequency and switching between RX/TX modes.
32.3.3. Easy Frequency Programming for FHSS
While Registers 73h77h may be used to program the carrier frequency of the transceiver, it is often easier
to think in terms of channels or channel numbers rather than an absolute frequency value in Hz. Also,
there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is
desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is
first set using Registers 73h77h, as described above. Registers 79h and 7Ah are then used to set a channel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size
(fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency
Hopping Channel Select Register then selects channels based on multiples of the step size.
Rev. 0.3
451
Si102x/3x
Add R/W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
79
R/W
Frequency Hopping
Channel Select
fhch[0]
00h
7A
R/W
Frequency Hopping
Step Size
fhs[7]
fhs[0]
00h
fhs[6]
fhs[5]
fhs[4]
fhs[3]
fhs[2]
fhs[1]
f fd [8 : 0] 625Hz
f
fd [8 : 0]
f = peak deviation
625Hz
Frequency
fcarrier
Time
452
Rev. 0.3
Si102x/3x
Add R/W
Function/
Description
D7
71
R/W
Modulation Mode
Control 2
72
R/W
Frequency Deviation
D6
D5
D4
D3
D2
D1
D0
POR Def.
fd[6]
fd[5]
fd[4]
fd[3]
fd[2]
fd[1]
fd[0]
00h
20h
fo[9 : 0]
DesiredOffset
156.25Hz (hbsel 1)
The adjustment range in high band is 160 kHz and in low band it is 80 kHz. For example to compute an
offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of 50 kHz in high band
mode the fo[9:0] register should be set to 360h.
Add R/W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
fo[1]
fo[0]
00h
fo[9]
fo[8]
00h
73
R/W
Frequency Offset
74
R/W
Frequency Offset
Rev. 0.3
453
Si102x/3x
454
Rev. 0.3
Si102x/3x
Frequency Correction
RX
TX
AFC disabled
AFC enabled
AFC
DR_TX(bps) 2
txdr[15:0] = --------------------------------------------------------------------------------1 MHz
For data rates higher than 100 kbps, Register 58h should be changed from its default of 80h to C0h. Nonoptimal modulation and increased eye closure will result if this setting is not made for data rates higher
than 100 kbps. The txdr register is only applicable to TX mode and does not need to be programmed for
RX mode. The RX bandwidth which is partly determined from the data rate is programmed separately.
Add R/W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
6E
txdr[15]
txdr[10]
txdr[9]
txdr[8]
0Ah
6F
txdr[7]
txdr[6]
txdr[2]
txdr[1]
txdr[0]
3Dh
txdr[5]
txdr[4]
txdr[3]
Modulation Source
00
Unmodulated Carrier
01
OOK
10
FSK
11
Rev. 0.3
455
Si102x/3x
TX Modulation Time Domain Waveforms -- FSK vs. GFSK
1.0
0.5
0.0
-0.5
-1.0
-40
-60
-80
-1.5
-100
1.0
-20
ModSpectrum_GFSK
SigData_GFSK[0,::]
SigData_FSK[0,::]
1.5
0.5
0.0
-0.5
-1.0
0
50
100
150
200
250
300
350
400
450
500
-40
-60
-80
-100
-250
-200
-150
-100
-50
50
100
150
200
250
freq, KHz
time, usec
DataRate
64000.0
TxDev
BT_Filter
32000.0
ModIndex
0.5
1.0
R/W
Function/
Description
Modulation
Mode
Control 2
D7
D6
D5
D4
D3
D2
D1
D0
dtmod[1:0]
POR Def.
00h
Data Source
00
Direct Mode using TX/RX Data via GPIO pin (GPIO configuration required)
01
Direct Mode using TX/RX Data via SDI pin (only when nSEL is high)
10
FIFO Mode
11
456
Rev. 0.3
Si102x/3x
determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler
Registers (see Table 32.4 on page 469). If the Automatic Packet Handler is disabled, the entire desired
packet structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word are
automatically added to the bytes stored in FIFO memory). For further information on the configuration of
the FIFOs for a specific application or packet size, see Data Handling and Packet Handler on page 465.
In RX mode, only the bytes of the received packet structure that are considered to be "data bytes" are
stored in FIFO memory. Which bytes of the received packet are considered "data bytes" is determined by
the Automatic Packet Handler (if enabled), in conjunction with the Packet Handler Registers (see
Table 32.4 on page 469). If the Automatic Packet Handler is disabled, all bytes following the Sync word are
considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation
is not desired, the preamble detection threshold and Sync word still need to be programmed so that the RX
Modem knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the
received data may still be observed directly (in real-time) by properly programming a GPIO pin as the
RXDATA output pin; this can be quite useful during application development.
When in FIFO mode, the chip will automatically exit the TX or RX State when either the ipksent or ipkvalid
interrupt occurs. The chip will return to the IDLE mode state programmed in "Register 07h. Operating
Mode and Function Control 1". For example, the chip may be placed into TX mode by setting the txon bit,
but with the pllon bit additionally set. The chip will transmit all of the contents of the FIFO and the ipksent
interrupt will occur. When this interrupt event occurs, the chip will clear the txon bit and return to TUNE
mode, as indicated by the set state of the pllon bit. If no other bits are additionally set in register 07h
(besides txon initially), then the chip will return to the STANDBY state.
In RX mode, the rxon bit will be cleared if ipkvalid occurs and the rxmpk bit (RX Multi-Packet bit, SPI Register 08h bit [4]) is not set. When the rxmpk bit is set, the part will not exit the RX state after successfully
receiving a packet, but will remain in RX mode. The microcontroller will need to decide on the appropriate
subsequent action, depending upon information such as an interrupt generated by CRC, packet valid, or
preamble detect.
32.4.2.2. Direct Mode
For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be
desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely.
In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real
time" (i.e., not stored in a register for transmission at a later time). A variety of pins may be configured for
use as the TX Data input function.
Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is
desired (only the TX Data input pin is required for FSK). Two options for the source of the TX Data are
available in the dtmod[1:0] field, and various configurations for the source of the TX Data Clock may be
selected through the trclk[1:0] field.
trclk[1:0]
00
01
10
11
The eninv bit in SPI Register 71h will invert the TX Data; this is most likely useful for diagnostic and testing
purposes.
In RX direct mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO
pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions
Rev. 0.3
457
Si102x/3x
of the RFIC. In RX direct mode, the chip must still acquire bit timing during the Preamble, and thus the preamble detection threshold (SPI Register 35h) must still be programmed. Once the preamble is detected,
certain bit timing functions within the RX Modem change their operation for optimized performance over
the remainder of the packet. It is not required that a Sync word be present in the packet in RX Direct mode;
however, if the Sync word is absent then the skipsyn bit in SPI Register 33h must be set, or else the bit timing and tracking function within the RX Modem will not be configured for optimum performance.
32.4.2.3. Direct Synchronous Mode
In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In
direct synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external
device that is providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal
to the programmed data rate. The external modulation source (e.g., MCU) must accept this TX Clock signal as an input and respond by providing one bit of TX Data back to the RFIC, synchronous with one edge
of the TX Clock signal. In this fashion, the rate of the TX Data input stream from the external source is controlled by the programmed data rate of the RFIC; no TX Data bits are made available at the input of the
RFIC until requested by another cycle of the TX Clock signal. The TX Data bits supplied by the external
source are transmitted directly in real-time (i.e., not stored internally for later transmission).
All modulation types (FSK/GFSK/OOK) are valid in TX direct synchronous mode. As will be discussed in
the next section, there are limits on modulation types in TX direct asynchronous mode.
32.4.2.4. Direct Asynchronous Mode
In TX direct asynchronous mode, the RFIC no longer controls the data rate of the TX Data input stream.
Instead, the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data
applied to its TX Data input pin, at whatever rate it is supplied. This means that there is no longer a need
for a TX Clock output signal from the RFIC, as there is no synchronous "handshaking" between the RFIC
and the external data source. The TX Data bits supplied by the external source are transmitted directly in
real-time (i.e., not stored internally for later transmission).
It is not necessary to program the data rate parameter when operating in TX direct asynchronous mode.
The chip still internally samples the incoming TX Data stream to determine when edge transitions occur;
however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples
the incoming TX Data stream at its maximum possible oversampling rate. This allows the chip to accurately determine the timing of the bit edge transitions without prior knowledge of the data rate. (Of course,
it is still necessary to program the desired peak frequency deviation.)
Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is not
available in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data
rate, and thus cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming
data.
458
Rev. 0.3
Px.x
nIRQ
XIN
XOUT
SDN
Si102x/3x
VDD_DIG
VDD_RF
Matching
TX
Px.x
RXp
Px.x
RXn
GPIO_2
VR_DIG
GPIO_1
ANT
GPIO_0
NC
GPIO configuration
GP1 : TX DATA clock output
GP2 : TX DATA input
DataCLK
MOD(Data)
Px.x
nIRQ
XOUT
XIN
SDN
VDD_DIG
VDD_RF
Px.x
TX
Matching
RXp
RXn
GPIO configuration
GP2 : TX DATA input
GPIO_2
VR_DIG
GPIO_1
ANT
GPIO_0
NC
MOD(Data)
Rev. 0.3
459
Si102x/3x
mode it will be the data to be modulated and transmitted. In RX mode it will be the received demodulated
data. Figure 32.9 demonstrates using MOSI and MISO as the TX/RX data and clock:
TX on
command
TX mode
TX off
command
RX on
command
RX mode
RX off
command
NSS
MOSI
SPI input
dont care
SPI input
MOD input
SPI input
dont care
SPI input
Data output
SPI input
MSIO
SPI output
dont care
SPI output
Data CLK
Output
SPI output
dont care
SPI output
Data CLK
Output
SPI output
460
Rev. 0.3
Si102x/3x
32.5.4. ADC
The amplified IQ IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low
current consumption and high dynamic range. The bandpass response of the ADC provides exceptional
rejection of out of band blockers.
32.5.5. Digital Modem
Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed
in the digital domain, resulting in reduced area while increasing flexibility. The digital modem performs the
following functions:
The configurable preamble detector is used to improve the reliability of the sync-word detection. The syncword detector is only enabled when a valid preamble is detected, significantly reducing the probability of
false detection.
The received signal strength indicator (RSSI) provides a measure of the signal strength received on the
tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel
power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT)
functionality.
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital automatic frequency control (AFC) in receive mode.
A comprehensive programmable packet handler including key features of Silicon Labs EZMAC is integrated to create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive programmability of the packet header allows for advanced packet filtering which in
turn enables a mix of broadcast, group, and point-to-point communication.
A wireless communication channel can be corrupted by noise and interference, and it is therefore important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the
presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and
CRC can significantly reduce the load on the microcontroller reducing the overall current consumption.
The digital modem includes the TX modulator which converts the TX data bits into the corresponding
stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator.
This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter
is implemented to support GFSK, considerably reducing the energy in the adjacent channels. The default
bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to other values.
Rev. 0.3
461
Si102x/3x
32.5.6. Synthesizer
An integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating from 240960 MHz is
provided on-chip. Using a synthesizer has many advantages; it provides flexibility in choosing data
rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the
loop in the digital domain through the fractional divider which results in very precise accuracy and control
over the transmit deviation.
Depending on the part, the PLL and - modulator scheme is designed to support any desired frequency
and channel spacing in the range from 240960 MHz with a frequency resolution of 156.25 Hz (Low band)
or 312.5 Hz (High band). The transmit data rate can be programmed between 0.123256 kbps, and the
frequency deviation can be programmed between 1320 kHz. These parameters may be adjusted via
registers as shown in Frequency Control on page 449.
TX
Fref = 10 M
PFD
CP
Selectable
Divider
LPF
RX
VCO
TX
Modulation
DeltaSigma
462
Rev. 0.3
Si102x/3x
32.5.7. Power Amplifier
The Si1020/21/22/23/30/31/32/33 devices have an internal integrated power amplifier (PA) capable of
transmitting at output levels between +1 and +20 dBm. The Si1024/25/26/27/34/35/36/37 devices have a
PA which is capable of transmitting output levels between 8 to +13 dBm. The PA design is single-ended
and is implemented as a two stage class CE amplifier with a high efficiency when transmitting at maximum
power. The PA efficiency can only be optimized at one power level. Changing the output power by adjusting txpow[2:0] will scale both the output power and current but the efficiency will not remain constant. The
PA output is ramped up and down to prevent unwanted spectral splatter.
With the Si1024/25/26/27/34/35/36/37 devices, the TX and RX may be tied directly. See the TX/RX directtie reference design available on the Silicon Labs website for more details. When the direct tie is used, the
lna_sw bit in Register 6Dh, TX Power must be set to 1.
32.5.7.1. Output Power Selection
The output power is configurable in 3 dB steps with the txpow[2:0] field in "Register 6Dh. TX Power". Extra
output power can allow the use of a cheaper smaller antenna, greatly reducing the overall BOM cost. The
higher power setting of the chip achieves maximum possible range, but of course comes at the cost of
higher TX current consumption. However, depending on the duty cycle of the system, the effect on battery
life may be insignificant.
Add R/W
6D
R/W
Function/
Description
TX Power
D7
D6
D5
D4
D3
D2
txpow[2:0]
000
001
010
011
100
101
110
111
txpow[2:0]
000
001
010
011
100
101
110
111
D1
D0
txpow[1] txpow[0]
POR
Def.
18h
Rev. 0.3
463
Si102x/3x
32.5.8. Crystal Oscillator
The transceiver includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than
600 s when a suitable parallel resonant crystal is used. The design is differential with the required crystal
load capacitance integrated on-chip to minimize the number of external components. By default, all that is
required off-chip is the 30 MHz crystal.
The crystal load capacitance can be digitally programmed to accommodate crystals with various load
capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load
capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load
Capacitance". The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps
(97fF/step). The xtalshift bit provides a coarse shift in frequency but is not binary with xlc[6:0].
The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing
the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal
can be canceled.
The typical value of the total on-chip capacitance Cint can be calculated as follows:
Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by
the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If
the maximum value of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning.
Additional information on calculating Cext and crystal selection guidelines is provided in AN417: Si4x3x
Family Crystal Oscillator.
If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency
Offset field fo[9:0]in "Register 73h. Frequency Offset 1" and "Register 74h. Frequency Offset 2", as discussed in Frequency Control on page 449.
The crystal oscillator frequency is divided down internally and may be output to the microcontroller through
one of the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for
the entire system and the BOM cost is reduced. The available clock frequencies and GPIO configuration
are discussed further in Output Clock on page 474.
The transceiver may also be driven with an external 30 MHz clock signal through the XOUT pin. When
driving with an external reference or using a TCXO, the XTAL load capacitance register should be set to 0.
Add R/W Function/Description
09
R/W
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
xtalshift
xlc[6]
xlc[5]
xlc[4]
xlc[3]
xlc[2]
xlc[1]
xlc[0]
7Fh
32.5.9. Regulators
There are a total of six regulators integrated onto the transceiver. With the exception of the digital regulator,
all regulators are designed to operate with only internal decoupling. The digital regulator requires an external 1 F decoupling capacitor. All regulators are designed to operate with an input supply voltage from
+1.8 to +3.6 V. The output stage of the of PA is not connected internally to a regulator and is connected
directly to the battery voltage.
A supply voltage should only be connected to the VDD pins. No voltage should be forced on the digital regulator output.
464
Rev. 0.3
Si102x/3x
32.6. Data Handling and Packet Handler
The internal modem is designed to operate with a packet including a 010101... preamble structure. To configure the modem to operate with packet formats without a preamble or other legacy packet structures contact customer support.
32.6.1. RX and TX FIFOs
Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 32.11.
"Register 7Fh. FIFO Access" is used to access both FIFOs. A burst write to address 7Fh will write data to
the TX FIFO. A burst read from address 7Fh will read data from the RX FIFO.
TX FIFO
RX FIFO
Rev. 0.3
465
Si102x/3x
Add R/W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
antdiv[2]
antdiv[1]
antdiv[0]
rxmpk
autotx
enldm
ffclrrx
ffclrtx
00h
08
R/W
Operating &
Function
Control 2
7C
R/W
TX FIFO
Control 1
7D
R/W
TX FIFO
Control 2
37h
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When
the incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
Add R/W
7E
R/W
Function/
Description
RX FIFO
Control
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
37h
Both the TX and RX FIFOs may be cleared or reset with the ffclrtx and ffclrrx bits. All interrupts may be
enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and Register 06h. Interrupt Enable 2. If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin
but the bits will still be read correctly in the Interrupt Status registers.
32.6.2. Packet Configuration
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. "Register 30h. Data Access Control" through Register 4Bh. Received Packet Length control the configuration,
status, and decoded RX packet data for Packet Handling. The usual fields for network communication
(such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be automatically added to the data payload. The fields needed for packet generation normally change infrequently
and can therefore be stored in registers. Automatically adding these fields to the data payload greatly
reduces the amount of communication between the microcontroller and the transceiver.
Packet Length
Data
1-4 Bytes
466
CRC
0 or 2
Bytes
0 or 1 Byte
0-4 Bytes
1-255 Bytes
TX Header
Preamble
Sync Word
The general packet structure is shown in Figure 32.12. The length of each field is shown below the field.
The preamble pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields
have programmable lengths to accommodate different applications. The most common CRC polynominals
are available for selection.
Rev. 0.3
Si102x/3x
32.6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field
before returning to IDLE mode and asserting the packet sent interrupt. To resume sending data from the
FIFO the microcontroller needs to command the chip to re-enter TX mode. Figure 32.13 provides an example transaction where the packet length is set to three bytes.
D ata
D ata
D ata
D ata
D ata
D ata
D ata
D ata
D ata
1
2
3
4
5
6
7
8
9
}
}
}
Preamble
SYNC
DATA
Rev. 0.3
467
Si102x/3x
RX FIFO Contents:
Transmission:
rx_multi_pk_en = 0
rx_multi_pk_en = 1
Register
Data
Header(s)
txhdlen = 0
Register
Data
Length
txhdlen > 0
fixpklen
fixpklen
0
Data
H
H
FIFO
Data
Data
Data
Data
Data
Initial state
RX FIFO Addr.
0
PK 1 OK
Write
Pointer
RX FIFO Addr.
0
PK 2 OK
RX FIFO Addr.
0
H
L
Write
Pointer
PK 4 OK
RX FIFO Addr.
0
RX FIFO Addr.
0
H
L
H
L
Data
Data
Data
H
L
Data
H
L
Data
H
L
Data
H
L
Data
PK 3
ERROR
Write
Pointer
Write
Pointer
H
L
L
Data
Data
63
63
63
63
Write
Pointer
CRC
error
63
468
Rev. 0.3
Si102x/3x
Table 32.4. Packet Handler Registers
Add
R/W
Function/Description
D7
D6
D5
D4
D3
30
R/W
31
EzMAC status
32
R/W
Header Control 1
D2
D1
enpacrx
lsbfrst
crcdonly
skip2ph
rxcrc1
pksrch
pkrx
enpactx
encrc
pkvalid
crcerror
bcen[3:0]
D0
POR
Def
crc[1]
crc[0]
8Dh
pktx
pksent
hdch[3:0]
0Ch
33
R/W
Header Control 2
skipsyn
hdlen[2]
hdlen[1]
hdlen[0]
fixpklen
synclen[1]
synclen[0]
prealen[8]
22h
34
R/W
Preamble Length
prealen[7]
prealen[6]
prealen[5]
prealen[4]
prealen[3]
prealen[2]
prealen[1]
prealen[0]
08h
35
R/W
preath[4]
preath[3]
preath[2]
preath[1]
preath[0]
rssi_off[2]
rssi_off[1]
rssi_off[0]
2Ah
36
R/W
Sync Word 3
sync[31]
sync[30]
sync[29]
sync[28]
sync[27]
sync[26]
sync[25]
sync[24]
2Dh
D4h
37
R/W
Sync Word 2
sync[23]
sync[22]
sync[21]
sync[20]
sync[19]
sync[18]
sync[17]
sync[16]
38
R/W
Sync Word 1
sync[15]
sync[14]
sync[13]
sync[12]
sync[11]
sync[10]
sync[9]
sync[8]
00h
39
R/W
Sync Word 0
sync[7]
sync[6]
sync[5]
sync[4]
sync[3]
sync[2]
sync[1]
sync[0]
00h
3A
R/W
Transmit Header 3
txhd[31]
txhd[30]
txhd[29]
txhd[28]
txhd[27]
txhd[26]
txhd[25]
txhd[24]
00h
3B
R/W
Transmit Header 2
txhd[23]
txhd[22]
txhd[21]
txhd[20]
txhd[19]
txhd[18]
txhd[17]
txhd[16]
00h
3C
R/W
Transmit Header 1
txhd[15]
txhd[14]
txhd[13]
txhd[12]
txhd[11]
txhd[10]
txhd[9]
txhd[8]
00h
3D
R/W
Transmit Header 0
txhd[7]
txhd[6]
txhd[5]
txhd[4]
txhd[3]
txhd[2]
txhd[1]
txhd[0]
00h
3E
R/W
pklen[7]
pklen[6]
pklen[5]
pklen[4]
pklen[3]
pklen[2]
pklen[1]
pklen[0]
00h
3F
R/W
Check Header 3
chhd[31]
chhd[30]
chhd[29]
chhd[28]
chhd[27]
chhd[26]
chhd[25]
chhd[24]
00h
40
R/W
Check Header 2
chhd[23]
chhd[22]
chhd[21]
chhd[20]
chhd[19]
chhd[18]
chhd[17]
chhd[16]
00h
41
R/W
Check Header 1
chhd[15]
chhd[14]
chhd[13]
chhd[12]
chhd[11]
chhd[10]
chhd[9]
chhd[8]
00h
42
R/W
Check Header 0
chhd[7]
chhd[6]
chhd[5]
chhd[4]
chhd[3]
chhd[2]
chhd[1]
chhd[0]
00h
43
R/W
Header Enable 3
hden[31]
hden[30]
hden[29]
hden[28]
hden[27]
hden[26]
hden[25]
hden[24]
FFh
44
R/W
Header Enable 2
hden[23]
hden[22]
hden[21]
hden[20]
hden[19]
hden[18]
hden[17]
hden[16]
FFh
45
R/W
Header Enable 1
hden[15]
hden[14]
hden[13]
hden[12]
hden[11]
hden[10]
hden[9]
hden[8]
FFh
FFh
46
R/W
Header Enable 0
hden[7]
hden[6]
hden[5]
hden[4]
hden[3]
hden[2]
hden[1]
hden[0]
47
Received Header 3
rxhd[31]
rxhd[30]
rxhd[29]
rxhd[28]
rxhd[27]
rxhd[26]
rxhd[25]
rxhd[24]
48
Received Header 2
rxhd[23]
rxhd[22]
rxhd[21]
rxhd[20]
rxhd[19]
rxhd[18]
rxhd[17]
rxhd[16]
49
Received Header 1
rxhd[15]
rxhd[14]
rxhd[13]
rxhd[12]
rxhd[11]
rxhd[10]
rxhd[9]
rxhd[8]
4A
Received Header 0
rxhd[7]
rxhd[6]
rxhd[5]
rxhd[4]
rxhd[3]
rxhd[2]
rxhd[1]
rxhd[0]
4B
rxplen[7]
rxplen[6]
rxplen[5]
rxplen[4]
rxplen[3]
rxplen[2]
rxplen[1]
rxplen[0]
Rev. 0.3
469
Si102x/3x
Manchester
Whitening
CRC
CRC
(Over data only)
Preamble
Header/
Address
Sync
PK
Length
Data
CRC
1
1
Preamble = 0xFF
0
0
1
0
First 4bits of the synch. word = 0x2
Data after Machester ( manppol = 1, enmaninv = 0)
Data after Machester ( manppol = 1, enmaninv = 1)
0
0
Preamble = 0x00
0
0
1
0
First 4bits of the synch. word = 0x2
Data after Machester ( manppol = 0, enmaninv = 0)
Data after Machester ( manppol = 0, enmaninv = 1)
470
Rev. 0.3
Si102x/3x
amble detection threshold. A shorter Preamble Detection Threshold may be chosen if occasional false
detections may be tolerated. When antenna diversity is enabled a 20-bit preamble detection threshold is
recommended. When the receiver is synchronously enabled just before the start of the packet, a shorter
preamble detection threshold may be used. Table 32.5 demonstrates the recommended preamble detection threshold and preamble length for various modes.
It is possible to use the transceiver in a raw mode without the requirement for a 010101... preamble. Contact customer support for further details.
Approximate
Receiver
Settling Time
1 byte
2 byte
1 byte
64 bits
2 byte
8 byte
2 byte
3 byte
4 byte
8 byte
8 byte
Note: The recommended preamble length and preamble detection threshold listed above are to achieve 0% PER.
They may be shortened when occasional packet errors are tolerable.
Rev. 0.3
471
Si102x/3x
32.6.10. Receive Header Check
The header check is designed to support 14 bytes and broadcast headers. The header length needs to
be set in register 33h, hdlen[2:0]. The headers to be checked need to be set in register 32h, hdch[3:0]. For
instance, there can be four bytes of header in the packet structure but only one byte of the header is set to
be checked (i.e., header 3). For the headers that are set to be checked, the expected value of the header
should be programmed in chhd[31:0] in Registers 3F42. The individual bits within the selected bytes to be
checked can be enabled or disabled with the header enables, hden[31:0] in Registers 4346. For example,
if you want to check all bits in header 3 then hden[31:24] should be set to FF but if only the last 4 bits are
desired to be checked then it should be set to 00001111 (0F). Broadcast headers can also be programmed
by setting bcen[3:0] in Register 32h. For broadcast header check the value may be either FFh or the
value stored in the Check Header register. A logic equivalent of the header check for Header 3 is shown in
Figure 32.19. A similar logic check will be done for Header 2, Header 1, and Header 0 if enabled.
Equivalence
comparison
hden[31:24]
=
BIT
WISE
chhd[31:24]
bcen[3]
header3_ok
Equivalence
comparison
FFh
=
hdch[3]
rxhd[31:24]
472
Rev. 0.3
Si102x/3x
32.7. RX Modem Configuration
A Microsoft Excel parameter calculator or Wireless Development Suite (WDS) calculator is provided to
determine the proper settings for the modem. The calculator can be found on www.silabs.com or on the
CD provided with the demo kits. An application note is available to describe how to use the calculator and
to provide advanced descriptions of the modem settings and calculations.
Initial power on, VDD starts from gnd: reset is active till VDD reaches VRR (see table);
When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR;
A software reset via Register 08h. Operating Mode and Function Control 2: reset is active for time
TSWRST
On the rising edge of a VDD glitch when the supply voltage exceeds the following time functioned limit:
VDD nom.
VDD(t)
reset limit:
0.4V+t*0.2V/ms
actual VDD(t)
showing glitch
0.4V
Reset
TP
t=0,
VDD starts to rise
reset:
Vglitch>=0.4+t*0.2V/ms
Rev. 0.3
473
Si102x/3x
Table 32.6. POR Parameters
Parameter
Release Reset Voltage
Power-On VDD Slope
Low VDD Limit
Software Reset Pulse
Threshold Voltage
Reference Slope
VDD Glitch Reset Pulse
Symbol
Kommentar
VRR
Min
Typ
Max
Unit
0.85
1.3
1.75
SVDD
0.03
300
V/ms
VLD
VLD<VRR is guaranteed
0.7
1.3
TSWRST
50
470
us
VTSD
0.4
0.2
V/ms
16
25
ms
TP
The reset will initialize all registers to their default values. The reset signal is also available for output and
use by the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by
default on GPIO_1.
Add R/W
0A
R/W
Function/
Description
D7
D6
Output Clock
D5
D4
D3
clkt[1]
clkt[0]
enlfc
D2
Modulation Source
000
30 MHz
001
15 MHz
010
10 MHz
011
4 MHz
100
3 MHz
101
2 MHz
1 MHz
111
32.768 kHz
D0
mclk[2:0]
110
D1
POR Def.
06h
Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz
clock can be automatically switched to become the output clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in Register 0Ah. Microcontroller Output Clock." When enlfc =
1 and the chip is in SLEEP mode then the 32.768 kHz clock will be provided regardless of the setting of
mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin in all IDLE,
474
Rev. 0.3
Si102x/3x
TX, or RX states. When the chip enters SLEEP mode, the output clock will automatically switch to
32.768 kHz from the RC oscillator or 32.768 XTAL.
Another available feature for the output clock is the clock tail, clkt[1:0] in Register 0Ah. Microcontroller
Output Clock." If the low frequency clock feature is not enabled (enlfc = 0), then the output is disabled in
SLEEP mode. Setting the clkt[1:0] field will provide additional cycles of the output clock before it shuts off.
clkt[1:0]
Modulation Source
00
0 cycles
01
128 cycles
10
256 cycles
11
512 cycles
If an interrupt is triggered, the output clock will remain enabled regardless of the selected mode. As soon
as the interrupt is read the state machine will then move to the selected mode. The minimum current consumption will not be achieved until the interrupt is read. For instance, if the EZRadioPRO peripheral is
commanded to SLEEP mode but an interrupt has occurred the 30 MHz XTAL will not be disabled until the
interrupt has been cleared.
Rev. 0.3
475
Si102x/3x
Diff. MUX
Diff. Amp.
Input MUX
aoffs [4:0]
adcsel [2:0]
GPIO0
soffs [3:0]
adcgain [1:0]
GPIO1
GPIO2
8-bit ADC
Temperature Sensor
Vin
adcsel [2:0]
Vref
0 -1020mV / 0-255
Ref MUX
VDD / 3
VDD / 2
VBG (1.2V)
adc [7:0]
adcref [1:0]
hinzufügen
R/W
Function/
Description
D7
0F
R/W
ADC Configuration
adcstart/adcdone
10
R/W
Sensor Offset
11
ADC Value
adc[7]
D6
D5
adcsel[2] adcsel[1]
adc[6]
adc[5]
D4
D3
D2
adcsel[0]
adcref[1]
adcref[0]
soffs[3]
soffs[2]
soffs[1]
soffs[0]
00h
adc[3]
adc[2]
adc[1]
adc[0]
adc[4]
D1
D0
POR
Def.
adcgain[1] adcgain[0]
00h
476
Rev. 0.3
Si102x/3x
Add
R/
W
Function/
Description
D7
D6
D5
D4
D3
D2
12
R/W
Temperature
Sensor Control
tsrange[1]
tsrange[0]
entsoffs
entstrim
tstrim[3]
tstrim[2]
13
R/W
Temperature Value
Offset
tvoffs[7]
tvoffs[6]
tvoffs[5]
tvoffs[4]
tvoffs[3]
tvoffs[2]
D1
D0
POR
Def.
vbgtrim[1] vbgtrim[0]
tvoffs[1]
tvoffs[0]
20h
00h
tsrange[1]
tsrange[0]
Temp. range
Unit
Slope
ADC8 LSB
64 64
8 mV/C
0.5 C
64 192
4 mV/C
1 C
0 128
8 mV/C
0.5 C
40 216
4 mV/F
1 F
0*
0 341
3 mV/K
1.333 K
Note: Absolute temperature mode, no temperature shift. This mode is only for test purposes. POR value of
EN_TOFF is 1.
The slope of the temperature sensor is very linear and monotonic. For absolute accuracy better than 10 C
calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in Register
12h. Temperature Sensor Control and setting the offset with the tvoffs[7:0] bits in Register 13h. Temperature Value Offset. This method adds a positive offset digitally to the ADC value that is read in Register
11h. ADC Value. The other method of calibration is to use the tstrim which compensates the analog circuit. This is done by setting entstrim = 1 and using the tstrim[2:0] bits to offset the temperature in Register
12h. Temperature Sensor Control. With this method of calibration, a negative offset may be achieved.
With both methods of calibration better than 3 C absolute accuracy may be achieved.
The different ranges for the temperature sensor and ADC8 are demonstrated in Figure 32.22. The value of
the ADC8 may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest Temperature
in Temp Range. For instance for a tsrange = 00, Temp = ADC8Value x 0.5 64.
Rev. 0.3
477
Si102x/3x
Temperature Measurement with ADC8
300
250
ADC Value
200
Sensor Range 0
Sensor Range 1
150
Sensor Range 2
Sensor Range 3
100
50
0
-40
-20
20
40
60
80
100
Temperature [Celsius]
R/W
1B
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
lbdt[4]
lbdt[3]
lbdt[2]
lbdt[1]
lbdt[0]
14h
The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled (enlbd = 1 in "Register 07h.
Operating Mode and Function Control 1") the battery voltage may be read at anytime by reading "Register
1Bh. Battery Voltage Level." A battery voltage threshold may be programmed in Register 1Ah. Low Battery Detector Threshold". When the battery voltage level drops below the battery voltage threshold an
interrupt will be generated on nIRQ pin to the microcontroller if the LBD interrupt is enabled in Register
478
Rev. 0.3
Si102x/3x
06h. Interrupt Enable 2. The microcontroller will then need to verify the interrupt by reading the interrupt
status register, addresses 03 and 04h. The LSB step size for the LBD ADC is 50 mV, with the ADC range
demonstrated in the table below. If the LBD is enabled the LBD and ADC will automatically be enabled
every 1 s for approximately 250 s to measure the voltage which minimizes the current consumption in
Sensor mode. Before an interrupt is activated four consecutive readings are required.
< 1.7
1.71.75
1.751.8
29
3.13.15
30
3.153.2
31
> 3.2
WUT
32 M 2 R
ms
32 .768
WUT Register
Description
wtr[4:0]
R Value in Formula
wtm[15:0]
M Value in Formula
Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by
using the R value.
Rev. 0.3
479
Si102x/3x
Add R/W Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
wtr[4]
wtr[3]
wtr[2]
wtr[1]
wtr[0]
03h
14
R/W
15
R/W
00h
16
R/W
wtm[7]
wtm[6]
wtm[5]
wtm[4]
wtm[3]
wtm[2]
wtm[1] wtm[0]
00h
17
wtv[15]
wtv[14]
wtv[13]
wtv[12]
wtv[11]
wtv[10]
wtv[9]
wtv[8]
18
wtv[7]
wtv[6]
wtv[5]
wtv[4]
wtv[3]
wtv[2]
wtv[1]
wtv[0]
There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is
enabled in Register 06h. Interrupt Enable 2. If the WUT interrupt is enabled then nIRQ pin will go low
when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the
microcontroller clock output is available for the microcontroller to use to process the interrupt. The other
method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation
the chip will not change state until commanded by the microcontroller. The different modes of operating the
WUT and the current consumption impacts are demonstrated in Figure 32.23.
A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in Register 07h
"Operating & Function Control 1", GPIO0 is automatically reconfigured so that an external 32 kHz XTAL
may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so
only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set, all internal functions such as WUT, microcontroller clock, and LDC mode
will use the 32 kHz XTAL and not the 32 kHz RC oscillator.
The 32 kHz XTAL accuracy is comprised of both the XTAL parameters and the internal circuit. The XTAL
accuracy can be defined as the XTAL initial error + XTAL aging + XTAL temperature drift + detuning from
the internal oscillator circuit. The error caused by the internal circuit is typically less than 10 ppm.
480
Rev. 0.3
Si102x/3x
Interrupt Enable enwut =1 ( Reg 06h)
WUT Period
GPIOX =00001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Current
Consumption
Ready
Sleep
Ready
1.5 mA
Sleep
1.5 mA
1 uA
Ready
Sleep
1.5 mA
1 uA
1 uA
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Current
Consumption
1 uA
Rev. 0.3
481
Si102x/3x
between the WUT and the TLDC. The ldc[7:0] bits are located in Register 19h. Low Duty Cycle Mode
Duration. The time of the TLDC is determined by the formula below:
ldc [ 7 : 0 ]
TLDC
42R
ms
32 . 768
Add R/W
Function/
Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
0B
R/W
GPIO0
Configuration
gpio0drv[1] gpio0drv[0]
pup0
00h
0C
R/W
GPIO1
Configuration
gpio1drv[1] gpio1drv[0]
pup1
00h
0D
R/W
GPIO2
Configuration
gpio2drv[1] gpio2drv[0]
pup2
00h
0E
R/W
I/O Port
Configuration
extitst[2]
extitst[1] extitst[0]
itsdo
dio2
dio1
dio0
00h
The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000
default setting. The default settings for each GPIO are listed below:
GPIO
GPIO0
GPIO1
GPIO2
00000Default Setting
POR
POR Inverted
Output Clock
For a complete list of the available GPIOs see AN440: EZRadioPRO Detailed Register Descriptions.
The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase
the drive strength and current capability of the GPIO by changing the driver size. Special care should be
482
Rev. 0.3
Si102x/3x
taken in setting the drive strength and loading on GPIO2 when the microcontroller clock is used. Excess
loading or inadequate drive may contribute to increased spurious emissions.
Pin 6, ANT may be used as an alternate to control a TR switch. Pin 6 is a hardwired version of GPIO setting 11000, Antenna 2 Switch used for antenna diversity. It can be manually controlled by the antdiv[2:0]
bits in register 08h if antenna diversity is not used. See AN440, register 08h for more details.
R/W
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
ffclrtx
00h
RX/TX State
GPIO Ant1
GPIO Ant2
0
1
1
0
0
1
1
0
Antenna Diversity Algorithm
Antenna Diversity Algorithm
Antenna Diversity Algorithm in Beacon Mode
Antenna Diversity Algorithm in Beacon Mode
Rev. 0.3
483
Si102x/3x
an incorrect error may rarely occur. The RSSI value may be incorrect if read during the update period. The
update period is approximately 10 ns every 4 Tb. For 10 kbps, this would result in a 1 in 40,000 probability
that the RSSI may be read incorrectly. This probability is extremely low, but to avoid this, one of the following options is recommended: majority polling, reading the RSSI value within 1 Tb of the RSSI interrupt, or
using the RSSI threshold described in the next paragraph for Clear Channel Assessment (CCA).
Add R/W
Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
26
rssi[7]
rssi[6]
rssi[5]
rssi[4]
rssi[3]
rssi[2]
rssi[1]
rssi[0]
27
R/W
rssith[7]
rssith[6]
rssith[5]
rssith[4]
rssith[3]
rssith[2]
rssith[1]
rssith[0]
00h
For CCA, threshold is programmed into rssith[7:0] in "Register 27h. RSSI Threshold for Clear Channel
Indicator." After the RSSI is evaluated in the preamble, a decision is made if the signal strength on this
channel is above or below the threshold. If the signal strength is above the programmed threshold then the
RSSI status bit, irssi, in "Register 04h. Interrupt/Status 2" will be set to 1. The RSSI status can also be
routed to a GPIO line by configuring the GPIO configuration register to GPIOx[3:0] = 1110.
200
RSSI
150
100
50
0
-120
-100
-80
-60
-40
-20
20
In Pow [dBm]
484
Rev. 0.3
Rev. 0.3
485
GND
TRX1
SMA
CC1
SJ7
CM3
LM2
LM
CM
GND
0.1UF
2.2UF
L0
C16
C15
100pF
C17
C0
CR2
LR2
C18
33PF
L2 IS AN OPTIONAL PLACEMENT
PLACE INSTEAD OF R0 IF FILTERING IS NECESSARY
VDD_RF
LR
LC
RDC
CR1
GND
GPIO_2
GPIO_1
GPIO_0
ANT_A
SDN
P1.7
SJ3
1.0UF
GND
C9
A24
A23
A22
A21
A20
A19
A18
A17
A15
A16
GND
100pF
C10
GPIO_2
GPIO_1
GPIO_0
ANT_A
RXN
RXP
TX
VDD_RF
NC
SDN
GND
0.1UF
C11
VDD_RF
GND
C8
X5R
10UF
GND GND
IRQ
P1.6
U1
SI1024-A1-GM
SJ4
X1
32.768KHZ-7-T
P7.0/C2D
RSTB/C2CK
VIORF
VDC
GND
GNDDC
IND
VBATDC
VIO
VBAT
P4.1/LCD
P0.0/VREF/ADC0
P4.2/LCD10
P0.1/AGND/ADC1
P4.3/LCD11
P0.2/XTAL1/ADC2
P0.3/XTAL2/ADC3
P2.4/COM0
P2.5/COM1
P2.6/COM2
P5.6/LCD22
P2.7/COM3
P5.7/LCD23
P3.0/LCD0
P6.0/LCD24
P3.1/LCD1
P6.1/LCD25
P3.2/LCD2
P6.2/LCD26
P3.3/LCD3
P6.3/LCD27
P3.4/LCD4
P6.4/LCD28
P3.5/LCD5
P6.5/LCD29
P3.6/LCD6
P6.6/LCD30
P3.7/LCD7
P4.0/LCD8
GND
P6.7/LCD31
A48
A47
B29
A46
B28
A45
B27
A44
B26
A43
B25
A42
B24
A41
B23
A40
A39
VBAT
GND
R1
1K
P4.1/LCD9
P0.0/VREF
P4.2/LCD10
P0.1/AGND
P4.3/LCD11
P0.2/XTAL1
P0.3/XTAL2
P7.0/C2D
RST/C2CK
VDD_RF
C2
X7R
0.1UF
0.01UF
X7R
C6
GND
VDC
C3
X7R
0.01UF
CM2
L2
NO POP
0.0
R13
VRF
VDC
SJ6
E0
D2
D6
A14
A13
B11
A12
B10
A11
B9
A10
B8
A9
B7
A8
B6
A7
B5
A6
B4
A5
B3
A4
B2
A3
B1
A2
A1
D5
D1
Q2
GND_EPAD
GND
GND
XIN
XOUT
NIRQ
P2.4/COM0
P2.5/COM1
P2.6/COM2
P5.6/LCD22
P2.7/COM3
P5.7/LCD23
P3.0/LCD0
P6.0/LCD24
P3.1/LCD1
P6.1/LCD25
P3.2/LCD2
P6.2/LCD26
P3.3/LCD3
P6.3/LCD27
P3.4/LCD4
P6.4/LCD28
P3.5/LCD5
P6.5/LCD29
P3.6/LCD6
P6.6/LCD30
P3.7/LCD7
P4.0/LCD8
P6.7/LCD31
P6.7/LCD31
30MHz
NO POP
VR_DIG
P1.7/ADC11
VDD_DIG
P1.6/INT01/ADC10
P5.5/LCD21
P1.5/INT01/ADC9
P5.4/LCD20
P1.4/ADC8
P5.3/LCD19
VLCD
P5.2/LCD18
P1.3/XTAL4
GND
P1.2/XTAL3
GND
GND
P5.1/LCD17
P1.1/PC1
P5.0/LCD16
P1.0/PC0
P4.7/LCD15
P0.7/IREF/ADC7
P4.6/LCD14
P0.6/CNVSTR/ADC6
P4.5/LCD13
P0.5/RX/ADC5
P0.4/TX/ADC4
P4.4/LCD12
P4.4/LCD12
TZ1430A
R6
SJ5
P1.7
P1.6
P5.5/LCD21
P1.5/CTS
P5.4/LCD20
P1.4
P5.3/LCD19
P5.2/LCD18
NO POP
P1.3
P1.2
R5
VBAT
D3
D7
A25
A26
B12
A27
B13
A28
B14
A29
B15
A30
B16
A31
B17
A32
B18
A33
B19
A34
B20
A35
B21
A36
B22
A37
A38
D8
D4
P5.1/LCD17
P1.1/PC1
P5.0/LCD16
P1.0/PC0
P4.7/LCD15
P0.7/IREF0
P4.6/LCD14
P0.6/CNVSTR
P4.5/LCD13
P0.5/RX
P0.4/TX
P4.4/LCD12
0.1UF
X7R
C5
C1
X5R
2.2UF
2.2UF
X5R
C4
2
A
NO-POP
Z1
1
L1
0.56uH
GND
0.1UF
X7R
C13
VIO
VBAT
GND
Si102x/3x
GND
TRX
SMA
CM3
LM2
GND
C20
100pF
CM2
CC2
RX
1
CR2
GND
LM
GND
C15
2.2UF
X5R
LR
GND
CM
GND
CR1
RH
49.9
33PF
C18
CH
GND
100pF
0.1UF
L0
C17
C16
C0
LH
RDC
L2 IS AN OPTIONAL PLACEMENT
PLACE INSTEAD OF R0 IF FILTERING IS NECESSARY
VDD_RF
LC
ANT_A
GPIO_0
GPIO_1
GPIO_2
SDN
P1.7
XTL-SMT_TZ1430A_30MHZ
SJ3
C10
100pF
GPIO_2
GPIO_1
GPIO_0
ANT_A
RXN
RXP
TX
VDD_RF
NC
SDN
GND
C9
1.0UF
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
GND
GND_EPAD
E0
GND
C8
X5R
10UF
VDD_RF
C11
0.1UF
GNDGND
U1
SI1020-A1-GM
X1
32.768KHZ-7-T
P7.0/C2D
RSTB/C2CK
VIORF
VDC
GND
GNDDC
IND
VBATDC
VIO
VBAT
P4.1/LCD
P0.0/VREF/ADC0
P4.2/LCD10
P0.1/AGND/ADC1
P4.3/LCD11
P0.2/XTAL1/ADC2
P0.3/XTAL2/ADC3
P2.4/COM0
P2.5/COM1
P2.6/COM2
P5.6/LCD22
P2.7/COM3
P5.7/LCD23
P3.0/LCD0
P6.0/LCD24
P3.1/LCD1
P6.1/LCD25
P3.2/LCD2
P6.2/LCD26
P3.3/LCD3
P6.3/LCD27
P3.4/LCD4
P6.4/LCD28
P3.5/LCD5
P6.5/LCD29
P3.6/LCD6
P6.6/LCD30
P3.7/LCD7
P4.0/LCD8
SJ4
IRQ
R5
D2
D6
A14
A13
B11
A12
B10
A11
B9
A10
B8
A9
B7
A8
B6
A7
B5
A6
B4
A5
B3
A4
B2
A3
B1
A2
A1
D5
D1
P1.6
NO POP
GND
GND
XIN
XOUT
NIRQ
P2.4/COM0
P2.5/COM1
P2.6/COM2
P5.6/LCD22
P2.7/COM3
P5.7/LCD23
P3.0/LCD0
P6.0/LCD24
P3.1/LCD1
P6.1/LCD25
P3.2/LCD2
P6.2/LCD26
P3.3/LCD3
P6.3/LCD27
P3.4/LCD4
P6.4/LCD28
P3.5/LCD5
P6.5/LCD29
P3.6/LCD6
P6.6/LCD30
P3.7/LCD7
P4.0/LCD8
P6.7/LCD31
P6.7/LCD31
GND
P1.7
P1.6
P5.5/LCD21
P1.5/CTS
P5.4/LCD20
P1.4
P5.3/LCD19
P5.2/LCD18
R6
P1.3
P1.2
NO POP
VR_DIG
P1.7/ADC11
VDD_DIG
P1.6/INT01/ADC10
P5.5/LCD21
P1.5/INT01/ADC9
P5.4/LCD20
P1.4/ADC8
P5.3/LCD19
VLCD
P5.2/LCD18
P1.3/XTAL4
GND
P1.2/XTAL3
GND
GND
P5.1/LCD17
P1.1/PC1
P5.0/LCD16
P1.0/PC0
P4.7/LCD15
P0.7/IREF/ADC7
P4.6/LCD14
P0.6/CNVSTR/ADC6
P4.5/LCD13
P0.5/RX/ADC5
P0.4/TX/ADC4
P4.4/LCD12
P4.4/LCD12
GND
D3
D7
A25
A26
B12
A27
B13
A28
B14
A29
B15
A30
B16
A31
B17
A32
B18
A33
B19
A34
B20
A35
B21
A36
B22
A37
A38
D8
D4
P5.1/LCD17
P1.1/PC1
P5.0/LCD16
P1.0/PC0
P4.7/LCD15
P0.7/IREF0
P4.6/LCD14
P0.6/CNVSTR
P4.5/LCD13
P0.5/RX
P0.4/TX
P4.4/LCD12
Q2
P6.7/LCD31
A48
A47
B29
A46
B28
A45
B27
A44
B26
A43
B25
A42
B24
A41
B23
A40
A39
GND
1K
R1
VBAT
TX
100pF
SJ2
SJ1
U3
UPG2214TB
CC1
L2
NO POP
0.0
R13
4
3
VC2
OUT2
5
2
RF_IN GND
6
1
VC1
OUT1
C19
SJ7
SJ6
VRF
VDC
VBAT
SJ5
GPIO1 / VC1
Rev. 0.3
GPIO2 / VC2
486
0.1UF
X7R
C5
0.01UF
X7R
C6
P4.1/LCD9
P0.0/VREF
P4.2/LCD10
P0.1/AGND
P4.3/LCD11
P0.2/XTAL1
P0.3/XTAL2
P7.0/C2D
RST/C2CK
VDD_RF
C2
X7R
0.1UF
C3
X7R
0.01UF
VDC
C4
2.2UF
X5R
GND
C1
X5R
2.2UF
GND
C13
0.1UF
X7R
GND
VBAT
VIO
Z1
NO POP
L1
0.56uH
Si102x/3x
Si102x/3x
32.10. Application Notes and Reference Designs
A comprehensive set of application notes and reference designs are available to assist with the development of a radio system. A partial list of applications notes is given below.
For the complete list of application notes, latest reference designs and demos visit the Silicon Labs website.
For answers to common questions please visit the wireless and mcu knowledge base at
www.silabs.com/support/knowledgebase.
Rev. 0.3
487
Si102x/3x
32.12. Register Table and Descriptions
Table 32.9. EZRadioPRO Internal Register Descriptions
Add
R/W
Function/Desc
00
01
02
03
04
05
06
07
R
R
R
R
R
R/W
R/W
R/W
08
R/W
09
R/W
0A
0B
0C
0D
0E
0F
R/W
R/W
R/W
R/W
R/W
R/W
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
Device Type
Device Version
Device Status
Interrupt Status 1
Interrupt Status 2
Interrupt Enable 1
Interrupt Enable 2
Operating & Function Control 1
Operating & Function Control 2
Crystal Oscillator Load
Capacitance
Microcontroller Output Clock
GPIO0 Configuration
GPIO1 Configuration
GPIO2 Configuration
I/O Port Configuration
ADC Configuration
488
D7
0
0
ffovfl
ifferr
iswdet
enfferr
enswdet
swres
D6
0
0
ffunfl
itxffafull
ipreaval
entxffafull
enpreaval
enlbd
D5
0
0
rxffem
itxffaem
ipreainval
entxffaem
enpreainval
enwt
Data
D4
dt[4]
vc[4]
headerr
irxffafull
irssi
enrxffafull
enrssi
x32ksel
D3
dt[3]
vc[3]
reserved
iext
iwut
enext
enwut
txon
D2
dt[2]
vc[2]
reserved
ipksent
ilbd
enpksent
enlbd
rxon
D1
dt[1]
vc[1]
cps[1]
ipkvalid
ichiprdy
enpkvalid
enchiprdy
pllon
D0
dt[0]
vc[0]
cps[0]
icrcerror
ipor
encrcerror
enpor
xton
POR
Default
00111
06h
00h
03h
01h
antdiv[2]
antdiv[1]
antdiv[0]
rxmpk
autotx
enldm
ffclrrx
ffclrtx
00h
xtalshft
xlc[6]
xlc[5]
xlc[4]
xlc[3]
xlc[2]
xlc[1]
xlc[0]
7Fh
Reserved
gpio0drv[1]
gpio1drv[1]
gpio2drv[1]
Reserved
adcstart/adcdone
Reserved
adc[7]
tsrange[1]
tvoffs[7]
Reserved
wtm[15]
wtm[7]
wtv[15]
wtv[7]
ldc[7]
Reserved
gpio0drv[0]
gpio1drv[0]
gpio2drv[0]
extitst[2]
adcsel[2]
clkt[1]
pup0
pup1
pup2
extitst[1]
adcsel[1]
clkt[0]
gpio0[4]
gpio1[4]
gpio2[4]
extitst[0]
adcsel[0]
enlfc
gpio0[3]
gpio1[3]
gpio2[3]
itsdo
adcref[1]
mclk[2]
gpio0[2]
gpio1[2]
gpio2[2]
dio2
adcref[0]
mclk[1]
gpio0[1]
gpio1[1]
gpio2[1]
dio1
adcgain[1]
mclk[0]
gpio0[0]
gpio1[0]
gpio2[0]
dio0
adcgain[0]
06h
00h
00h
00h
00h
00h
Reserved
adc[6]
tsrange[0]
tvoffs[6]
Reserved
wtm[14]
wtm[6]
wtv[14]
wtv[6]
ldc[6]
Reserved
adc[5]
entsoffs
tvoffs[5]
Reserved
wtm[13]
wtm[5]
wtv[13]
wtv[5]
ldc[5]
Reserved
adc[4]
entstrim
tvoffs[4]
wtr[4]
wtm[12]
wtm[4]
wtv[12]
wtv[4]
ldc[4]
adcoffs[3]
adc[3]
tstrim[3]
tvoffs[3]
wtr[3]
wtm[11]
wtm[3]
wtv[11]
wtv[3]
ldc[3]
adcoffs[2]
adc[2]
tstrim[2]
tvoffs[2]
wtr[2]
wtm[10]
wtm[2]
wtv[10]
wtv[2]
ldc[2]
adcoffs[1]
adc[1]
tstrim[1]
tvoffs[1]
wtr[1]
wtm[9]
wtm[1]
wtv[9]
wtv[1]
ldc[1]
adcoffs[0]
adc[0]
tstrim[0]
tvoffs[0]
wtr[0]
wtm[8]
wtm[0]
wtv[8]
wtv[0]
ldc[0]
00h
20h
00h
03h
00h
01h
00h
Reserved
Reserved
Reserved
lbdt[4]
lbdt[3]
lbdt[2]
lbdt[1]
lbdt[0]
14h
0
dwn3_bypass
afcbd
0
ndec[2]
enafc
0
ndec[1]
afcgearh[2]
vbat[4]
ndec[0]
afcgearh[1]
vbat[3]
filset[3]
afcgearh[0]
vbat[2]
filset[2]
1p5 bypass
vbat[1]
filset[1]
matap
vbat[0]
filset[0]
ph0size
01h
40h
swait_timer[1]
Reserved
swait_timer[0]
Reserved
shwait[2]
crfast[2]
shwait[1]
crfast[1]
shwait[0]
crfast[0]
anwait[2]
crslow[2]
anwait[1]
crslow[1]
anwait[0]
crslow[0]
0Ah
03h
rxosr[7]
rxosr[6]
rxosr[5]
rxosr[4]
rxosr[3]
rxosr[2]
rxosr[1]
rxosr[0]
64h
rxosr[10]
rxosr[9]
rxosr[8]
stallctrl
ncoff[19]
ncoff[18]
ncoff[17]
ncoff[16]
01h
ncoff[15]
ncoff[14]
ncoff[13]
ncoff[12]
ncoff[11]
ncoff[10]
ncoff[9]
ncoff[8]
47h
ncoff[7]
ncoff[6]
ncoff[5]
ncoff[4]
ncoff[3]
ncoff[2]
ncoff[1]
ncoff[0]
AEh
Reserved
Reserved
Reserved
rxncocomp
crgain2x
crgain[10]
crgain[9]
crgain[8]
02h
crgain[7]
crgain[6]
crgain[5]
crgain[4]
crgain[3]
crgain[2]
crgain[1]
crgain[0]
8Fh
rssi[7]
rssi[6]
rssi[5]
rssi[4]
rssi[3]
rssi[2]
rssi[1]
rssi[0]
rssith[7]
rssith[6]
rssith[5]
rssith[4]
rssith[3]
rssith[2]
rssith[1]
rssith[0]
1Eh
adrssi1[7]
adrssib[7]
Afclim[7]
afc_corr[9]
afc_corr[9]
ookcnt[7]
Reserved
adrssia[6]
adrssib[6]
Afclim[6]
afc_corr[8]
afc_corr[9]
ookcnt[6]
attack[2]
adrssia[3]
adrssib[3]
Afclim[3]
afc_corr[5]
madeten
ookcnt[3]
decay[3]
adrssia[2]
adrssib[2]
Afclim[2]
afc_corr[4]
ookcnt[10]
ookcnt[2]
decay[2]
adrssia[1]
adrssib[1]
Afclim[1]
afc_corr[3]
ookcnt[9]
ookcnt[1]
decay[1]
adrssia[0]
adrssib[0]
Afclim[0]
afc_corr[2]
ookcnt[8]
ookcnt[0]
decay[0]
00h
00h
18h
BCh
26h
adrssia[5]
adrssia[4]
adrssib[5]
adrssib[4]
Afclim[5]
Afclim[4]
afc_corr[7]
afc_corr[6]
ookfrzen
peakdeten
ookcnt[5]
ookcnt[4]
attack[1]
attack[0]
Reserved
Rev. 0.3
Si102x/3x
Table 32.9. EZRadioPRO Internal Register Descriptions (Continued)
Add
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C-4E
4F
50-5F
60
R/W
Function/Desc
D7
enpacrx
0
Data
D6
D5
D4
lsbfrst
crcdonly
skip2ph
rxcrc1
pksrch
pkrx
bcen[3:0]
hdlen[2]
hdlen[1]
hdlen[0]
prealen[6]
prealen[5]
prealen[4]
preath[3]
preath[2]
preath[1]
sync[30]
sync[29]
sync[28]
sync[22]
sync[21]
sync[20]
sync[14]
sync[13]
sync[12]
sync[6]
sync[5]
sync[4]
txhd[30]
txhd[29]
txhd[28]
txhd[22]
txhd[21]
txhd[20]
txhd[14]
txhd[13]
txhd[12]
txhd[6]
txhd[5]
txhd[4]
pklen[6]
pklen[5]
pklen[4]
chhd[30]
chhd[29]
chhd[28]
chhd[22]
chhd[21]
chhd[20]
chhd[14]
chhd[13]
chhd[12]
chhd[6]
chhd[5]
chhd[4]
hden[30]
hden[29]
hden[28]
hden[22]
hden[21]
hden[20]
hden[14]
hden[13]
hden[12]
hden[6]
hden[5]
hden[4]
rxhd[30]
rxhd[29]
rxhd[28]
rxhd[22]
rxhd[21]
rxhd[20]
rxhd[14]
rxhd[13]
rxhd[12]
rxhd[6]
rxhd[5]
rxhd[4]
rxplen[6]
rxplen[5]
rxplen[4]
Reserved
Reserved
adc8[5]
adc8[4]
Reserved
Inv_pre_th[2] Inv_pre_th[1] Inv_pre_th[0]
R/W
Data Access Control
R
EzMAC status
R/W
Header Control 1
R/W
Header Control 2
R/W
Preamble Length
R/W Preamble Detection Control
R/W
Sync Word 3
R/W
Sync Word 2
R/W
Sync Word 1
R/W
Sync Word 0
R/W
Transmit Header 3
R/W
Transmit Header 2
R/W
Transmit Header 1
R/W
Transmit Header 0
R/W
Transmit Packet Length
R/W
Check Header 3
R/W
Check Header 2
R/W
Check Header 1
R/W
Check Header 0
R/W
Header Enable 3
R/W
Header Enable 2
R/W
Header Enable 1
R/W
Header Enable 0
R
Received Header 3
R
Received Header 2
R
Received Header 1
R
Received Header 0
R
Received Packet Length
skipsyn
prealen[7]
preath[4]
sync[31]
sync[23]
sync[15]
sync[7]
txhd[31]
txhd[23]
txhd[15]
txhd[7]
pklen[7]
chhd[31]
chhd[23]
chhd[15]
chhd[7]
hden[31]
hden[23]
hden[15]
hden[7]
rxhd[31]
rxhd[23]
rxhd[15]
rxhd[7]
rxplen[7]
R/W
ADC8 Control
Reserved
R/W
Inv_pre_th[3]
61
62
R/W
Crystal Oscillator/
Control Test
pwst[2]
pwst[1]
63-6C
6D
6E
6F
70
71
72
73
74
75
76
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
txdr[15]
txdr[7]
Reserved
trclk[1]
fd[7]
fo[7]
Reserved
Reserved
fc[15]
Reserved
txdr[14]
txdr[6]
Reserved
trclk[0]
fd[6]
fo[6]
Reserved
sbsel
fc[14]
77
R/W
TX Power
TX Data Rate 1
TX Data Rate 0
Modulation Mode Control 1
Modulation Mode Control 2
Frequency Deviation
Frequency Offset 1
Frequency Offset 2
Frequency Band Select
Nominal Carrier Frequency
1
Nominal Carrier Frequency
0
fc[7]
fc[6]
78
79
R/W
fhch[7]
fhch[6]
7A
R/W
fhs[7]
fhs[6]
7B
7C
7D
7E
7F
R/W
R/W
R/W
R/W
TX FIFO Control 1
TX FIFO Control 2
RX FIFO Control
FIFO Access
Reserved
Reserved
Reserved
fifod[7]
Reserved
Reserved
Reserved
fifod[6]
D3
enpactx
pkvalid
fixpklen
prealen[3]
preath[0]
sync[27]
sync[19]
sync[11]
sync[3]
txhd[27]
txhd[19]
txhd[11]
txhd[3]
pklen[3]
chhd[27]
chhd[19]
chhd[11]
chhd[3]
hden[27]
hden[19]
hden[11]
hden[3]
rxhd[27]
rxhd[19]
rxhd[11]
rxhd[3]
rxplen[3]
D2
D1
encrc
crc[1]
crcerror
pktx
hdch[3:0]
synclen[1]
synclen[0]
prealen[2]
prealen[1]
rssi_off[2]
rssi_off[1]
sync[26]
sync[25]
sync[18]
sync[17]
sync[10]
sync[9]
sync[2]
sync[1]
txhd[26]
txhd[25]
txhd[18]
txhd[17]
txhd[10]
txhd[9]
txhd[2]
txhd[1]
pklen[2]
pklen[1]
chhd[26]
chhd[25]
chhd[18]
chhd[17]
chhd[10]
chhd[9]
chhd[2]
chhd[1]
hden[26]
hden[25]
hden[18]
hden[17]
hden[10]
hden[9]
hden[2]
hden[1]
rxhd[26]
rxhd[25]
rxhd[18]
rxhd[17]
rxhd[10]
rxhd[9]
rxhd[2]
rxhd[1]
rxplen[2]
rxplen[1]
prealen[8]
prealen[0]
rssi_off[0]
sync[24]
sync[16]
sync[8]
sync[0]
txhd[24]
txhd[16]
txhd[8]
txhd[0]
pklen[0]
chhd[24]
chhd[16]
chhd[8]
chhd[0]
hden[24]
hden[16]
hden[8]
hden[0]
rxhd[24]
rxhd[16]
rxhd[8]
rxhd[0]
rxplen[0]
POR
Default
8Dh
0Ch
22h
08h
2Ah
2Dh
D4h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
D0
crc[0]
pksent
adc8[3]
adc8[2]
adc8[1]
adc8[0]
10h
chfiladd[3]
chfiladd[2]
chfiladd[1]
chfiladd[0]
00h
Reserved
pwst[0]
clkhyst
enbias2x
enamp2x
bufovr
enbuf
24h
Reserved
Reserved
Reserved
txdr[13]
txdr[12]
txdr[5]
txdr[4]
txdtrtscale
enphpwdn
dtmod[1]
dtmod[0]
fd[5]
fd[4]
fo[5]
fo[4]
Reserved
Reserved
hbsel
fb[4]
fc[13]
fc[12]
Ina_sw
txdr[11]
txdr[3]
manppol
eninv
fd[3]
fo[3]
Reserved
fb[3]
fc[11]
txpow[2]
txdr[10]
txdr[2]
enmaninv
fd[8]
fd[2]
fo[2]
Reserved
fb[2]
fc[10]
txpow[1]
txdr[9]
txdr[1]
enmanch
modtyp[1]
fd[1]
fo[1]
fo[9]
fb[1]
fc[9]
txpow[0]
txdr[8]
txdr[0]
enwhite
modtyp[0]
fd[0]
fo[0]
fo[8]
fb[0]
fc[8]
18h
0Ah
3Dh
0Ch
00h
20h
00h
00h
75h
BBh
fc[3]
fc[2]
fc[1]
fc[0]
80h
Reserved
fhch[5]
fhch[4]
fhch[3]
fhch[2]
fhch[1]
fhch[0]
00h
fhs[5]
fhs[3]
fhs[2]
fhs[1]
fhs[0]
00h
txafthr[3]
txaethr[3]
rxafthr[3]
fifod[3]
txafthr[2]
txaethr[2]
rxafthr[2]
fifod[2]
txafthr[1]
txaethr[1]
rxafthr[1]
fifod[1]
txafthr[0]
txaethr[0]
rxafthr[0]
fifod[0]
37h
04h
37h
fc[5]
fc[4]
fhs[4]
Reserved
txafthr[5]
txafthr[4]
txaethr[5]
txaethr[4]
rxafthr[5]
rxafthr[4]
fifod[5]
fifod[4]
Note: Detailed register descriptions are available in AN440: EZRadioPRO Detailed Register Descriptions.
Rev. 0.3
489
Si102x/3x
32.13. Required Changes to Default Register Values
The following register writes should be performed during device initialization.
1. The value 0x40 should be written to Register 59h.
2. If the device will be operated in the 240320 MHz or 480640 MHz bands at a temperature above
60 C, then Register 59h should be written to 0x43 and Register 5Ah should be written to 0x02.
490
Rev. 0.3
Si102x/3x
33. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 2 and
Timer 3 have a Capture Mode that can be used to measure the SmaRTClock, Comparator, or external
clock period with respect to another oscillator. The ability to measure the Comparator period with respect
to another oscillator is particularly useful when interfacing to capacitive sensors.
Timer 2 Modes:
Timer 3 Modes:
13-bit counter/timer
16-bit counter/timer
8-bit counter/timer with autoreload
Two 8-bit counter/timers (Timer 0
only)
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M
T0M) and the Clock Scale bits (SCA1SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 33.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12. Timer 2 may additionally be
clocked by the SmaRTClock divided by 8 or the Comparator0 output. Timer 3 may additionally be clocked
by the external oscillator clock source divided by 8 or the Comparator1 output.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a frequency of up to one-fourth the system clock frequency can be counted. The input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Rev. 0.3
491
Si102x/3x
SFR Definition 33.1. CKCON: Clock Control
Bit
Name
T3MH
T3ML
T2MH
T2ML
T1M
T0M
SCA[1:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
T3MH
Function
T3ML
T2MH
T2ML
T1M
T0M
1:0
492
Rev. 0.3
Si102x/3x
33.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register (Section 17.5. Interrupt Register Descriptions on page 241); Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register (Section 17.5. Interrupt Register Descriptions on page 241). Both
counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
GATE0
INT0
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 17.7).
Rev. 0.3
493
Si102x/3x
CKCON
T
3
M
H
P re -s ca le d C lo c k
SYSCLK
T
3
M
L
T
2
M
H
TM OD
T T T S S
2 1 0 C C
MMM A A
L
1 0
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
IT 0 1 C F
T
0
M
1
T
0
M
0
I
N
1
P
L
I
N
1
S
L
2
I
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
TCLK
TR0
TL0
(5 b its )
TH0
(8 b its)
G ATE0
C ro ss b a r
IN T 0
IN 0 P L
TCON
T0
TF1
TR1
TF0
TR0
IE 1
IT 1
IE 0
IT 0
Inte rru pt
XOR
494
Rev. 0.3
Si102x/3x
CKCON
T T T T T T S
3 3 2 2 1 0 C
MMMMMMA
H L H L
1
Pre-scaled Clock
TMOD
S
C
A
0
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
IT01CF
T
0
M
1
T
0
M
0
I
N
1
P
L
I
N
1
S
L
2
I
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
0
0
SYSCLK
1
1
T0
TL0
(8 bits)
TCON
TCLK
TR0
Crossbar
GATE0
TH0
(8 bits)
INT0
IN0PL
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Reload
XOR
Rev. 0.3
495
Si102x/3x
CKCO N
T T T T T T
3 3 2 2 1 0
MMMMMM
H L H L
Pre-scaled Clock
TM O D
S
C
A
1
S
C
A
0
G
A
T
E
1
C
/
T
1
T
1
M
1
T
1
M
0
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
0
TR1
SYSCLK
TH0
(8 bits)
1
TCON
1
T0
TL0
(8 bits)
TR0
Crossbar
INT0
G ATE0
IN0PL
XOR
496
Rev. 0.3
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
Si102x/3x
Name
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
TF1
TR1
TF0
TR0
IE1
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
IT1
IE0
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
IT0
Rev. 0.3
497
Si102x/3x
SFR Definition 33.3. TMOD: Timer Mode
Bit
Name
GATE1
C/T1
Typ
R/W
R/W
Zurücksetzen
T1M[1:0]
GATE0
C/T0
T0M[1:0]
R/W
R/W
R/W
R/W
GATE1
Function
C/T1
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4
T1M[1:0]
GATE0
C/T0
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0
T0M[1:0]
498
Rev. 0.3
Si102x/3x
Name
TL0[7:0]
Typ
R/W
Zurücksetzen
TL0[7:0]
Function
Name
TL1[7:0]
Typ
R/W
Zurücksetzen
TL1[7:0]
Function
Rev. 0.3
499
Si102x/3x
SFR Definition 33.6. TH0: Timer 0 High Byte
Bit
Name
TH0[7:0]
Typ
R/W
Zurücksetzen
TH0[7:0]
Function
Name
TH1[7:0]
Typ
R/W
Zurücksetzen
TH1[7:0]
Function
500
Rev. 0.3
Si102x/3x
33.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the SmaRTClock or
the Comparator 0 period with respect to another oscillator. The ability to measure the Comparator 0 period
with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 2 may be clocked by the system clock, the system clock divided by 12, SmaRTClock divided by 8, or
Comparator 0 output. Note that the SmaRTClock divided by 8 and Comparator 0 output is synchronized
with the system clock.
T2XCLK[1:0]
SYSCLK / 12
00
To ADC,
SMBus
To SMBus
01
TR2
Comparator 0
TCLK
TMR2L
TMR2H
TMR2CN
SmaRTClock / 8
TL2
Overflow
11
1
SYSCLK
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
Interrupt
T2XCLK
TMR2RLL TMR2RLH
Reload
Rev. 0.3
501
Si102x/3x
33.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 33.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
T2MH
T2XCLK[1:0]
00
TMR2H Clock
Source
T2ML
T2XCLK[1:0]
TMR2L Clock
Source
SYSCLK / 12
00
SYSCLK / 12
01
SmaRTClock / 8
01
SmaRTClock / 8
10
Reserved
10
Reserved
11
Comparator 0
11
Comparator 0
SYSCLK
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
CKCON
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0
T2XCLK[1:0]
SYSCLK / 12
00
SmaRTClock / 8
01
TMR2RLH
Reload
To SMBus
0
TCLK
TR2
11
TMR2RLL
SYSCLK
Reload
TMR2CN
Comparator 0
TMR2H
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
Interrupt
T2XCLK
1
TCLK
TMR2L
To ADC,
SMBus
502
Rev. 0.3
Si102x/3x
When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge
or every 8 SmaRTClock clock cycles, depending on the T2XCLK1 setting. When the capture event occurs,
the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2 reload registers
(TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrupts are enabled).
By recording the difference between two successive timer capture values, the Comparator 0 or SmaRTClock period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster
than the capture clock to achieve an accurate reading.
For example, if T2ML = 1b, T2XCLK1 = 0b, and TF2CEN = 1b, Timer 2 will clock every SYSCLK and capture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the SmaRTClock clock is as follows:
24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact SmaRTClock frequency in self-oscillate mode and the
time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the capacitance of a Touch Sense Switch.
T2XCLK[1:0]
CKCON
X0
Comparator 0
01
SmaRTClock / 8
11
0
TR2
T2XCLK1
SmaRTClock / 8
Comparator 0
TMR2L
TMR2H
Capture
SYSCLK
TCLK
TF2CEN
TMR2RLL TMR2RLH
TMR2CN
SYSCLK / 12
TTTTTTSS
3 3 2 2 1 0CC
MMMMMM A A
HLHL
1 0
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK1
T2XCLK0
Interrupt
Rev. 0.3
503
Si102x/3x
SFR Definition 33.8. TMR2CN: Timer 2 Control
Bit
Name
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK[1:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
1:0
T2XCLK[1:0]
504
Rev. 0.3
Si102x/3x
Name
TMR2RLL[7:0]
Typ
R/W
Zurücksetzen
Function
Name
TMR2RLH[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
505
Si102x/3x
SFR Definition 33.11. TMR2L: Timer 2 Low Byte
Bit
Name
TMR2L[7:0]
Typ
R/W
Zurücksetzen
Function
Name
TMR2H[7:0]
Typ
R/W
Zurücksetzen
Function
506
Rev. 0.3
Si102x/3x
33.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR2CN.3) defines
the Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator
source or the SmaRTClock oscillator period with respect to another oscillator.
Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator source
divided by 8, or the SmaRTClock oscillator. The external oscillator source divided by 8 and SmaRTClock
oscillator is synchronized with the system clock.
SYSCLK / 12
TTTTTTSS
3 3 2 2 1 0CC
MMMMMM A A
HLHL
1 0
00
To ADC
01
TR3
SmaRTClock
TCLK
TMR3L
TMR3H
TMR3CN
External Clock / 8
11
1
SYSCLK
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK1
T3XCLK0
Interrupt
TMR3RLL TMR3RLH
Reload
Rev. 0.3
507
Si102x/3x
33.3.2. 8-Bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figure 33.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or the SmaRTClock. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON)
select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in
TMR3CN), as follows:
T3MH
T3XCLK[1:0]
00
TMR3H Clock
Source
T3ML
T3XCLK[1:0]
TMR3L Clock
Source
SYSCLK / 12
00
SYSCLK / 12
01
SmaRTClock
01
SmaRTClock
10
Reserved
10
Reserved
11
External Clock / 8
11
External Clock / 8
SYSCLK
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H overflows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
CKCON
TT TTT TSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0
T3XCLK[1:0]
SYSCLK / 12
00
SmaRTClock
01
TMR3RLH
Reload
0
TCLK
TR3
11
TMR3RLL
SYSCLK
Reload
TMR3CN
External Clock / 8
TMR3H
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK1
T3XCLK0
Interrupt
1
TCLK
TMR3L
To ADC
508
Rev. 0.3
Si102x/3x
Setting TF3CEN to 1 enables the SmaRTClock/External Oscillator Capture Mode for Timer 3. In this mode,
T3SPLIT should be set to 0, as the full 16-bit timer is used.
When Capture Mode is enabled, a capture event will be generated either every SmaRTClock rising edge
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the difference between two successive timer capture values, the SmaRTClock or external clock period can be
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture
clock to achieve an accurate reading.
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and capture every SmaRTClock rising edge. If SYSCLK is 24.5 MHz and the difference between two successive
captures is 350 counts, then the SmaRTClock period is as follows:
350 x (1 / 24.5 MHz) = 14.2 s.
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or
the time between consecutive SmaRTClock rising edges, which is useful for determining the SmaRTClock
frequency.
T 3X C L K [1:0]
CKCON
X0
E xtern al C lock/8
01
S m a R T C lo ck
11
T T T S S
2 1 0 C C
MMM A A
1 0
L
TR 3
TCLK
T M R 3L
TM R3H
T M R 3R LL
T M R 3 R LH
C ap ture
T 3X C L K 1
T
2
M
H
S Y S C LK
S m aR T C loc k
T
3
M
L
TF3CEN
TMR3CN
S Y S C LK /12
T
3
M
H
T F 3H
TF3L
TF3LEN
TF3CEN
T 3 S P LIT
TR3
T 3X C L K 1
T 3X C L K 0
Interrupt
Rev. 0.3
509
Si102x/3x
SFR Definition 33.13. TMR3CN: Timer 3 Control
Bit
Name
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK[1:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
TF3H
Function
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
1:0
510
Rev. 0.3
Si102x/3x
Name
TMR3RLL[7:0]
Typ
R/W
Zurücksetzen
Function
Name
TMR3RLH[7:0]
Typ
R/W
Zurücksetzen
Function
Rev. 0.3
511
Si102x/3x
SFR Definition 33.16. TMR3L: Timer 3 Low Byte
Bit
Name
TMR3L[7:0]
Typ
R/W
Zurücksetzen
TMR3L[7:0]
Function
Name
TMR3H[7:0]
Typ
R/W
Zurücksetzen
TMR3H[7:0]
Function
512
Rev. 0.3
Si102x/3x
34. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between seven sources: system clock, system clock divided by
four, system clock divided by twelve, the external oscillator clock source divided by 8, SmaRTClock divided
by 8, Timer 0 overflows, or an external clock signal on the ECI input pin. Each capture/compare module
may be configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer,
High-Speed Output, Frequency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section 34.3. Capture/Compare Modules on page 516). The external oscillator clock option is ideal for realtime clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the
internal oscillator drives the system clock. The PCA is configured and controlled through the system controller's Special Function Registers. The PCA block diagram is shown in Figure 34.1
Important Note: The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 34.4 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
PCA
CLOCK
MUX
16-Bit Counter/Timer
External Clock/8
SmaRTClock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5 / WDT
CEX5
CEX4
CEX3
CEX2
CEX1
CEX0
ECI
Crossbar
Port I/O
Figure 34.1. PCA Block Diagram
Rev. 0.3
513
Si102x/3x
34.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a snapshot register; the following PCA0H read accesses this snapshot register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 34.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
CPS1
CPS0
Timebase
Timer 0 overflow
System clock
Reserved
Notes:
1. External oscillator source divided by 8 is synchronized with the system clock.
2. SmaRTClock oscillator source divided by 8 is synchronized with the system clock.
514
Rev. 0.3
Si102x/3x
IDLE
PCA0MD
CWW
I D D
DT L
L E C
K
CCCE
PPPC
SSSF
2 1 0
PCA0CN
CCCCCCCC
FRCCCCCC
FFFFFF
5 4 3 2 1 0
To SFR Bus
PCA0L
read
Snapshot
Register
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
SmaRTClock/8
000
001
0
010
PCA0H
PCA0L
Overflow
011
100
To PCA Modules
101
110
Rev. 0.3
515
Si102x/3x
(for n = 0 to 5)
PCA0CPMn
PCA0CN
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
CCCCCCCC
FRCCCCCC
FFFFFF
5 4 3 2 1 0
PCA0MD
C WW
I DD
DT L
LEC
K
PCA0PWM
A CE
ROC
S VO
EFV
L
CCCE
PPPC
SSSF
2 1 0
C
L
S
E
L
1
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
C
L
S
E
L
0
Set 8, 9, 10, or 11 bit Operation
ECCF0
PCA Module 0
(CCF0)
EPCA0
EA
Interrupt
Priority
Decoder
ECCF1
0
PCA Module 1
(CCF1)
ECCF2
0
PCA Module 2
(CCF2)
ECCF3
0
PCA Module 3
(CCF3)
ECCF4
0
PCA Module 4
(CCF4)
ECCF5
0
PCA Module 5
(CCF5)
Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode
PCA0CPMn
PCA0PWM
Bit Number 7 6 5 4 3 2 1 0 7 6 5
42
10
X X 1 0 0 0 0 A 0 X B XXX
XX
X X 0 1 0 0 0 A 0 X B XXX
XX
X X 1 1 0 0 0 A 0 X B XXX
XX
516
Rev. 0.3
Si102x/3x
Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode
PCA0CPMn
PCA0PWM
Software Timer
X C 0 0 1 0 0 A 0 X B XXX
XX
X C 0 0 1 1 0 A 0 X B XXX
XX
Frequency Output
X C 0 0 0 1 1 A 0 X B XXX
XX
0 C 0 0 E 0 1 A 0 X B XXX
00
0 C 0 0 E 0 1 A D X B XXX
01
0 C 0 0 E 0 1 A D X B XXX
10
0 C 0 0 E 0 1 A D X B XXX
11
1 C 0 0 E 0 1 A 0 X B XXX
XX
Notes:
1. X = Dont Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
Rev. 0.3
517
Si102x/3x
PCA Interrupt
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0 0 0 x
Port I/O
Crossbar
CEXn
CCC
CCC
FFF
2 1 0
(to CCFn)
x x
PCA0CN
CC
FR
PCA0CPLn
PCA0CPHn
Capture
0
1
PCA
Timebase
PCA0L
PCA0H
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
518
Rev. 0.3
Si102x/3x
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA Interrupt
ENB
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
x
0 0
PCA0CN
PCA0CPLn
CC
FR
PCA0CPHn
CCC
CCC
FFF
2 1 0
0 0 x
Enable
16-bit Comparator
PCA
Timebase
PCA0L
Match
0
1
PCA0H
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Rev. 0.3
519
Si102x/3x
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MPN n n n F
6 n n n
n
n
ENB
0 0
0 x
PCA Interrupt
PCA0CN
PCA0CPLn
Enable
CC
FR
PCA0CPHn
16-bit Comparator
Match
CCC
CCC
FFF
2 1 0
0
1
TOGn
Toggle
PCA
Timebase
0 CEXn
1
PCA0L
Crossbar
Port I/O
PCA0H
F PCA
F CEXn = ----------------------------------------2 PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
520
Rev. 0.3
Si102x/3x
Write to
PCA0CPLn
0
ENB
Zurücksetzen
PCA0CPMn
Write to
PCA0CPHn
ENB
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
x
0 0 0
PCA0CPLn
8-bit Adder
PCA0CPHn
Adder
Enable
TOGn
Toggle
x
Enable
PCA Timebase
8-bit
Comparator
match
0 CEXn
1
Crossbar
Port I/O
PCA0L
34.3.5.1.
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 34.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the modules capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 34.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
256 PCA0CPHn
Duty Cycle = --------------------------------------------------256
Equation 34.2. 8-Bit PWM Duty Cycle
Using Equation 34.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Rev. 0.3
521
Si102x/3x
Write to
PCA0CPLn
0
ENB
Zurücksetzen
PCA0CPHn
Write to
PCA0CPHn
ENB
COVF
PCA0PWM
A
R
S
E
L
EC
CO
OV
VF
0 x
C
L
S
E
L
1
PCA0CPMn
C
L
S
E
L
0
0 0
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0
0 0 x 0
PCA0CPLn
x
Enable
8-bit
Comparator
match
R
PCA Timebase
SET
CLR
CEXn
Crossbar
Port I/O
PCA0L
Overflow
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an AutoReload Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated modules capture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 34.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the modules auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in Equation 34.3, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
2 N PCA0CPn -
Duty Cycle = ------------------------------------------2N
Equation 34.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
522
Rev. 0.3
Si102x/3x
Write to
PCA0CPLn
R/W when
ARSEL = 1
ENB
Reset
Write to
PCA0CPHn
(Auto-Reload)
PCA0PWM
PCA0CPH:Ln
A
R
S
E
L
(right-justified)
ENB
C
L
S
E
L
1
EC
CO
OV
VF
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0
0 0 x 0
R/W when
ARSEL = 0
C
L
S
E
L
0
x
(Capture/Compare)
Set N bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
PCA0CPH:Ln
(right-justified)
x
Enable
N-bit Comparator
match
R
PCA Timebase
SET
CLR
CEXn
Crossbar
Port I/O
PCA0H:L
Overflow of Nth Bit
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
65536 PCA0CPn
Duty Cycle = ----------------------------------------------------65536
Equation 34.4. 16-Bit PWM Duty Cycle
Using Equation 34.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Rev. 0.3
523
Si102x/3x
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
ENB
PCA0CPMn
P EC
WCA
MOP
1 MP
6 n n
n
1
C
A
P
N
n
MT P
AOW
TGM
n n n
0 0 x 0
E
C
C
F
n
PCA0CPHn
PCA0CPLn
x
Enable
16-bit Comparator
match
R
PCA Timebase
PCA0H
SET
CLR
CEXn
Crossbar
Port I/O
PCA0L
Overflow
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is
loaded into PCA0CPH5. (See Figure 34.11.)
524
Rev. 0.3
Si102x/3x
PC A0M D
C
I
D
L
W
D
T
E
W
D
L
C
K
C
P
S
2
C
P
S
1
C E
P C
S F
0
PC A0C PH 5
Enable
PCA0CPL5
8-bit Adder
W rite to
PCA 0C PH 2
8-bit
C om parator
PC A 0H
M atch
R eset
PCA0L O verflow
Adder
Enable
The PCA clock source and idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 34.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 34.3 lists some example timeout intervals for typical system clocks.
Rev. 0.3
525
Si102x/3x
PCA0CPL5
24,500,000
255
32.1
24,500,000
128
16.2
24,500,000
32
4.1
3,062,5002
255
257
3,062,5002
128
129.5
3,062,5002
32
33.1
32,000
255
24576
32,000
128
12384
32,000
32
3168
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
526
Rev. 0.3
Si102x/3x
34.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
Name
CF
CR
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
CF
CR
5:0
Rev. 0.3
527
Si102x/3x
SFR Definition 34.2. PCA0MD: PCA Mode
Bit
Name
CIDL
WDTE
WDLCK
Typ
R/W
R/W
R/W
Zurücksetzen
CPS2
CPS1
CPS0
ECF
R/W
R/W
R/W
R/W
CIDL
Function
WDTE
WDLCK
4
3:1
Unused
ECF
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
528
Rev. 0.3
Si102x/3x
Name
ARSEL
ECOV
COVF
Typ
R/W
R/W
R/W
Zurücksetzen
ARSEL
CLSEL[1:0]
R/W
0
Function
ECOV
COVF
4:2
Unused
Rev. 0.3
529
Si102x/3x
SFR Definition 34.4. PCA0CPMn: PCA Capture/Compare Mode
Bit
Name
PWM16n
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
SFR Address, Page: PCA0CPM0 = 0xDA, 0x0; PCA0CPM1 = 0xDB, 0x0; PCA0CPM2 = 0xDC, 0x0
PCA0CPM3 = 0xDD, 0x0; PCA0CPM4 = 0xDE, 0x0; PCA0CPM5 = 0xCE, 0x0
Bit
Name
Function
7
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Note: When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the
watchdog timer. To change the contents of the PCA0CPM5 register or the function of module 5, the Watchdog
Timer must be disabled.
530
Rev. 0.3
Si102x/3x
Name
PCA0[7:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Function
7:0
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
Name
PCA0[15:8]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Function
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
Rev. 0.3
531
Si102x/3x
SFR Definition 34.7. PCA0CPLn: PCA Capture Module Low Byte
Bit
Name
PCA0CPn[7:0]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Bit
7:0
Note: A write to this register will clear the modules ECOMn bit to a 0.
Name
PCA0CPn[15:8]
Typ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Zurücksetzen
Bit
532
Rev. 0.3
Si102x/3x
35. C2 Interface
Si102x/3x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface
uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the
device and a host system. See the C2 Interface Specification for details on the C2 protocol.
Name
C2ADD[7:0]
Typ
R/W
Zurücksetzen
Bit
Name
Function
Address
Description
0x00
0x01
0x02
0xB4
Rev. 0.3
533
Si102x/3x
C2 Register Definition 35.2. DEVICEID: C2 Device ID
Bit
Name
DEVICEID[7:0]
Typ
R/W
Zurücksetzen
C2 Address: 0x00
Bit
Name
7:0
Function
Name
REVID[7:0]
Typ
R/W
Zurücksetzen
Varies
Varies
Varies
Varies
C2 Address: 0x01
Bit
Name
7:0
Varies
Varies
Varies
Varies
Function
534
Rev. 0.3
Si102x/3x
Name
FPCTL[7:0]
Typ
R/W
Zurücksetzen
C2 Address: 0x02
Bit
Name
7:0
Function
Name
FPDAT[7:0]
Typ
R/W
Zurücksetzen
C2 Address: 0xB4
Bit
Name
7:0
Function
Code
Command
0x06
0x07
0x08
0x03
Device Erase
Rev. 0.3
535
Si102x/3x
35.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely borrow the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 35.1.
C8051Fxxx
RST (a)
C2CK
Input (b)
C2D
Output (c)
C2 Interface Master
Figure 35.1. Typical C2 Pin Sharing
The configuration in Figure 35.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
536
Rev. 0.3
Si102x/3x
NOTES:
Rev. 0.3
537
Si102x/3x
CONTACT INFORMATION
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538
Rev. 0.3