What is DFT in VLSI?

Design-for-testability (DFT)

Why DFT?
 To make design testable and to find the physical defect in the silicon chip
after manufacturing.
 Attempt to reduce the high cost in time and effort required to generate test
vector sequences for VLSI circuits.

DFT Techniques
DFT techniques are broadly classified into two types:

Ad-hoc techniques
These are a collection of techniques or set of rules (do’s and don’ts) in the chip
design process learned from design experience to make design testability more
comfortable to accomplish.
Advantages
 Test vector generation is simplified
 Very easy to implement, no design rule or constraints and area overhead is
very less.
Drawbacks
 Are not always reusable, since each design has its specific requirements and
testability problems.
 It doesn’t guarantee high testability levels regardless of the circuit.
 Not systematic enough to enable a uniform approach to testable circuit
design.

Structured techniques
In this technique, extra logic and signals are added to the circuit to allow the test
according to some predefined procedure.
Advantage
In contrast to Ad-hoc, structured DFT implies that the same design approach can
always be used and assure good testability levels, regardless of the circuit function.
This technique is the only solution to modern world DFT problems.
Disadvantage
Usually consists of accepting that some design rules are enforced and that
additional silicon area and propagation delays are tolerated.

Examples
Following are a few examples of structured DFT which we will cover extensively
in future lessons:
 Scan Path
  Partial Scan
 Level Sensitive Scan
 BIST
 Boundary Scan

Scan chains – the backbone of DFT

What are scan chains: Scan chains are the elements in scan-based designs that are
used to shift-in and shift-out test data. A scan chain is formed by a number of flops
connected back to back in a chain with the output of one flop connected to another.
The input of first flop is connected to the input pin of the chip (called scan-in) from
where scan data is fed. The output of the last flop is connected to the output pin of
the chip (called scan-out) which is used to take the shifted data out.  A signal called
scan-enable is used to control which input will propagate to the output.
If scan-enable = 0, data at D pin of the flop will propagate to Q at the next active
edge
If scan-enable= 1, data present at scan-in input will propagate to Q at the next
active edge

Hence the circuit now has two operation modes: Normal mode and Test mode.
Normal Mode
 In normal mode, Scan Flip-Flops are configured to
perform capture operation.
Test Mode
 In test mode, the scan flip-flops are first configured to
perform shift operation so we can shift-in our test pattern.
 And then the scan flip-flops are configured to capture the response from the
logic.
 Finally, we configure the flip-flops to perform the shift-out operation so
that we can observe the values in the Scan flip-flops.

Purpose of testing using scan: Scan testing is carried out for various
reasons, two most prominent of them are: 

  To test stuck-at faults in manufactured devices 

  To test the paths in the manufactured devices for delay; i.e. to test whether
each path is working at functional frequency or not

The idea of the Internal Scan is to connect internal Flip-Flops and latches so that
we can observe them in test mode. Scan remains one of the most popular structured
techniques for digital circuits. This above process is known as Scan chain
Insertion. In the VLSI industry, it is also known as DFT Insertion or DFT
synthesis.
To enable scan test for a chip additional test logic must be inserted it is scan
insertion .

The steps involved in DFT synthesis are:

 Replace FF/latch
 Stitch FF/latch into a chain.

Tessent Scan Inputs and Outputs

Tessent Scan uses the following inputs:
 
• Design (netlist)
 — A Verilog gate-level netlist needs to be provided as input.
• Circuit Setup (or Dofile or Tcl file)
 — This is the set of commands that gives the tool information about the circuit
and how to insert test structures. You can issue these commands interactively in
the tool session or place them in a dofile or Tcl file. 
• Library
 — The Tessent Cell library contains descriptions of all the cells the design uses.
The library also includes information that the tool uses to map non-scan cells to
scan cells and to select components for added test logic circuitry.
• Input TCD File
 — If there are pre-existing scan segments that are described in a *.tcd_scanfile,
then you need to provide them as input to Scan Insertion. You can read them in
using the set_design_sources command. The full syntax of tcd_scan file is found in
Scan section of the Tessent Shell Reference Manual. Also, if there are CTL models
for pre-existing scan segments ,these can be converted using stil2mgc and then
read in.
• Test Procedure File
 — This file defines the stimulus for shifting scan data through the define scan
chains. This input is only necessary on designs containing pre-existing scan
circuitry or requiring initialization for test mode (test setup).
Tessent Scan produces the following outputs:
 
• Design (Netlist)
 — This netlist contains the original design modified with the inserted test
structures. The output netlist format is gate-level Verilog.
• TCD (Tessent Core Description)
 — This file contains all the Scan modes that were specified during scan insertion.
This file is used by ATPG tool to generate patterns. If any .tcd files from
a previous insertion pass or from a lower level core are read in, then the scan
modes are appended to the input *.tcd file and written out into the tsdb_outdir
directory.
Several scan_cells: muxed-D scan, clocked-scan, level-sensitive scan design
(LSSD);
muxed-D Scan cell: multi-fingered edge_triggered muxed-D scan cell, consisting
of a D flip-flop and a multiplexer,

A level-sensitive muxed-D scan cell consists of a multiplexer, a D Latch, and a D

FF to replace an ordinary latch.

Clocked-scan cell:

It is also mainly used to replace D-FF, but it is selected by two independent clks.
A data clock DCK; a shift clock SCK;
The main advantage is that it will not affect the timing of the data path, but
requires one more clock routing.

A typical scan implementation flow:

Clock mux and some resets are bypassed in Scan and cannot be detected. So the
test coverage of DFT is generally at 97% or 98%.
 
Scan design rule checking and repair:

It can be done on pre-synthesis RTL design or post-synthesis gate-level design,

The design after scan repair is called testable design.
Scan synthesis converts a testable design into a scan design. Currently, the design
contains several scan chains.
Scan extraction is to extract the structure of the final scan chain for use by ATPG.
Scan verification performs response verification for shift and capture operations.
 

Scan Design Rule Checking and Repair

Check the scan design rule, and some clock control structures need to be modified
to increase the at-speed test.
The check of the scan design rule can also be done after the scan synthesis to
ensure that no new violations appear.
In the shift operation, all clocks can be controlled by external pins, between two
adjacent scan cells
Clock skew must be guaranteed not to cause shift failures.
In the capture operation, the originate/terminate clock of the data path may be
different, which needs to be considered
Timing to ensure the correct operation of capture.
 
Scan Synthesis
Scan synthesis transforms a testable design into a scan design.
In 1990, the operation of scan synthesis was some scattered tools, and the
Gate_level after logic synthesis
Netlist for processing.
Recently, the operation of scan synthesis has been integrated in logic synthesis,
such processing is called one-pass
Synthesis or single-pass synthesis.

It mainly includes four parts:

1) Scan configuration;
2) Scan replacement;
3) Scan reordering;
4) Scan stitching;

Scan Replacement:
After scan configuration, scan replacement replaces storage element with
functionally equivalent scan cell
The design at this time is called scan-ready design.
The inputs of these scan cells are usually connected to the outputs of the same scan
cell to avoid floating. These connections are removed at the stitch stage.
Currently, partial scan replacement can also be implemented in the RTL stage.
 
Scan Reordering
Reacts the reorder of scan cells in the scan chain. Before physical implementation,
a random scan order is used by design.
When performing physical implementation, scan order can use intra_scan_chain
reordering (scan cell is only in this scan
Re order within the chain) and inter_scan_chain reordering (scan cell reorder
between different scan chains)
 

Scan stitching
Stitch all scan cells together to form a scan chain. Connect the output of each scan
cell to the input of the next level.
Connect the input of the first scan cell to the primary input, and the output of the
last scan cell to the primary output.
In the process of stitching, some lock_up latches and lock_up FFs need to be
inserted to ensure that the shift operation is correct.
After scan stitch, scan synthesis has been completed,
Scan extraction is mainly used to extract all instances from scan design to ensure
the integrity of the scan chain.
And ensure that all design changes are integrated into scan design.
 
Scan Verification
1) Hold time violation in shift operate, if two scan cells are at the same clock, CTS
is required to ensure that there is a clock skew
The value of minimum. If the clock is an asynchronous clock, the lock_up latch
needs to be inserted.
2) Wrong scan initialization sequence, cannot enter test mode.
3) Check and repair of incomplete scan design rule, set/reset of reg and enable/gate
of clock, etc.
4) The error of scan synthesis, put the positive before the negative, etc.

Scan Design Costs:

Area overhead cost, I/O pin cost, Performance degradation cost, and Design effort
cost.

Tessent TestKompress is a Design-for-Test (DFT) product that creates test patterns

and implements compression for the testing of manufactured ICs. Advanced
compression reduces ATE memory and channel requirements and reduced data
volume results in shorter test application times and higher tester throughput than
with traditional ATPG. TestKompress also supports traditional ATPG.

Tessent TestKompress creates and embeds compression logic (EDT logic) and
generates compressed test patterns as follows:

Tessent TestKompress Inputs

• Scan-inserted gate-level Verilog netlist.
• Synthesis tool
• Compatible Tessent cell library of the models used for your design scan circuitry

 Timing simulator such as ModelSim.

EDT technology consists of logic embedded on-chip, new EDT-specific DRCs,

and a deterministic pattern generation technique. The embedded logic includes a
decompressor located between the external scan channel inputs and the internal
scan chain inputs and a compactor located between the internal scan chain outputs
and the external scan channel outputs.

TestKompress Compression Logic

Tessent TestKompress generates hardware in blocks in VHDL or Verilog RTL.

You integrate the compression logic (EDT logic) into your design by using Tessent
Shell with the core level of the design. The tool then generates the following three
components:

• Decompressor — Feeds a large number of scan chains in your core design from a
small number of scan channels, and decompresses EDT scan patterns as they are
shifted in.
The decompressor resides between the channel inputs (connected to the tester) and
the scan chain inputs of the core. Its main parts are an LFSM and a phase shifter.
• Compactor — compacts the test responses from the scan chains in your core
design into a small number of scan output channels as they are shifted out. The
compactor resides between the core scan chain outputs and the channel outputs
connected to the tester. It primarily consists of spatial compactor(s) and gating
logic.
But there are two problems that we may encounter –
a. ‘X’ contamination due to unknown value propagation
b. Fault Aliasing due to bad Probability of Aliasing (PAL)
a fault is aliased when it is observed by an even number of scan cells
that happened to line up at the same location in different scan chains
that are compacted to the same output channel.

To deal with these issues, a mask controller is also found as a part of

compactor logic. This mask controller along with masking logic at the
scan chain output can selectively mask scan chains based on few bits
(called mask code) at the end of the pattern shifted-in, that don’t make it
to the decompressor.

• Bypass Module (Optional) — Bypasses the EDT logic by using multiplexers

(and lockup cells if necessary) to concatenate the internal scan chains into fewer,
longer chains. Enables you to access the internal scan chains directly through the
channel pins. Generated by default.

Bypassing the EDT logic enables you to apply uncompressed test patterns to the
design to:
• Debug compressed test patterns.
• Apply additional custom uncompressed scan chains.
• Apply test patterns from other ATPG tools.
Bypass logic can also be inserted in the core netlist at scan insertion time. This
allows you to place the multiplexers and lockup cells required to operate the
bypass mode inside the core netlist instead of the EDT logic.

Test Data Volume ≈ Number of Scan Cells in all the Scan Chains × Scan
Patterns

ATPG stands for Automatic Test Pattern Generation. Test patterns, sometimes
called test vectors, are sets of 1s and 0s placed on primary input pins during the
manufacturing test process to determine if the chip is functioning properly. When
the test pattern is applied, the Automatic Test Equipment (ATE) determines if the
circuit is free from manufacturing defects by comparing the fault-free output—
which is also contained in the test pattern—with the actual output measured by the
ATE.

The goal of ATPG is to create a set of patterns that achieves a given test coverage,
where test coverage is the total percentage of testable faults the pattern set actually
detects.

ATPG consists of two main steps: 1) generating patterns and, 2) performing fault
simulation to determine which faults the patterns detect. The two most typical
methods for pattern generation are random and deterministic.

Random Pattern Test Generation

An ATPG tool uses random pattern test generation when it produces a number of
random patterns and identifies only those patterns that detect faults. It then stores
only those patterns in the test pattern set.

Deterministic Pattern Test Generation

An ATPG tool uses deterministic test pattern generation when it creates a test
pattern intended to detect a given fault. The procedure is to pick a fault from the
fault list, create a pattern to detect the fault, fault simulate the pattern, and check to
make sure the pattern detects the fault.

ATPG Tool Inputs and Outputs the ATPG tool uses multiple inputs to produce test
patterns, a fault list, and ATPG information files.

Inputs :
Design
The supported design data format is gate-level Verilog. Other inputs also include
1) a cell model from the design library and 2) a previously-saved, flattened model.

Test Procedure File

This file defines the operation of the scan circuitry in your design. You can
generate this file by hand, or Tessent Scan can create this file automatically when
you issue the command write_atpg_setup.

Library
The design library contains descriptions of all the cells used in the design. The tool
uses the library to translate the design data into a flat, gate-level simulation model
for use by the fault simulator and test generator.

Fault List
The tool can read in an external fault list. The tool uses this list of faults and their
current status as a starting point for test generation.

Test Patterns
The tool can read in an external fault list. The tool uses this list of faults and their
current status as a starting point for test generation.

Outputs:
Test Patterns
The tool generates files containing test patterns. They can generate these patterns
in a number of different simulator and ASIC vendor formats.

ATPG Information Files

These consist of a set of files containing information from the ATPG session. For
example, you can specify creation of a log file for the session.

Fault List
This is an ASCII-readable file that contains internal fault information in the
standard Mentor Graphics fault format.

What is on-chip clock control in DFT (VLSI)?

On -chip clock controller is the logic inserted on the SOC for controlling clocks
during silicon testing for defects on ATE (Automatic test Equipment). OCC
enables the AT-speed/Transition testing of the Logic by generating two clock
pulses at speed during capture phase. So OCC enables the pulse control of the
clock during Test mode through clock chain (chain comprising all the OCC logic
flops in a chain)
Without OCC you need to provide At-speed pulses through Top pins called PADS.
But Pads has limitation in terms of maximum frequency they can support. OCC on
other hand uses internal PLL clock for generating 2 pulses for test.

The standard OCC performs all three OCC functions: clock selection, clock
chopping control, and clock gating.

Depending on your design style, you may need to guide the Clock Tree Synthesis
(CTS) not to balance the flops and latches in the OCC with the clock tree it drives.

What is the difference between clock skew and clock jitter?

Clock skew is two different flip flops receive the clock signal at slightly different
time due to difference in clock net length but clock jitter is on the same flip flop
but the position of clock edge moves edge to edge due to some noise in oscillator.

Clock skew (timing skew) is a phenomenon in synchronous digital circuit systems

in which the same sourced clock signal arrives at different components at different
times.
.
Clock Latency: Clock latency is only good till the clock source. So it is the delay
that is attributed to a particular clock till the clock source point.

Clock Jitter: Sometimes some external sources like noise, voltage variations may
cause to disrupt the natural periodicity or frequency of the clock. This deviation
from the natural location of the clock is termed to be clock jitter.

Clock Uncertainty: Most EDA simulators treat clock uncertainty as cumulative

sum for clock skew and jitter.
Clock Uncertainty = Clock Jitter + Clock Skew

Setup Time: If the data or signal changes just before the active edge of the clock
then we say that setup time has been violated.
Hold Time: If the data or signal changes after the active edge of the clock then we
say that hold time has been violated.

Setup time is frequency dependent (depends on clock period) whereas hold time is
frequency independent (doesn’t depends on clock period).

Which violation is more dangerous setup time or hold time in VLSI?

Hold violation is more dangerous than setup violation .Because after timing
closure also we can adjust the frequency .so by that we can avoid setup viol .but
hold violation is not dependent on frequency.

Setup Time and Hold Time: If the data or signal changes just before and after the
active edge of the clock respectively then we say that setup time/ hold time has
been violated.
Causes for Setup Time: Setup violations can happen as a result of slow conditions
(slow process, high temperature) leading to signals arriving too late in the clock
period.
Strategy to Fix Setup Time: Reduce Delay.
 Try to make use of libraries derived from NAND logic.
 Restructuring/Re-timing would be the best way to optimize the logic.
 For a critical path with a capture flop and a launch flop.
Causes for Hold Time Violations: Hold violations can happen as a result of fast
conditions (fast process, low temperature) leading to signals arriving too early in
the clock period.
Strategy to Fix Hold Time:
 Insert buffers. 
 Use data-path cells with higher threshold voltages.
 Lock up Latches
 A positive skew degrades hold timing and a negative skew aids hold timing.
False paths:
Paths in the design which doesn't require timing analysis are called false paths.

 Multicycle path:
Paths in the design which can have some timing exception to propagate from the
start point to end point for specific number of clocks. Which means the data from
start point to end point will changes only once per specified number of clock, those
paths are called multicycle paths.

Clock gating logic can also be used to generate the clock pulse. In many circuits,
clock gating logic serving multiple purposes like reduce power consumption and
improve design performance
Clock gating is a common technique for reducing clock power by shutting off the
clock to modules by a clock enable signal. Clock gating functionally requires only
an AND or OR gate.

What are the challenges with clock gating?

1. Circuit timing changes
2. Area penalty (additional logic is added)
3. Equivalency checking (especially for sequential clock gating)
4. Clock domain crossing issues
5. Reset domain crossing issues
6. Complicate timing closure due to additional delay at clock network.
7. As these changes are local to power domains, I don’t think any impact can
come from power states. I am not sure of any impact if the clock gating
applied at an architectural level?
8. DFT methodology changes. The test enable mux can be inserted pre OR
post of latch in clock gating cell.

How does integrated clock gating cell (ICG) prevent glitching?

 Produces an uninterrupted gated clock signal in cases where glitches occur in the
enable signal during clock transitions.

Since the enable signal can change any time, which may not be synchronous with
the clock signal, it can cause a glitch in the gated clock. To avoid this
situation, a latch is added in front of the logic gate in order to synchronize the
enable signal with the clock edge.

There are two types of clock gating styles available. They are: 1) Latch-based
clock gating 2) Latch-free clock gating. The latch-free clock gating style uses a
simple AND or OR gate (depending on the edge on which flip-flops are triggered).

What is fault equivalence, fault collapsing, and fault simulation in (VLSI)

DFT?

While creating fault site list, tool identifies fault which are dependent to each other
and consider them as equivalent faults.

If 4 faults are equivalent, then tool mark one of them as a real fault and rest three
of them are marked as collapsed to the real fault. This concept is called fault
collapsing.

After we generate all the test patterns, we need to validate those test patterns. So,
we can trust those test patterns as golden test patterns. Thus we run simulation
those test patterns with fault. This process is called fault simulation.
What is launch off shift and launch off capture in DFT? (VLSI)

In scan based DFT, we do testing in following format:

1. Shift-in the pattern until the stimulus reaches fault site by keeping shift
enable =1.
2. Have a lunching clock pulse at the fault site, which will feed the pattern to
fault site.
3. Capture the response from the fault site with given pattern.
4. Shift-out the response to the scan out pin by keeping shift enable =1.

If we have the lunching clock pulse with Shift enable =1 then we call it Lunch off
shift (LOS). Similarly, If we have the lunching clock pulse with Shift enable =0
then we call it Lunch off capture (LOC). Both method will test the fault site but
they have their own pros and cons.

Lunch off shift (LOS):

This is the simplest method to adopt for scan. With this the size of generated
pattern will be low. But the shift enable goes from high to low in between lunching
and capturing pulses. So, if we want to run at-speed test of a high speed circuit it
will critical case for lowering shift enable for all flops. So, in industry people
mostly use LOS patterns to test stuck-at faults.

Lunch off capture (LOC):

Unlike LOS, here we do both lunching and capturing with shift enable =0. So, we
can test the circuit at high frequency without touching shift enable. But these type
of test vector comes with higher memory size, and need better and expensive ATE
setup.
On what basis do we select LOS or LOC in DFT? Is there any major run time
difference too in the execution of these two concepts?

It is necessary that the timing path should be same as the functional path. i.e.,
clocks should be the same in both functional & at-speed test mode. Whatever
methodology (Launch on Shift / Launch on Capture) is required to meet this
requirement should be implemented. There are other critical factors that will also
drive to LOS / LOC implementation.

1. Whether clocks are generated by internal PLLs.

2. Whether, tester can support multiple waveforms on the same clock pin.
3. How do you handle scan enable to switch between shift & capture modes.
FYI, most of the designs that have internal clock generators implement LOC
method for testing.
Below are differences between the LOC and LOS

a) For LOS the scan enable has to closed at functional frequency (which may result
in gate count increase with addition of large buffers), whereas in LOC the timing
on scan enable can relaxed between the last shift and launch cycle.
b) LOS atpg run time is less compared to the LOC for pattern generation.
c) Pattern count in LOS in less than the LOC.
d) Test/fault coverage for LOS is higher than the LOC.

Transition ATPG is meant for detecting slow-to-rise and slow-to-fall faults on a

particular node. In order to detect the transition fault, we have to create the
transition on the node. We can achieve this in two ways

I) Launch on last shift - In this method, during the last shift itself, we will shift in
the required value in to the flop which will create the required transition on the
intended node.

Advantages: 1) Tool has the controllability to put the required value in to the flop
to cause transition.

2) We will get good coverage as we are launching the value through SD path.
Disadvantages: 1) Scan-enable need to change at-speed, we have to implement

pipeline logic in order to support this.

II) Launch on capture - In this method, the flop which creates the launch on the
intended node will get the value through D path. Scan-enable will be low during
this time.

Advantages: 1) No need to add pipeline logic for Scan-enable.

Disadvantages: 1) We may lose some coverage as the value is launched through D
path.
It’s always better to go with LOS, The major advantage with LOS is increased
coverage and reduction in number of patterns. When the no of patterns decreases,
the test time reduces, which in turn reduces the cost for test time to a great extent.

A fault model tries to model the impact of different type of physical effects which
can occur on silicon. Corresponding to the type of fault which we are targeting,
different type of fault models are used. Following are some commonly used fault
models
1. Single Stuck at 0 /Single stuck at 1
2. Multiple stuck at
3. Bridging
4. Stuck Open
5. Transition fault model
6. Path delay fault model

1.  Stuck-at Faults
This is the most common fault model used in industry. It models manufacturing
defects which occurs when a circuit node is shorted to VDD (stuck-at-1 fault) or
GND (stuck-at-0 fault) permanently. The fault can be at the input or output of a
gate.

 2.  At-speed Faults
It models the manufacturing defects that behave as gross delays on gate input-
output ports. So each port is tested for logic 0-to-1 transition delay (slow-to-rise
fault) or logic 1-to-0 transition delay (slow-to-fall fault). Like stuck-at faults, the
at-speed fault can be at the input or output of a gate. The reason for transition-delay
at a node is some manufacturing defect at that node (more resistive node). The
reason for path-delay is some manufacturing defect that is distributed throughout
the path (more resistive path).

3. Bridging fault model:

 This is a new model which is gaining importance. In this case any two close lying
net may effect the value of each other. There is generally a victim and another is
a aggressor, so an aggressor forces some value on the victim. We first find the
coupling capacitance of each net pair, then depending on the specs we may select
some nets which have coupling capacitance more than specified value, these
are selected and then these become the fault locations for the ATPG.

4. Iddq fault model:

 This is similar to the stuck at fault model but here instead of measuring the voltage
we measure the current. In a CMOS design at the quiescent state, ideally there is
supposed to no current in the silicon, if there is current then some node has either
shorted to ground or to the power.

What is meant by coverage in DFT terminology?

  The term coverage can be broadly classified as:
1. Fault Coverage: This is the total number of detected faults (during testing)
divided by the total number of faults in the design.
2. Test coverage: This is the total number of detected faults divided by the number
of testable faults in the design. Testable faults are the faults in the design that can
be tested and observed by the patterns used during testing

Fault Coverage is percentage of detected fault from all fault in design.

And Test coverage is percentage of detected fault from detectable fault in design
Detectable fault not contain the fault which are Tied, unused or redundant
Test Coverage is a percentage detected of all detectable faults and gives the most
meaningful measure of test pattern quality.

Test Coverage=DT+(NP+AP)*PT_credit)/(total faults-UD-(AN*AU_credit)

Fault Coverage: the fault coverage is the percentage detected of all faults.it gives
no credit for undetectable faults.
Fault Coverage=(DT+(NP+AP)*PT_credit)/total faults.
DT-Detected
-DR-detected robustly
-DS-detected by simulation-
DI-Detected by implication
PT-Possibly detected
-AP-ATPG untestable possibly detected.
NP-not analysed, possibly detected.
UD-Undetectable
-UU-undectable unused-
UT-Undectable tied-
UB undetectable tied-
UR undetectable redundant 
AU-ATPG untestable-
AN-ATPG untestable not detected.
ND- not detected-
NC-not controlled.-
NO-not observed.

62. How to toggle reset to get coverage?

If the reset is asynchronous (and properly bypassed during scan), you can declare
the reset pin as a clock during ATPG, and ATPG will toggle it accordingly to get
faults on reset pin. If the reset is synchronous, you can treat the reset pin as
a normal data pin, and ATPG should be able to cover faults on the reset. Be
careful, however, if you run transition fault ATPG. Reset usually cannot toggle at-
speed, so you may not want to declare the reset as a clock when running transition
fault ATPG.You can also try to run the patterns that toggle the reset as a clock pin
at a reduced speed on the tester, if you worry about transition fault coverage on
reset.

What are lock-up latches: Lock-up latch is an important element in scan-based

designs, especially for hold timing closure of shift modes. Lock-up latches are
necessary to avoid skew problems during shift phase of scan-based testing. A lock-
up latch is nothing more than a transparent latch used intelligently in the places
where clock skew is very large and meeting hold timing is a challenge due to large
uncommon clock path.

Where to use a lock-up latch: As mentioned above, a lock-up latch is used where
there is high probability of hold failure in scan-shift modes. So, possible scenarios
where lockup latches are to be inserted are:

Scan chains from different clock domains: In this case, since, the two
domains do not interact functionally, so both the clock skew and uncommon
clock path will be large.
 Flops within same domain, but at remote places: Flops within a scan
chain which are at remote places are likely to have more uncommon clock
path. 
Advantages of inserting lockup latches:

 Inserting lock-up latches helps in easier hold timing closure for scan-shift
mode
 Robust method of hold timing closure where uncommon path is high
between launch and capture flops
 Power efficient and area efficient
 It improves yield as it enables the device to handle more variations.

 For flops triggering on positive edge of the clock, you need to have latch
transparent when clock is low (negative level-sensitive lockup latch)
 For flops triggering on negative edge of the clock, you need to have latch
transparent when clock is high (positive level-sensitive lockup latch)

Clock latency in dft

Clock Latency is the general term for the delay that the clock signal takes between
any two points. It can be from source (PLL) to the sink pin (Clock Pin) of registers
or between any two intermediate points.
Clock latency = Source latency + Network latency
Setup slack
Setup Slack = required time - Arrival time

What are wrapper cells and chains tell its function

The wrapper chains can comprise of two distinct kinds of wrapper cells: shared and
dedicated. A shared wrapper cell is really a current functional flop in the structure
that additionally shares duty as a wrapper cell. No extra rationale is required. One
just needs to distinguish the right functional flop as the shared wrapper cell and
stitch it into the wrapper chains. A dedicated cell is another cell that is added to the
plan. In its most straightforward structure, it very well may be only a mux and a
flop. In any case, it can likewise be progressively mind boggling.

What is Simulation failure?

Vectors generated by ATPG applied to the simulation stage to check the validity of
the signals and nets for a sanity check of the scan inserted netlist.
If the input vectors provided for simulation don't match with expected or golden
output leads to simulation failure.
It is always necessary to clean the simulation without any mismatch to make sure
the perfection of scan insertion.
Simulation Failure debug and its solution:
To debug the mismatches that occurred during the pattern validation, we need a
specific tool to check the waveform signals value like ncsim, Verdi, etc.
To debug, first of all, take the absolute path of the failing register and analyze the
value of the mandatory signals like clock, reset, D, SI, SO, Q, etc.
If any X value observed in the signal, then back-trace the particular signal and do
this until the source for X generation is observed.
1. Clock value X
2. Reset value X
3. Clock Frequency not correct
Clock value X
 In the below-shown waveform, scan_clk, CLK, Scan_en, reset, test_mode
and scan_mode is getting X value after some amount of time extent.
 Initialization value seems to be 0 or 1, and after that, it's getting X
throughout for few signals and some it is having similar behavior for the
whole signal.
 First of all, for debugging any simulation mismatches, check all the signal
value for mandatory signals which illustrate the scan signals like scan clock,
scan enable, scan mode, scan reset, etc.

On further back tracing the scan_clk and RESET_L signals, below source
test_mode – X and scan_clk – 1 is observed.

It is observed that the value of the clock is ceaselessly 1 and test_mode is X.

Now the question arises in mind that How to resolve? Where to fix? How to fix?
So, here are the answer explained below for the above question.
We can force value while performing simulation to temporarily clean it.
Also, to fix the issue without any force given at the simulation stage, we can check
the values of the particular signals in SPF used at the ATPG stage.
Here comes the SPF editing part to define the scan_clk and test_mode values.
Earlier the values for scan_clk and test_mode is inaccurately defined in the SPF as
shown below:

In this, “All_in” values are defined based on the signals and its position.

As described in the SPF infrastructure section, the values of required scan signals
should be set properly in the procedures portion.
Round mark are drawn on the issue part, and below is the description of that.
Scenario 1:
In “multiclock_capture” procedure, “All_in” values are not correct as shown
below:
“All_in” = 11 \r8 N;
//
C {
"All_in" = '"scan_clk = 1" + "clk =1" + "ScanIn_1 = N" + "ScanIn_2 = N" +
"Input_1 = N" + "Input_2 = N" + "rstn_L = N" + "scan_enable = N" + "scan_mode
= N" + "test_mode = N"';
}

F {
“scan_clk” = P; //scan clock is pulsing, it will override the value in C section, so
clock will pulse in capture cycle.
}
Solution 1:
C {
“All_in” = 00 \r4 N 1011;
}

F {
“scan_clk” = P;
“test_mode” = 1 //It should be throughout 1 for all the process.
}
Scenario 2:
In “load_unload” procedure – Clock should be pulsing for shift procedures.
In below scenario clock is defined constant 1.
C {
“All_in” = 11 \r8 N;
}

Shift {
V {
"Clock" = 11;
}}
Solution 2:
C {
“All_in” = 00 \r4 N 1011;
}

Shift {
V {
"Clock" = PP; // clock should be pulsing while shifting
}}
Scenario 3:
If the scan clock frequency is different than the required frequency, then change
the clock period in _WFT table, as shown below:
“scan_clk" { P { '0ns' D; '35ns' U; '65ns' D; } }
"clk" { P { '0ns' D; '25ns' U; '75ns' D; } }
Change the period in ns for the up and down section of the respected scan clock
according to the required frequency.
SPF is also used to feed instructions and data bits to the UTDR (user defined test
data register bits) and for initialization/test setup purpose as well.