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Common commands in ICC2 (2) place stage

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ICC2
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One, the process of place_opt

place_opt is a packaged command that contains:  

1. Corase placement This step is to place the standard cell of the timing driven according
to the timing requirements. At this time, the placement of the standard units is still illegal,
that is, the standard units are not on the row, and they may all overlap.  

Command: initial_place  

SPG flow uses DCG netlist and def, and can skip initial_place and initial_drc.

set_app_options -name

place_opt.flow.do_spg -value true

Two pass placement can optimize the timing driven and congestion driven in this step,
and preprocess the high fanout net.

set_app_options -name place_opt.initial_drc.global_route_based -value true

set_app_options -name place_opt.initial_place.two_pass -value true

2. HFN solves fanout This step will first remove buffer trees, that is, buffers and inverters
that the tool considers redundant. Then start to solve fanout net and logic drc . It is worth
noting that this stage does not solve the ideal network network.  

Command: initial_drc  

3. Preliminary timing optimization This step is the timing optimization before the most
refine placement.  

Command: initial_opto   

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4. Final placement This step is the most timing & congestion driven placement. After this
step, the positions of all standard units are legal, and there will be no cases where the
standard units are not on the row or have overlaps .  

Command: final_place  

5. The final timing optimization This step is based on the results of final placement for
further timing optimization, this process will also involve the rearrangement of cells.  

Command: final_opto

Second, the relevant settings of the place stage

1. early clock

Doing place_opt of CTS will effectively improve the timing

set_app_options -name place_opt.flow.clock.aware_placement -value true

set_app_options -name place_opt.flow.trial_clock_tree -value true

set_app_options -name place_opt.flow.optimize_icgs -value true

#Using optimize icg does not need to set the above two app options.

create_routing_rule icc2rm_2w2s \

-default_reference_rule -multiplier_width 2 -multiplier_spacing 2

set_routing_rule -rule icc2rm_2w2s [get_nets -physical_context -of [get_clock_tree_pins]]

# For early clock, it is better to specify cts buffer or inverter, and ndr rule, which is more
consistent with the cts stage.

2. global route

set_app_options -name place_opt.initial_drc.global_route_based -value 1

set_app_options -name place_opt.initial_place.two_pass -value true

# global route combined with two pass placement can reduce congestion and improve
timing

3. Other options can improve timing

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set_app_options -name place_opt.flow.optimize_ndr -value true

set_app_options -name place_opt.flow.do_path_opt -value true

set_app_options -name place_opt.flow.enable_ccd -value false

# It is recommended to be consistent with the clock_opt ccd switch state

set_app_options -name place.coarse.icg_auto_bound -value true

# Set bounds for icg and the registers it drives, and putting them together can improve the
violation of reg2clkGate.

set_app_options -name opt.buffering.enable_rebuffering -value true

3. create bound

Limit the area of ​the specified cell place

create_bound -name boundname -boundary {{lx ly} {ux uy}}

add_to_bound boundname [get_flat_cells**]

set_size_only [get_flat_cells **]

Even if there is a bound, cells will still be copied and placed outside the bound during
optimization. Using size only allows the constrained cells to only be placed in the bound.

4. missing def

Do not add scan def when doing some small modules without dft or create placement try
floorplan in the floorplan stage

set_app_options -name \

place.coarose.continue_on_missing_scandef -value true

5.spacing rule

remove_placement_spacing_rules -all

set_placement_spacing_label -name X -side both -lib_cells [get_lib_cells */*]

set_placement_spacing_rule -label {XX} {1 1}

set_placement_spacing_rule -label {X SNPS_BOUNDARY} {1 1}

If you add filler to generate 1x spacing, you can use create_stdcell:fillers -lib_cells
*/filler_list -rules no_1x

6. Magnet placement

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Preplace the pin/port related logic of the fixed instance.

magnet_placement\

-move_fixed //Soft constraints, optimization can still be moved \

-mark_fixed //hard constraint, fixed after magnet \

-stop_on_sequential_cells [get_cells xxx] //magnet trace to stop sequential devices,


including sequential devices, there is also a stop_by** \

-logic_level 1 //Select the level of magnet.

7.keep module port

Prevent some module ports from being optimized during the optimization process.

set_freeze_port -all [get_cells -filter "is_hierarchical == true"]

8. Consider the place of preroute

set_app_options -name place.legalize.enable_advanced_legalizer -value true

set_app_options -name place.legalize.enable_advanced_prerouted_net_check -value true

set_app_options -name place.legalize.enable_prerouted_net_check -value true //Considering


the pin shape or blockage inside the std cell, place can make the std cell avoid places that
will generate drc, such as near pg via

set_app_options -name plan.pgroute.honor_std_cell_drc -value true

9. legalize

legalize_placement \

-cell [get_cells xx] \

-moveable_distance 10 //The cells within the specified cell10um range can be moved 

set_app_options -name \

place.legalize.report_displacement_limit -value 1000 //report upper limit of 1000

set_app_options -name \

place.legalize.stream_place -value true //More instance small displacements instead of large


displacements

set_app_options -name \

place.legalize.optimize_orientations -value true //Change direction to reduce displacement

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