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Assignment 4 Unit 4
Assignment 4 Unit 4
UNIT-4
SHORT
1. Differentiate Between Sequential and Parallel Blocks
2. Define Logic Synthesis and Synthesis Design Flow
3. Write Verilog code for Parity Generator in Behavioural modelling
4. Discuss Generate blocks with an example
5. Explain Blocking and Non-Blocking statements with example
6. Give the example for replication and concatenation
7. Differentiate between Mealy FSM and Moore FSM
8. Differentiate between Task and Function
LONG
1. With Examples for each, explain all the types of Conditional Statements
2. Write short note on Data flow modelling and explain with a suitable example
3. Explain all the Types of Timing Controls with examples for each
4. Explain Blocking and Non-blocking assignments with examples.
5. Write Neat Diagram Explain Race Condition
6. Mealy Machine Design
7. Differentiate latch and Flip flop and draw its timing diagram.
8. Design a mod-8 Counter using D-FF's and Write Verilog Code for the same
9. Design a Mod-8 Counter using Sequential Circuit approach with JK-FF's and write it's Verilog
Codes
10. Write Verilog code for a 16:1 multiplexer using keyword task and verify its functionality using
stimulus.
VERILOG CODES
1. Write Switch Level Modelling Source Code and Test Bench for 2-input AND GATE
2. Write Switch Level Modelling Source Code and Test Bench for 2-input OR GATE
3. Write Switch Level Modelling Source Code and Test Bench for 2-input NOT GATE
4. Write Switch Level Modelling Source Code and Test Bench for 2-input NAND GATE
5. Write Switch Level Modelling Source Code and Test Bench for 2-input NOR GATE
6. Write Switch Level Modelling Source Code and Test Bench for 2-input XOR GATE
7. Write Switch Level Modelling Source Code and Test Bench for 2-input XNOR GATE
8. Write Switch Level Modelling Source Code and Test Bench for 3-input AND GATE
9. Write Switch Level Modelling Source Code and Test Bench for 3-input OR GATE
10. Write Switch Level Modelling Source Code and Test Bench for 3-input NAND GATE
11. Write Switch Level Modelling Source Code and Test Bench for 3-input NOR GATE
12. Write Switch Level Modelling Source Code and Test Bench for 3-input XOR GATE
13. Write Switch Level Modelling Source Code and Test Bench for 3-input XNOR GATE
14. Write Switch Level Modelling Source Code and Test Bench for HALF ADDER
15. Write Switch Level Modelling Source Code and Test Bench for FULL ADDER
16. Write Switch Level Modelling Source Code and Test Bench for 2:1 MUX
17. Write Switch Level Modelling Source Code and Test Bench for 4:1 MUX
18. Write Verilog Code for SR-FF
19. Write Verilog Code for D-FF
20. Write Verilog Code for JK-FF
21. Write Verilog Code for T-FF
22. Write Verilog code for 4-bit SISO Shift Register
23. Write Verilog code for 4-bit SIPO Shift Register