UNIT-4

UNIT-4
SHORT
1. Differentiate Between Sequential and Parallel Blocks
2. Define Logic Synthesis and Synthesis Design Flow
3. Write Verilog code for Parity Generator in Behavioural modelling
4. Discuss Generate blocks with an example
5. Explain Blocking and Non-Blocking statements with example
6. Give the example for replication and concatenation
7. Differentiate between Mealy FSM and Moore FSM
8. Differentiate between Task and Function

LONG
1. With Examples for each, explain all the types of Conditional Statements
2. Write short note on Data flow modelling and explain with a suitable example
3. Explain all the Types of Timing Controls with examples for each
4. Explain Blocking and Non-blocking assignments with examples.
5. Write Neat Diagram Explain Race Condition
6. Mealy Machine Design
7. Differentiate latch and Flip flop and draw its timing diagram.
8. Design a mod-8 Counter using D-FF's and Write Verilog Code for the same
9. Design a Mod-8 Counter using Sequential Circuit approach with JK-FF's and write it's Verilog
Codes
10. Write Verilog code for a 16:1 multiplexer using keyword task and verify its functionality using
stimulus.

VERILOG CODES
1. Write Switch Level Modelling Source Code and Test Bench for 2-input AND GATE
2. Write Switch Level Modelling Source Code and Test Bench for 2-input OR GATE
3. Write Switch Level Modelling Source Code and Test Bench for 2-input NOT GATE
4. Write Switch Level Modelling Source Code and Test Bench for 2-input NAND GATE
5. Write Switch Level Modelling Source Code and Test Bench for 2-input NOR GATE
6. Write Switch Level Modelling Source Code and Test Bench for 2-input XOR GATE
7. Write Switch Level Modelling Source Code and Test Bench for 2-input XNOR GATE
8. Write Switch Level Modelling Source Code and Test Bench for 3-input AND GATE
9. Write Switch Level Modelling Source Code and Test Bench for 3-input OR GATE
10. Write Switch Level Modelling Source Code and Test Bench for 3-input NAND GATE
11. Write Switch Level Modelling Source Code and Test Bench for 3-input NOR GATE
12. Write Switch Level Modelling Source Code and Test Bench for 3-input XOR GATE
13. Write Switch Level Modelling Source Code and Test Bench for 3-input XNOR GATE
14. Write Switch Level Modelling Source Code and Test Bench for HALF ADDER
15. Write Switch Level Modelling Source Code and Test Bench for FULL ADDER
16. Write Switch Level Modelling Source Code and Test Bench for 2:1 MUX
17. Write Switch Level Modelling Source Code and Test Bench for 4:1 MUX
18. Write Verilog Code for SR-FF
19. Write Verilog Code for D-FF
20. Write Verilog Code for JK-FF
21. Write Verilog Code for T-FF
22. Write Verilog code for 4-bit SISO Shift Register
23. Write Verilog code for 4-bit SIPO Shift Register

6 t h SEM ECE-VLSI Design-OU Unit-4 T Maharshi Sanand Yadav

 UNIT-4
24. Write Verilog code for 4-bit PIPO Shift Register
25. Write Verilog code for 4-bit PISO Shift Register
26. Write Verilog code for 8-bit SISO Shift Register
27. Write Verilog code for 8-bit SIPO Shift Register
28. Write Verilog code for 8-bit PIPO Shift Register
29. Write Verilog code for 8-bit PISO Shift Register
30. Write Verilog code for Mealy 00 FSM
31. Write Verilog code for Mealy 01 FSM
32. Write Verilog code for Mealy 10 FSM
33. Write Verilog code for Mealy 11 FSM
34. Write Verilog code for Mealy 000 FSM
35. Write Verilog code for Mealy 001 FSM
36. Write Verilog code for Mealy 010 FSM
37. Write Verilog code for Mealy 011 FSM
38. Write Verilog code for Mealy 100 FSM
39. Write Verilog code for Mealy 101 FSM
40. Write Verilog code for Mealy 110 FSM
41. Write Verilog code for Mealy 111 FSM
42. Write Verilog code for Mealy 0000 FSM
43. Write Verilog code for Mealy 0001 FSM
44. Write Verilog code for Mealy 0010 FSM
45. Write Verilog code for Mealy 0011 FSM
46. Write Verilog code for Mealy 0100 FSM
47. Write Verilog code for Mealy 0101 FSM
48. Write Verilog code for Mealy 0110 FSM
49. Write Verilog code for Mealy 0111 FSM
50. Write Verilog code for Mealy 1000 FSM
51. Write Verilog code for Mealy 1001 FSM
52. Write Verilog code for Mealy 1010 FSM
53. Write Verilog code for Mealy 1011 FSM
54. Write Verilog code for Mealy 1100 FSM
55. Write Verilog code for Mealy 1101 FSM
56. Write Verilog code for Mealy 1110 FSM
57. Write Verilog code for Mealy 1111 FSM
58. Write Verilog code for Moore 00 FSM
59. Write Verilog code for Moore 01 FSM
60. Write Verilog code for Moore 10 FSM
61. Write Verilog code for Moore 11 FSM
62. Write Verilog code for Moore 000 FSM
63. Write Verilog code for Moore 001 FSM
64. Write Verilog code for Moore 010 FSM
65. Write Verilog code for Moore 011 FSM
66. Write Verilog code for Moore 100 FSM
67. Write Verilog code for Moore 101 FSM
68. Write Verilog code for Moore 110 FSM
69. Write Verilog code for Moore 111 FSM
70. Write Verilog code for Moore 0000 FSM
71. Write Verilog code for Moore 0001 FSM
72. Write Verilog code for Moore 0010 FSM
73. Write Verilog code for Moore 0011 FSM
74. Write Verilog code for Moore 0100 FSM

6 t h SEM ECE-VLSI Design-OU Unit-4 T Maharshi Sanand Yadav

 UNIT-4
75. Write Verilog code for Moore 0101 FSM
76. Write Verilog code for Moore 0110 FSM
77. Write Verilog code for Moore 0111 FSM
78. Write Verilog code for Moore 1000 FSM
79. Write Verilog code for Moore 1001 FSM
80. Write Verilog code for Moore 1010 FSM
81. Write Verilog code for Moore 1011 FSM
82. Write Verilog code for Moore 1100 FSM
83. Write Verilog code for Moore 1101 FSM
84. Write Verilog code for Moore 1110 FSM
85. Write Verilog code for Moore 1111 FSM
86. Design 2-bit synchronous Up counter using SR-FF
87. Design 2-bit synchronous Up counter using D-FF
88. Design 2-bit synchronous Up counter using JK-FF
89. Design 2-bit synchronous Up counter using T-FF
90. Design 2-bit synchronous Down counter using SR-FF
91. Design 2-bit synchronous Down counter using D-FF
92. Design 2-bit synchronous Down counter using JK-FF
93. Design 2-bit synchronous Down counter using T-FF
94. Design 2-bit synchronous Up-Down counter using SR-FF
95. Design 2-bit synchronous Up-Down counter using D-FF
96. Design 2-bit synchronous Up-Down counter using JK-FF
97. Design 2-bit synchronous Up-Down counter using T-FF
98. Design 3-bit synchronous Up counter using SR-FF
99. Design 3-bit synchronous Up counter using D-FF
100. Design 3-bit synchronous Up counter using JK-FF
101. Design 3-bit synchronous Up counter using T-FF
102. Design 3-bit synchronous Down counter using SR-FF
103. Design 3-bit synchronous Down counter using D-FF
104. Design 3-bit synchronous Down counter using JK-FF
105. Design 3-bit synchronous Down counter using T-FF
106. Design 3-bit synchronous Up-Down counter using SR-FF
107. Design 3-bit synchronous Up-Down counter using D-FF
108. Design 3-bit synchronous Up-Down counter using JK-FF
109. Design 3-bit synchronous Up-Down counter using T-FF
110. Design 4-bit synchronous Up counter using SR-FF
111. Design 4-bit synchronous Up counter using D-FF
112. Design 4-bit synchronous Up counter using JK-FF
113. Design 4-bit synchronous Up counter using T-FF
114. Design 4-bit synchronous Down counter using SR-FF
115. Design 4-bit synchronous Down counter using D-FF
116. Design 4-bit synchronous Down counter using JK-FF
117. Design 4-bit synchronous Down counter using T-FF
118. Design 4-bit synchronous Up-Down counter using SR-FF
119. Design 4-bit synchronous Up-Down counter using D-FF
120. Design 4-bit synchronous Up-Down counter using JK-FF
121. Design 4-bit synchronous Up-Down counter using T-FF
122. Design 2-bit asynchronous Up counter using SR-FF
123. Design 2-bit asynchronous Up counter using D-FF
124. Design 2-bit asynchronous Up counter using JK-FF
125. Design 2-bit asynchronous Up counter using T-FF

6 t h SEM ECE-VLSI Design-OU Unit-4 T Maharshi Sanand Yadav

 UNIT-4
126. Design 2-bit asynchronous Down counter using SR-FF
127. Design 2-bit asynchronous Down counter using D-FF
128. Design 2-bit asynchronous Down counter using JK-FF
129. Design 2-bit asynchronous Down counter using T-FF
130. Design 2-bit asynchronous Up-Down counter using SR-FF
131. Design 2-bit asynchronous Up-Down counter using D-FF
132. Design 2-bit asynchronous Up-Down counter using JK-FF
133. Design 2-bit asynchronous Up-Down counter using T-FF
134. Design 3-bit asynchronous Up counter using SR-FF
135. Design 3-bit asynchronous Up counter using D-FF
136. Design 3-bit asynchronous Up counter using JK-FF
137. Design 3-bit asynchronous Up counter using T-FF
138. Design 3-bit asynchronous Down counter using SR-FF
139. Design 3-bit asynchronous Down counter using D-FF
140. Design 3-bit asynchronous Down counter using JK-FF
141. Design 3-bit asynchronous Down counter using T-FF
142. Design 3-bit asynchronous Up-Down counter using SR-FF
143. Design 3-bit asynchronous Up-Down counter using D-FF
144. Design 3-bit asynchronous Up-Down counter using JK-FF
145. Design 3-bit asynchronous Up-Down counter using T-FF
146. Design 4-bit asynchronous Up counter using SR-FF
147. Design 4-bit asynchronous Up counter using D-FF
148. Design 4-bit asynchronous Up counter using JK-FF
149. Design 4-bit asynchronous Up counter using T-FF
150. Design 4-bit asynchronous Down counter using SR-FF
151. Design 4-bit asynchronous Down counter using D-FF
152. Design 4-bit asynchronous Down counter using JK-FF
153. Design 4-bit asynchronous Down counter using T-FF
154. Design 4-bit asynchronous Up-Down counter using SR-FF
155. Design 4-bit asynchronous Up-Down counter using D-FF
156. Design 4-bit asynchronous Up-Down counter using JK-FF
157. Design 4-bit asynchronous Up-Down counter using T-FF
158. Write Verilog code for priority encoder using behavioural modelling and write test
bench to verify its functionality
159. Write Verilog Code for D-Latch using Transmission Gates

6 t h SEM ECE-VLSI Design-OU Unit-4 T Maharshi Sanand Yadav