Hardware-Aware In Situ Learning Based on Stochastic Magnetic Tunnel Junctions

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Hardware-Aware In Situ Learning Based on Stochastic Magnetic Tunnel Junctions

Jan Kaiser, William A. Borders, Kerem Y. Camsari, Shunsuke Fukami, Hideo Ohno, and Supriyo Datta

Phys. Rev. Applied 17, 014016 – Published 13 January 2022

Abstract

One of the big challenges of current electronics is the design and implementation of hardware neural networks that perform fast and energy-efficient machine learning. Spintronics is a promising catalyst for this field with the capabilities of nanosecond operation and compatibility with existing microelectronics. Considering large-scale, viable neuromorphic systems however, variability of device properties is a serious concern. In this paper, we show an autonomously operating circuit that performs hardware-aware machine learning utilizing probabilistic neurons built with stochastic magnetic tunnel junctions. We show that in situ learning of weights and biases in a Boltzmann machine can counter device-to-device variations and learn the probability distribution of meaningful operations such as a full adder. This scalable autonomously operating learning circuit using spintronics-based neurons could be especially of interest for standalone artificial-intelligence devices capable of fast and efficient learning at the edge.

Received 19 July 2021
Revised 1 November 2021
Accepted 13 December 2021

DOI:https://doi.org/10.1103/PhysRevApplied.17.014016

Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.

Physics Subject Headings (PhySH)

Spintronics Stochastic inference Synapses

Artificial neural networks Magnetic tunnel junctions Stochastic dynamical systems

Machine learning

Condensed Matter, Materials & Applied Physics

Authors & Affiliations

Jan Kaiser ¹, William A. Borders ², Kerem Y. Camsari ^3,*, Shunsuke Fukami ^{2,4,5,6,7,†}, Hideo Ohno ^2,4,5,6,7, and Supriyo Datta ¹

¹Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47906, USA
²Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan
³Department of Electrical and Computer Engineering, University of California Santa Barbara, Santa Barbara, California 93106, USA
⁴Center for Innovative Integrated Electronic Systems, Tohoku University, Sendai, Japan
⁵Center for Spintronics Research Network, Tohoku University, Sendai, Japan
⁶Center for Science and Innovation in Spintronics, Tohoku University, Sendai, Japan
⁷WPI-Advanced Institute for Materials Research, Tohoku University, Sendai, Japan

^*[email protected]
^†[email protected]

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Vol. 17, Iss. 1 — January 2022

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Images

Figure 1
Probabilistic learning circuit. (a) Block diagram of the learning circuit with p-bit output voltages ${V_{out}}$ , p-bit input voltages ${V_{in}}$ , weight voltages ${V_{i, j}}$ , capacitor voltages ${V_{C}}$ , p-bit correlation voltages ${V_{m}}$ , and data distribution correlation voltages ${V_{v}}$ . (b) A photograph of the PCB with the five p-bits (each consisting of a SMTJ, a NMOS transistor, and a source resistor $R_{S}$ ) and 15 $R C$ elements and 20 operational amplifiers (five used as a comparator and 15 as a buffer). The p-bits are interconnected with the $R C$ array as shown in (a).
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Figure 2
Full-adder learning. (a) Average response of emulated ideal MTJ p-bits for the five p-bits used in the FA with average normalized output voltage $⟨ norm . V_{out, i} ⟩ = 2 \times ⟨ V_{out, i} ⟩ / V_{DD} - 1 = ⟨ m_{i} ⟩$ . Every point is averaged over 15 s. (b) Experimental distribution of emulated ideal MTJ circuit $P_{\exp} (m)$ with p-bit output states $([m_{1}, m_{2}, m_{3}, m_{4}, m_{5}] + 1) / 2 = [A, B, C_{in}, S, C_{out}]$ where $m_{i} = 2 \times V_{out, i} / V_{DD} - 1$ collected as a histogram over for the first 60 s of learning. (c) Experimental distribution of emulated ideal MTJ circuit collected as a histogram over the last 60 s of learning. (d) KL divergence between ideal and experimental distribution $KL [P_{ideal} | | P_{\exp} (t)]$ versus time of ideal and nonideal MTJ system. The experimental distribution is obtained over 60 s of learning. (e) Average response of nonideal MTJ p-bits for the 5 p-bits used in the FA with average normalized output voltage $⟨ norm . V_{out, i} ⟩ = 2 \times ⟨ V_{out, i} ⟩ / V_{DD} - 1 = ⟨ m_{i} ⟩$ . Every point is averaged over 15 s. (f) Experimental distribution of nonideal MTJ circuit $P_{\exp} (m)$ collected as a histogram over the first 60 s of learning. (g) Experimental distribution of nonideal MTJ circuit $P_{\exp} (m)$ collected as a histogram over the last 60 s of learning.
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Figure 3
Weight voltages during FA learning. The ten weight voltages are shown during the 3000 s of learning. Blue lines are the weights learned with the ideal MTJ circuit; red lines show the weights for the nonideal MTJ circuit. The solid lines in the middle are the moving average of the actual weights taken over a window of 10 s.
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Figure 4
Boltzmann distribution obtained from learned weights. (a) Boltzmann distribution $P (m) = 1 / Z \exp (- β E)$ with energy $E = - \sum W_{i, j} m_{i} m_{j}$ computed by using the learned weights $W_{i, j}$ of the FA with the emulated ideal SMTJ p-bit circuit where the bipolar p-bit states $([m_{1}, m_{2}, m_{3}, m_{4}, m_{5}] + 1) / 2 = [A, B, C_{in}, S, C_{out}]$ . (b) Boltzmann distribution $P (m)$ computed by using the learned weights of the FA with the nonideal SMTJ p-bit circuit. Biases are set to 0.
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Figure 5
Multiplexer emulation. The SMTJ-based p-bit on the left is modeled by a multiplexer that switches randomly between $R_{P}$ and $R_{AP}$ but as a function of $V_{in}$ so that the right statistics are preserved [43].
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