User contributions for 50504F
A user with 548 edits. Account created on 16 February 2017.
30 May 2017
- 07:4407:44, 30 May 2017 diff hist +1,048 Talk:Instruction set architecture →The lead section as of 29 May 2017: Comment
- 06:5806:58, 30 May 2017 diff hist −4,136 m Talk:Instruction set architecture Removed unhelpful and uncivil remarks by the indefinitely blocked User:Janagewen
- 06:4706:47, 30 May 2017 diff hist −72 MIPS architecture MIPS-X was a follow onto Stanford MIPS, so it's unrelated to this article's topic
- 06:4406:44, 30 May 2017 diff hist +21 MIPS architecture →top: Distinguished
- 06:3606:36, 30 May 2017 diff hist +3,993 MIPS architecture →MIPS III: Added CPU and FPU instruction tables, made minor corrections and elaborated on the supervisor privilege level
29 May 2017
- 07:3307:33, 29 May 2017 diff hist +463 User talk:Risc64 →Media Extension Unit has been merged: new section
- 07:2607:26, 29 May 2017 diff hist +234 Talk:Ingenic Semiconductor →Merged Media Extension Unit to here: new section
- 07:2307:23, 29 May 2017 diff hist +125 N Talk:Media Extension Unit ←Created page with '{{Copied|from=Media Extension Unit|from_oldid=778855849|to=Ingenic Semiconductor|to_oldid=782796270|date=07:07, 29 May 2017}}' current
- 07:2307:23, 29 May 2017 diff hist +127 Talk:Ingenic Semiconductor No edit summary
- 07:0707:07, 29 May 2017 diff hist −1,352 Media Extension Unit Merged content to Ingenic Semiconductor#XBurst microarchitecture.
- 07:0707:07, 29 May 2017 diff hist +1,002 Ingenic Semiconductor Merged content from Media Extension Unit to here.
- 06:4006:40, 29 May 2017 diff hist +2,236 Talk:Instruction set architecture →The lead section as of 29 May 2017: new section
- 06:2606:26, 29 May 2017 diff hist −1 m Instruction set architecture →top
- 06:0906:09, 29 May 2017 diff hist +752 User talk:Yamla →Re. Janagewen: new section
28 May 2017
- 10:3310:33, 28 May 2017 diff hist +244 Template talk:Infobox CPU architecture →Template title: new section
- 10:2910:29, 28 May 2017 diff hist +839 Template talk:Multimedia extensions →Scope: new section
- 10:1710:17, 28 May 2017 diff hist +14 Template:Processor technologies CISC et al. are types of ISAs, not instruction sets; clarified types of ISAs from example ISAs
- 10:0810:08, 28 May 2017 diff hist +32 N Power ISA ←Redirected page to Power Architecture
- 10:0610:06, 28 May 2017 diff hist −48 Template:Multimedia extensions There is no need to quality group1 because group2 can be treated as a subgroup; shorten links; fix Power ISA's name
- 09:3709:37, 28 May 2017 diff hist −89 Instruction set architecture →top: Attempted to improve flow; moved the text about the implications ISAs have before the text explaining what an ISA is to improve accessibility
- 08:2308:23, 28 May 2017 diff hist +267 Wikipedia:Redirects for discussion/Log/2017 May 14 →RISC-based computer design approach: Comment
- 07:5907:59, 28 May 2017 diff hist −12 m Instruction set architecture →top: Copyedited
27 May 2017
- 10:2810:28, 27 May 2017 diff hist +1 m User talk:50504F →Somebody doesn't like your introductory paragraph in Instruction set
- 10:2810:28, 27 May 2017 diff hist +1,427 User talk:50504F →Somebody doesn't like your introductory paragraph in Instruction set: Replies
26 May 2017
- 07:5407:54, 26 May 2017 diff hist −11 Template:RISC architectures Correct RISC; "RISC-based processor architectures" is redundant and superfluous
- 07:5007:50, 26 May 2017 diff hist −95 Reduced instruction set computer →top: Simpler instructions are more versatile, complex instructions are less so (the classic RISC provides primitives, CISC provides solutions dichotomy); other improvements
- 07:3507:35, 26 May 2017 diff hist −290 Reduced instruction set computer →top: See Talk:Reduced instruction set computer#Problems with the lead
- 07:3507:35, 26 May 2017 diff hist +1,996 Talk:Reduced instruction set computer →Problems with the lead: new section
22 May 2017
- 08:1508:15, 22 May 2017 diff hist +12 Template:RISC architectures No edit summary
- 08:1308:13, 22 May 2017 diff hist +40 MIPS-X No edit summary
- 08:1108:11, 22 May 2017 diff hist +9 MIPS-X Wrong MIPS
- 08:0408:04, 22 May 2017 diff hist +1 m Stanford MIPS No edit summary
- 08:0208:02, 22 May 2017 diff hist +46 Stanford MIPS No edit summary
- 07:5707:57, 22 May 2017 diff hist +228 MIPS →Technology: Added Stanford MIPS and MIPS-X
- 07:4507:45, 22 May 2017 diff hist +25 Template:RISC architectures Added Stanford MIPS and Alpha was just called Alpha, not DEC Alpha
- 07:3207:32, 22 May 2017 diff hist −18 History of Digital Equipment Corporation →Faltering in the market: Wrong MIPS
- 07:3107:31, 22 May 2017 diff hist −4 Berkeley RISC →top: Wrong MIPS
- 07:2407:24, 22 May 2017 diff hist +4 Stanford University →Discoveries and innovation: Name the Stanford design
- 07:0807:08, 22 May 2017 diff hist −5 Classic RISC pipeline →Solution B. Pipeline interlock: Name the Stanford design
- 07:0607:06, 22 May 2017 diff hist −22 Intel i960 →Architecture: Name the Stanford design
- 07:0207:02, 22 May 2017 diff hist −4 m History of general-purpose CPUs →Asynchronous CPUs
- 06:4906:49, 22 May 2017 diff hist +4 m AMD Am29000 →Design
- 06:4806:48, 22 May 2017 diff hist +1 Register window →Criticism: Wrong MIPS
- 06:3906:39, 22 May 2017 diff hist +54 m Microprocessor chronology →1980s
- 06:2706:27, 22 May 2017 diff hist +57 Reduced instruction set computer Name the Stanford project; Stanford's MIPS is a separate architecture
- 06:2106:21, 22 May 2017 diff hist −3,281 MIPS architecture processors →History: Stanford MIPS has its own article, and it's a separate design
- 06:0306:03, 22 May 2017 diff hist +192 MIPS Technologies Name the RISC project
- 05:5405:54, 22 May 2017 diff hist +98 John L. Hennessy Name the RISC project
- 05:4805:48, 22 May 2017 diff hist −19 DLX The commercial MIPS architecture and Stanford MIPS are different designs
19 May 2017
- 07:4407:44, 19 May 2017 diff hist −4 Microprocessor without Interlocked Pipeline Stages ←Redirected page to Stanford MIPS current
