Tessent Silicon Lifecycle Solutions

Discover the latest advances in Tessent DFT solutions for the #semiconductor industry by joining our experts on the Siemens EDA booth at ITC India 2024, 21 - 23 July. Our team will be showcasing the Tessent Streaming Scan Network (SSN) and Tessent Multi-die software solutions, amongst others, and there will also be the opportunity to enjoy the special Keynote address by Lee Harrison, Director of Product Marketing, Siemens. Explore the full range of DFT solutions from Tessent today. https://sie.ag/prGG6 To learn more and to register for ITC India, visit. https://sie.ag/4JLepF #ITCIndia2024 #DFTmarketleader #Tessent #DFT #3DIC #TessentStreamingScanNetwork #TessentMultiDie #SiemensEDA

Yield learning and silicon debug have evolved in the era of high complexity SoCs and multi-die systems. Marc Hutner, Director, Product Management, Tessent, explains how in this podcast with https://sie.ag/3a8y9V. Marc discusses improving Yield Insights through AI, ML and other techniques that can result in millions of dollars of savings. Listen now to the full podcast to learn more. https://sie.ag/7VhBUc #YieldLearning #yieldmanagement #TessentYieldInsight #DFTmarketleader #Tessent #semiconductor #SiemensEDA

Check out this STMicroelectronics presentation, in which Fabien Chiantia, Test Engineer and Jean-Marcs Denollet, DFT Engineer, provide their expert insight into OST (Observable Scan Technology) and Test Point benchmarking inside an imaging chip. Observable Scan Technology (OST) is a feature that enables faster achievement of the targeted coverage with a different impact on the area. Fabien and Jean-Marcs presentation demonstrates the coverage differences between Test Points and OST, as well as the impact on the area for three different chips that they have in their division. Watch the full presentation that was delivered at the Siemens EDA User to User European summit earlier this year. https://sie.ag/6ZJmdE #3DIC #DFTmarketleader #Tessent #designfortest #OST #ObservableScanTechnology #Semiconductors #ATPG

If you're attending IPFA 2024 in Singapore, be sure not to miss this expert product presentation by Jayant D'Souza, Principal Technical Product Manager at Tessent, Siemens EDA. Whilst Scan chain diagnosis has long been used to identify manufacturing defects and yield issues in early ramp, identifying and eliminating these yield issues quickly and efficiently is required to ensure a successful product. The advent of new technologies, like backside power, in advanced process nodes have made fault isolation extremely challenging. In this paper, Jayant presents results from three new software-based technologies that provide accurate localization to enable efficient failure analysis of both front-end of line and back-end of line defects. Learn more about Jayants presentation content and the IPFA agenda: https://sie.ag/4QTKtY #TessentHiResChain #YieldLearning #yieldmanagement #TessentYieldInsight #DFTmarketleader #Tessent #semiconductor #SiemensEDA

As organizations seek to achieve and maintain a competitive edge in the field of AI chip technology, a key criteria remains getting new AI chips to market quickly and efficiently, and that relies on using design and test solutions that address the challenges of new AI chip architectures. This Siemens White paper explores the design of AI hardware and specifically looks at how to best test AI chips, to help reduce time to market. Author Lee Harrison, also provides a technical insight into how existing Tessent technologies help to speed time-to-market for AI chips. Download the White paper to learn more: https://sie.ag/uYriQ #AIchips #DFTmarketleader #Tessent #designfortest #3DIC #TessentStreamingScanNetwork #TessentSSN #Semiconductor #EDA

Gain an expert introduction to the Tessent Streaming Scan Network and its practical DFT approach for hierarchical and flat designs, in this latest on-demand webinar from Siemens EDA. Presented by Christian Dodd, Senior DFT Architect, the webinar is ideal for anyone inserting DFT on a design, regardless of running flat ATPG or scan pattern retargeting for a hierarchical design. With modern integrated circuit designs presenting huge challenges in their size, complexity and limited access, making them difficult to test using traditional scan access methods. Christian explains the advantages of using Tessent Streaming Scan Network (SSN) in this scenario. Tessent SSN provides a packetized scan delivery mechanism that efficiently delivers scan patterns for heterogenous and identical cores independent of top-level I/O resources. Watch now to learn more: https://sie.ag/6o5g3G #TessentStreamingScanNetwork #TessentSSN #chiplets #DFT #Tessent #DFTMarketLeader #SiemensEDA #3DIC #EDA #semiconductors

Introducing Tessent Hi-Res Chain software, a new tool from Siemens EDA, designed to address the critical challenges faced by integrated circuit (IC) design and manufacturing teams in advanced technology nodes, where even minor process variations can significantly impact yield and time-to-market. As IC designs progress to more advanced nodes at 5nm and below, they become increasingly susceptible to manufacturing variations that can create defects and slow yield ramp. At these geometries, traditional failure analysis (FA) methods can require weeks or months of laboratory effort to investigate. Siemens’ new Tessent Hi-Res Chain tool addresses this problem by rapidly providing transistor-level isolation for scan chain defects. For advanced process nodes where yield ramp heavily relies on chain diagnosis, the new software can boost diagnosis resolution by more than 1.5x, reducing the need for costly extensive failure analysis cycles. Read more about the new Tessent Hi-Res Chain software. https://sie.ag/tT8NP #TessentHiResChain #YieldLearning #yieldmanagement #TessentYieldInsight #DFTmarketleader #Tessent #semiconductor #SiemensEDA

Discover why silicon learning matters and how the Tessent Yield Learning team, led by Marc Hutner, Director Product Management, is developing dedicated solutions that reduce complexity without compromising quality or profitability. These new products are designed to help customers adapt to changing environments while also decreasing time-to-market and reducing cost. Learn more and discover why silicon learning matters in this short video below. To learn more about Tessent silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs, visit. https://sie.ag/2AqVoJ #YieldLearning #yieldmanagement #TessentYieldInsight #DFTmarketleader #Tessent #semiconductor #SiemensEDA

Learn about Layout Aware Diagnosis Flow using Tessent ATPG in this presentation by Intel Corporation and Siemens EDA, delivered at the U2U Europe summit. Balajiraja Ravinarayanan, DFT Engineering Manager, Siemens and Kevin McGonigle, Tech Lead Production Team, Intel, demonstrate a test methodology for Tessent diagnosis with and without the layout aware feature and compares the impact of both flows to final diagnosis outcome. Their presentation also includes the methodology describing the flows used, the methodology to validate the flows pre-silicon and finally the outcomes for both methodologies. To learn more about the content and to watch the full presentation, visit. https://sie.ag/4FQer1 #3DIC #DFTmarketleader #Tessent #designfortest #TessentStreamingScanNetwork #TessentSSN #Semiconductors #ATPG

In this blog post, Lee Harrison, Director Product Marketing, Siemens EDA explains how quality, reliability, safety and security are key considerations when designing ICs but not all chips and systems are designed equal. If you are designing SoCs for automotive, aerospace or medical applications, then the process of designing, manufacturing, testing, and in-life monitoring becomes much more challenging. Typical design challenges include adherence to standards and regulations, managing capital investments and engineering resources, securing the right tools and flows, and establishing methods to manage the vast amounts of data that inform each step in the lifecycle of the device. The DFT software solutions from Tessent are built to address these challenges and to help get products to market faster. Read the full post to discover more. https://sie.ag/7Cnb9D #3DIC #DFT #Tessent #DFTMarketLeader #TessentStreamingScanNetwork #TessentSSN #SiemensEDA