(Counter) Paper - 1 - 7967 - 163 PDF
(Counter) Paper - 1 - 7967 - 163 PDF
7KH Counters
By:'U(KDE$+$/+LDO\
Electrical Engineering Department
7KH Counters
DIGITAL ELECTRONICS
Introduction COUNTERS
Asynchronous counters
Synchronous counters
the clock signal (CLK) is only used to clock the first FF.
Synchronous Counters ,
the clock signal (CLK) is applied to all FF, which means that
all FF shares the same clock signal,
thus the output will change at the same time.
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Introduction COUNTERS
Thus, the number of flip-flops used depends on the MOD of the counter
(ie; MOD-4 use 2 FF (2-bit), MOD-8 use 3 FF (3-bit), etc..)
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Asynchronous Counters
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Present State
Next State
Q1Q0
Q1Q0
00
01
01
10
10
11
11
00
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00
11
01
10
Waveform
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Waveform
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Waveform
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Waveform
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1
Next State
CBA
000
001
CBA
001
010
010
011
100
101
110
111
011
100
101
110
111
000
0
7
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2
5
3
4
1
Exercise :
Figure .4 : MOD 8 Asynchronous Up Counter
CLK
K
C
1
CLK
K
Q
CLK
CLK
A
0
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1
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1
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1
A (LSB)
1
B (MSB)
CLK
Q
CLK
CLK
A
Binary 0 3
2 1 0 3
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1 0
1
Asynchronous Counters
Exercise:
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1
MOD-6 counters will count from 010 (0002) to 510(1012) and after
that will recount back to 0 10 (0002) continuously.
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1
Next St.
CBA
000
001
010
011
100
101
CBA
001
010
011
100
101
000(110)
2
3
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1
Next St.
CBA
000
001
010
011
100
101
CBA
001
010
011
100
101
000(110)
1
CLK
C(MSB)
1
CLK
CLK
CLK
K Q
K Q
K Q
CLR
CLR
CLR
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2
Q3 Q2 Q1 Q0
Q0
1
CP0
CP1
MR1
MR2
J Q
CLK
K
Q
CLR
CP1
74293
CP0
Q1
J Q
CLK
K
Q
CLR
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Q2
J Q
CLK
K
Q
CLR
Q3
J Q
CLK
K
Q
CLR
2
Exercise:
CP1
74293
MR2
CP0
Q3 Q2 Q1 Q0
1
DIGITAL ELECTRONICS
0
2
Exercise:
CP1
74293
MR2
CP0
Q3 Q2 Q1 Q0
MR1
Answer : MOD 8
CP1
74293
MR2
CP0
Q3 Q2 Q1 Q0
1
0 1
Answer : MOD 5
2
CP1
74293
MR2
CP0
Q3 Q2 Q1 Q0
1
1
Answer : MOD 14
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2
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2
The binary counters previously introduced have two to the power n states. But
counters with states less than this number are also possible. They are designed to
have the number of states in their sequences, which are called truncated sequences.
These sequences are achieved by forcing the counter to recycle before going
through all of its normal states.
A common modulus for counters with truncated sequences is ten. A counter with
ten states in its sequence is called a decade counter . The circuit below is an
implementation of a decade counter.
2
2
',*,7$/(/(&7521,&6
30
',*,7$/(/(&7521,&6
3
',*,7$/(/(&7521,&6
3
Asynchronous Counters
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3
Synchronous Counters
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3
Synchronous Counters
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3
Synchronous Counters
Now, the question is, what do we do with the J and K inputs? We know that we still have to
maintain the same divide-by-two frequency pattern in order to count in a binary sequence, and
that this pattern is best achieved utilizing the "toggle" mode of the flip-flop, so the fact that the
J and K inputs must both be (at times) "high" is clear. However, if we simply connect all the J
and K inputs to the positive rail of the power supply as we did in the asynchronous circuit, this
would clearly not work because all the flip-flops would toggle at the same time: with each and
every clock pulse!
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3
Synchronous Counters
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3
Synchronous Counters
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3
Procedure to design synchronous counter are as follows:STEP 1: Obtain the State Diagram.
STEP 2: Obtain the Excitation Table using state transition
table for any particular FF (JK or D). Determine number
of FF used.
STEP 3: Obtain and simplify the function of each FF input
using K-Map.
STEP 4: Draw the circuit.
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3
0
3
Binary
11
01
10
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FF INPUT
J
K
0
X
1
X
X
1
X
0
Excitation table
Present State
Next State
BA
0 0
0 1
1 0
1 1
BA
0 1
1 0
1 1
0 0
Input, J K
JB K B
0 X
1 X
X 0
X 1
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JA KA
1 X
X 1
1 X
X 1
4
B
A
0
0 0
1 X
1
1
X
JB = A
0
0 1
1 1
1
X
1
KB = A
1
1
1
KA = 1
B
A
0
0 X
1 0
1
X
X
JA = 1
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0
0 X
1 X
4
B (MSB)
J A QA
JB QB
CLK
CLK
KA Q A
KB QB
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4
N = 2
8 = 2n
n = log 8 / log 2
= 3 Flip Flop ( 3 Bit )
n
M = 2 -1
= 23 - 1
=8-1=7
N = Modulo/MOD
n = Flip Flop Used
M = Maximum Number To Be Count
DIGITAL ELECTRONICS
4
Next State
Q2
Q1
Q0
Q2
Q1
Q0
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Q0 = QA
Q1 = QB
Q2 = Q c
4
Present
State
Excitation Table
(Jadual Ujaan Flip Flop
JK)
_
J
K
Q
Q
Next State
Present inputs
QC
QB
QA
QC
QB
QA
JCKC
JBKB
JAKA
0X
0X
1X
0X
1X
X1
0X
X0
1X
1X
X1
X1
X0
0X
1X
X0
1X
X1
X0
X0
1X
X1
X1
X1
X indicates a "don
"dont care" condition.
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4
Step 4: Use Karnaugh maps to identify the present state logic functions
for each of the inputs.
E.g. for J 2 we get:
QcQB
QcQB
00
QA
QA
JC
01
0
1
11
10
Q BQ A
QBQA
JB =
QA
KB =
QA
JA =
KA =
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4
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4
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Solution:
Step 1 : Flip Flop Used
n
Find Modulo, N= 2
n
M = 7, M = 2 -1 = 7
n
2 =N
2 = 8, n = log 8 / log 2
n = 3 bit = 3 Flip Flop.
DIGITAL ELECTRONICS
Solution:
Step 2 : State Transation
Diagram, to count 4, 7, 3, 0
and 2.
Next
State
Qn+1
100
010
000
111
011
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Present
State
Next State
JC KC JB KB JA KA
QC
QB
QA
QC
QB
QA
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00
01
11
10
A
0
0
1
x
1
x
3
K-Map For
JA = QC
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CB
K-Map For
K-Map For
JA = QC
KA = QC
00
01
11
10
01
11
10
0
0
CB 00
X
2
X
1
1
6
X
3
X
5
DIGITAL ELECTRONICS
1
1
0
3
X
7
CB
K-Map For
K-Map For
JB = 1
KB = QC
00
01
11
10
01
11
10
X
0
CB 00
X
2
X
1
1
6
X
3
X
5
DIGITAL ELECTRONICS
1
1
0
3
X
7
K-Map For
K-Map For
JC = QA+QB
KC = QB
CB 00
01
11
10
1
0
00
01
11
10
CB
X
2
0
1
X
6
X
3
X
7
DIGITAL ELECTRONICS
X
1
1
3
X
7
KA = QC,
JA QA
J B QB
JC QC
KA QA
KB QB
K C QC
CP,CLOCK PULSE
DIGITAL ELECTRONICS
Synchronous Counter
Exercises:
Design a counter to count in the following
sequence: 6, 4. 2, 3, 1.
5