STPM 32
STPM 32
Description
Features The STPM3x is an ASSP family designed for high
Active power accuracy: accuracy measurement of power and energies in
– < 0.1% error over 5000: 1 dynamic range power line systems using the Rogowski coil,
current transformer or shunt current sensors. The
– < 0.5% error over 10000: 1 dynamic range
STPM3x provides instantaneous voltage and
Exceeds 50-60 Hz EN 50470-x, IEC 62053-2x, current waveforms and calculates RMS values of
ANSI12.2x standard requirements for AC watt voltage and currents, active, reactive and
meters apparent power and energies. The STPM3x is a
Reactive power accuracy: mixed signal IC family consisting of an analog and
– < 0.1% error over 2000:1 dynamic range a digital section. The analog section consists of
up to two programmable gain low-noise low-offset
Dual mode apparent energy calculation amplifiers and up to four 2nd order 24-bit sigma-
Instantaneous and averaged power delta ADCs, two bandgap voltage references with
RMS and instantaneous voltage and current independent temperature compensation, a low
drop voltage regulator and DC buffers. The digital
Under and overvoltage detection (sag and section consists of digital filtering stage, a
swell) and monitoring hardwired DSP, DFE to the input and a serial
Overcurrent detection and monitoring communication interface (UART or SPI). The
UART and SPI serial interface with STPM3x is fully configurable and allows a fast
programmable CRC polynomial verification digital system calibration in a single point over the
entire current dynamic range.
Programmable LED and interrupt outputs
Four independent 24-bit 2nd order sigma-delta Table 1. Device summary
ADCs Order code Package Packing
Two programmable gain chopper stabilized
low-noise and low-offset amplifiers STPM34TR QFN32L 5x5x1 Tape and reel
Vcc supply range 3.3 V ± 10% STPM32TR QFN24L 4x4x1 Tape and reel
Inhalt
1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Measurement error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3 ADC offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.1 General operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.2 Functional description of the analog part . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.2.1 Power management section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.2.2 Analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2.4 Power-on-reset (POR) and enable (EN) . . . . . . . . . . . . . . . . . . . . . . . . 36
8.3 Functional description of the digital part . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.3.1 Digital front end (SDSx bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.3.2 Decimation block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.3.3 Filter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3.4 DC cancellation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3.5 Fundamental component filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3.6 Reactive filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4 Functional description of hardwired DSP . . . . . . . . . . . . . . . . . . . . . . . . . 40
10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.1 Register map graphical representation . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.2 Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.3 UART/SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
10.4 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
List of tables
List of figures
1 Schematic diagram
CLKOUT/
ZCR LED1 LED2 INT1 INT2 EN
2nd
VIP1 order Phase
ΣΔ Decimation compensation
VIN1 modulator
2nd
VIP2 order Phase
ΣΔ Decimation compensation
VIN2 modulator
Filters
DSP
nd
2
IIP1 order
ΣΔ Phase
PLNA Decimation compensation
modulator
IIN1
2nd
order
IIP2
ΣΔ Phase
PLNA modulator Decimation compensation
IIN2
VDDD
VRefC2
VOLTAGE
LDR 1.2 V
REFERENCE
VRefV2
VOLTAGE
VRefC1
VCC LDR 3.0 V REFERENCE OSC 16 MHz SPI/UART
VRefV1
VDDA VREF2 VREF1 XTAL1 XTAL2 SCS MISO/ MOSI/ SCL SYN
TXD RXD
GIPG1303141224LM
CLKOUT/
ZCR LED1 LED2 INT1 INT2 EN
2nd
VIP1 order Phase
ΣΔ Decimation compensation
VIN1 modulator
nd
2
IIP1 order
Phase
PLNA ΣΔ Decimation
compensation
Filters DSP
IIN1 modulator
nd
2
IIP2 order
Phase
PLNA ΣΔ Decimation
modulator compensation
IIN2
VDDD
VRefC2
LDR 1.2 V VOLTAGE
REFERENCE
VRefV2
VRefC1
VOLTAGE
VCC LDR 3.0 V REFERENCE OSC 16 MHz SPI/UART
VRefV1
VDDA VREF2 VREF1 XTAL1 XTAL2 SCS MISO/ MOSI/ SCL SYN
TXD RXD
GIPG1303141235LM
CLKOUT/
ZCR LED1 LED2 INT1 EN
nd
2
VIP1 order
ΣΔ Decimation Phase
compensation
VIN1 modulator
Filters DSP
nd
2
IIP1 order
PLNA ΣΔ Decimation Phase
compensation
IIN1 modulator
VDDD
LDR 1.2 V
VRefC1
VOLTAGE
LDR 3.0 V
VCC REFERENCE OSC 16 MHz SPI/UART
VRefV1
GIPG1303141239LM
2 Pin configuration
MOSI/RXD
MISO/TXD
GNDD
GNDD
VDDD
SCL
SCS
28 SYN
32
31
30
29
27
26
25
CLKOUT/ZCR 1 24 NC
CLKIN/XTAL2 2 23 VCC
XTAL1 3 22 GND_REG
LED1 4 21 VDDA
STPM34
LED2 5 20 GNDA
INT1 6 19 VREF2
INT2 7 18 GND_REF
EN 8 17 VREF1
11
10
12
13
14
15
16
9
IIN1
IIP1
VIN1
VIP1
IIP2
VIN2
VIP2
IIN2
GIPG1303141253LM
MOSI/RXD
MISO/TXD
GNDD
VDDD
SCL
SCS
SYN
NC
32
31
30
29
28
27
26
25
CLKOUT/ZCR 1 24 NC
CLKIN/XTAL2 2 23 VCC
XTAL1 3 22 GND_REG
LED1 4 21 VDDA
STPM33
LED2 5 20 GNDA
INT1 6 19 VREF2
INT2 7 18 GND_REF
EN 8 17 VREF1
11
10
IIN1 12
13
14
15
16
9
IIP1
VIN1
VIP1
IIP2
NC
IIN2
NC
GIPG1303141257LM
7%%%
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4$-
$-,065;$3 (/%%
$-,*/95"- 7$$
95"- (/%@3&(
451.
-&% 7%%"
-&% (/%"
*/5 (/%@3&'
73&'
**1
7*1
**/
&/
7*/
(*1(-.
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. All values are referred to GND.
QFN32L 5x5x1 30
RthJA Thermal resistance junction-ambient °C/W
QFN24L 4x4x1 35
Note: This value is referred to single-layer PCB, JEDEC standard test board.
4 Electrical characteristics
VCC = 3.3 V, CL= 1 μF between VDDA and GNDA, CL = 4.7 μF between VDDD and GNDD,
CL= 1 μF between VCC and GND, CL = 100 nF between VREF1, 2 and GNDREF,
FCLK = 16 MHz, TAMB = 25 °C, EN = VCC, SPI/UART not used, unless otherwise specified.
General section
Operating junction
TOP - -40 - 105 °C
temperature range
Operating supply
VCC - 2.95 3.3 3.65 V
voltage
STPM32 - 4.3 -
STPM33 - 5.0 -
STPM34 - 5.9 -
STPM34
Primary channel ON: ENVREF1 = 1,
enV1 = enC1 = 1 - 4.5 -
ICC Operating current mA
Secondary channel OFF: ENVREF2 =
0, enV2 = enC2 = 0
STPM34
Primary current channel ON only:
ENVREF1 = 1, enV1 = 0, enC1 = 1 - 4.0 -
Secondary channel OFF: ENVREF2 =
0, enV2 = enC2 = 0
FCLK Nominal frequency - - 16 - MHz
Interface selection
t_comm - 125 - - ns
timing
External Clock Source(1)
Duty cycle of CLKIN
Duty cycle - 40 - 60 %
signal
Rise time (10% to 90%)
t_rise - - - 3 ns
of CLKIN signal
Crystal oscillator(1)
Maximum critical
Gm_crit_max - - - 0.46 mA/V
crystal gm
DL Drive level - - 100 - uW
Internal capacitance of
COSC_IN - - 4 - pF
oscillator inputs
Standby current
ISTBY EN = GND - <1 - A
consumption
Analog regulated
VDDA - - 2.85 - V
voltage
Digital regulated
VDDD - - 1.2 - V
voltage
Power supply rejection
PSRRREGS 50 Hz - 50 - dB
ratio(1)
Analog inputs (VIP1, VIN1, VIP2, VIN2, IIP1, IIN1, IIP2, IIN2)
Digital I/O (CLKOUT/ZCR, LED1, LED2, INT1, INT2, MISO, MOSI, SCL, SCS, SYN)
0.75
VIH Input high-voltage - - 3.3 V
VCC
VIL Input low-voltage VCC = 3.2 V -0.3 - 0.6 V
VCC-
VOH Output high-voltage IO = -1 mA, VCC = 3.2 V - - V
0.4
VOL Output low-voltage IO = +1 mA, VCC = 3.2 V - - 0.4 V
Oversampling
OSF - - 4 - MHz
frequency
DR Decimation ratio - - 1/512 - -
Fs Sampling frequency - - 7.8125 - kHz
FBW Flat band < 0.05 dB allowed ripple 2 - - kHz
BW Effective bandwidth -3 dB, HPF = 0 0 - 3600 Hz
DC measurement accuracy
SPI timings(3)
UART timings(3)
t1 - CS enable to RX start 5 - - ns
t2 - Stop bit to CS disable 1 - - μs
t3 - CS disable to TX idle hold time - - 250 ns
Enable to high level VCC = 3.3 V ± 10%,
tpZH - 21 - ns
time VIN = 0 to 3 V, 1 MHz,
Rise time = fall time = 6 ns
Disable from high level
tpHZ RL = 1 kΩ, CL = 50 pF - 11 - ns
time
see Figure 10
SYN timings(3)
Time between
t_ltch - 20 - - ns
de-selection and latch
t_lpw Latch pulse width - 4 - - μs
Time between two
t_w consecutive latch - 4 - - μs
pulses
t_rpw Reset pulse width - 4 - - μs
Time between pulse
t_rel - 40 - - ns
and selection
Time between power-
t_startup - 35 - - ms
on and reset
1. Guaranteed by design.
2. Guaranteed by characterization.
3. Guaranteed by application.
t_en
SCS
t_clk
t_cpw
SCL
MOSI
t_setup
t_hold
t_lpw t_rpw
SYN
*1'
WS=/ WS/=
0,62 9FF
9
92/ 9
92/
*,3*/0
WS=+ WS+=
92+
92+ 9
9
0,62 *1'
*,3*/0
Figure 10. Output load circuit for enable and disable times
3UREH
.RKP 9FF
0,62 *1'
S)
3UREHDQGERDUGFDSDFLWDQFHLQFOXGHG
*,3*/0
Pin programmability
Table 6. Programmable pin functions
Name Multiplexed function Functional description I/O
Figure 11 below shows the reference schematic of an application with the following
properties:
Constant pulses CP = 41600 imp/kWh
INOM = 5 A
IMAX = 90 A
Typical values for current sensor sensitivity are indicated in Table 7.
For more information about the application dimensioning and calibration please refer to
Section 9 on page 78.
Note: Above listed components refer to typical metering applications. The STPM3x operation is
not limited to the choice of these external components.
6 Terminology
6.1 Conventions
The lowest analog and digital power supply voltage is named GND and represents the
system ground. All voltage specifications for digital input/output pins are referred to GND.
The highest power supply voltage is named VCC. The highest core power supply is internally
generated and is named VDDA. Positive currents flow to a pin. Sinking current means that
the current is flowing to the pin and it is positive. Sourcing current means that the current is
flowing out of the pin and it is negative. A positive logic convention is used in all equations.
Equation 1
e% = measuredpower – truepower-
----------------------------------------------------------------------------------
truepower
All measurements come from the comparison with a higher class power (0.02% error) meter
reference. Output bitstream of modulator is indicated as bsV and bsC for voltage and
current channel respectively.
Active energy error is measured at T= 25 °C, over phi (0°, 60°, -60°).
Reactive energy error is measured at T= 25 °C, over phi (90°, -90°, 60°, -60°).
Figure 12. Active energy error vs. current Figure 13. Active energy error vs. current
gain=2x integrator off gain=16x integrator off
1
1
0.8 phi=0°
0.8
phi=-60°
0.6 phi=+60°
phi=0°
0.6
phi=+60°
phi=-60°
0.4
0.4
0.2
0.2
error[%]
error[%]
0
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
0.01 0.1 1 10 100 -1
Current Amplitude to full -scale ratio [%] 0.01 0.1 1 10 100
Current Amplitude to full - scale ratio [%] GIPG1403141120LM
GIPG1403141112LM
Figure 14. Active energy error vs. frequency Figure 15. Active energy error vs. frequency
gain=2x integrator off gain=16x integrator off
1
1
phi=0°
phi=0° 0.8 phi=+60°
0.8 phi=+60°
phi=-60°
phi=-60°
0.6
0.6
0.4 0.4
error [%]
0.2 0.2
error [%]
0 0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
45 50 55 60 65
Frequency [Hz] -1
45 50 55 60 65
Frequency [Hz]
GIPG1403141123LM GIPG1403141129LM
Figure 16. Reactive energy error vs. current Figure 17. Reactive energy error vs. current
gain=2x integrator off gain=16x integrator off
1 1
0.8 0.8
0.2 0.2
error[%]
error[%]
0 0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
0.01 0.1 1 10 100 0.01 0.1 1 10 100
Current Amplitude to full - scale ratio [%] Current amplitude to full -scale ratio [%]
GIPG1403141132LM GIPG1403141135LM
Figure 18. Reactive energy error vs. frequency Figure 19. Reactive energy error vs. frequency
gain=2x integrator off gain=16x integrator off
1
1
phi=+90°
phi=+90° 0.8 phi=-90°
0.8 phi=-90° phi=+60°
phi=+60° phi=-60°
phi=-60° 0.6
0.6
0.4
0.4
0.2
error [%]
0.2
error [%]
0
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
45 50 55 60 65
-1 Frequency [Hz]
45 50 55 60 65
Frequency [Hz]
GIPG1403141137LM GIPG1403141141LM
Figure 20. Active energy error vs. current Figure 21. Reactive energy error vs. current
gain=16x integrator on gain=16x integrator on
1 1
phi=0°
0.8 phi=-60°
0.8
phi=+60°
0.6
0.6 phi=+60°
phi=-60°
phi=+90°
0.4 phi=-90°
0.4
0.2
0.2
error [%]
error [%]
0
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
0.010 0.100 1.000 10.000 100.000 -1
Current amplitude to full -scale ratio [%] 0.010 0.100 1.000 10.000 100.000
Current amplitude to full - scale ratio [%]
GIPG1403141143LM GIPG1403141145LM
8 Theory of operation
VDDD
TC2
ENVREF1 VRefC2
4.7 uF VOLTAGE
LDR 1.2 V REFERENCE
GNDD VRefV2
TC1
ENVREF2 VRefC1
3.3 V VCC
VOLTAGE
LDR 3.0 V REFERENCE
1 μF VRefV1
GND_REG
100 nF
1 uF 100 nF
GIPG1303141315LM
0 0 0 -30
0 0 1 0
0 1 0 30 (default)
0 1 1 60
1 0 0 90
1 0 1 120
1 1 0 150
1 1 1 180
0 0 X2 ± 300 mV
0 1 X4 ± 150 mV
1 0 X8 ± 75 mV
1 1 X16 ± 37.5 mV
The oversampling frequency of the modulators is 4 MHz, the output bitstreams of the 2nd
order sigma-delta modulators relative to the voltage and to the two current channels are
available on INT and LED output pins through the proper configuration (see configuration bit
map).
nd
2
VIPx order bsV
ΣΔ
VINx modulator
DFE
GAINx [1:0]
nd
2
IIPx
order
bsC
PLNA ΣΔ
IINx modulator
GIPG1303141321LM
PLNA uses the chopping technique to cancel the intrinsic offset of the amplifier.
A dedicated block generates chopper frequencies for voltage and current channels.
The amplified signals are fed to the 2nd order sigma-delta modulator.
The analog-to-digital conversion in the STPM3x is carried out using four 2nd order sigma-
delta converters. A pseudo-random block generates pseudo-random signals for voltage and
current channels. These random signals implement the dithering technique in order to de-
correlate the output of the modulators and avoid accumulation points on the frequency
spectrum. The device performs A/D conversions of analog signals on four independent
channels in parallel.
Dithering
a1 a2
D/A
GIPG1303141326LM
The sigma-delta modulators convert the input signals into a continuous serial stream of “1”
and “0” at a rate determined by the sampling clock. In the STPM3x, the oversampling clock
is equal to 4 MHz.
1-bit DAC in the feedback loop is driven by the serial data stream. DAC output is subtracted
from the input signal and from the integrated error. If the loop gain is high enough, the
average value of DAC output (and therefore the bitstream) can approach to the input signal
level. When a large number of samples are averaged, a very precise value of the analog
signal is obtained. This average is described in DSP section.
The converted sigma-delta bitstreams of voltage and current channels are fed to the internal
hardwired DSP unit, which decimates, filters and processes those signals in order to boost
the resolution and to yield all necessary signals for computations.
Figure 26. Different oscillator circuits (a): with quartz; (b): with external source
CLKOUT/ZCR CLKOUT/ZCR
CLKIN/XTAL2 CLKIN/XTAL2
XTAL1 XTAL1
1 MΩ
15 pF 16 MHz 15 pF
GIPG1303141329LM
From the external 16 MHz clock, the entire clock tree is generated. All internal clocks have
50% duty cycle.
CLKOUT pin can be used to feed another STPM3x device clock with 16 MHz, when multiple
STPM3x are used in cascade as shown in Figure 27.
1 MΩ
15 pF 15 pF
GIPG2503141257LM
EN VDDD
LDR 1.2 V
PowerOK_1.2 V
POR
PowerOK_3.0 V
VDDA
LDR 3.0 V
VCC
CLKIN
XTAL1
OSC
16 MHz Osc
XTAL2
GIPG1303141331LM
The STPM3x also has an enable pin (EN) which works as follows:
EN is high: when the power is on and EN pin raises, the device is enabled and starts
after POR procedure as above described.
EN is low: when the power is on and EN pin has a transition high to low, the device is
disabled. It stops and the internal digital memory is deleted so a new initialization is
needed when EN goes back to high.
After POR, to ensure a correct initialization, it is necessary to perform a reset of DSP and
communication peripherals through three SYN pulses (see Section 8.6.1 on page 68) and
a single SCS pulse, as shown in the figure below. SCS pulse can be performed before or
after SYN pulses, but minimum startup time before reset (as indicated in Table 5 on
page 17) has to be respected.
1 1 Phase 1 24 24
compensation
Calibration
SCLK SCLK SCLK DCLK DCLK
1 1 Phase 1 24 24
compensation Calibration
SCLK SCLK SCLK DCLK DCLK
GIPG1403141159LM
The decimation ratio, out of the filter cascade, is 512 so that outputs of this block are parallel
24-bit data at a rated frequency of 7.8125 kHz.
The decimation block has a magnitude response -3 dB band of 3.6 kHz and a 2.0 kHz flat
band.
Vx[23:0]
HPF LPF
Cx [23:0]
HPF ROCOIL LPF
INT
GIPG1403141207LM
0000 0.0625
0001 0.125
0010 0.25
0011 0.5
0100 1
0101 2
0110 4
0111 8
1000 16
1001 32
1010 64
1011 128
1100 256
1101 512
1110 1024
1111 2048
The signal chain for each power, energy calculations and related frequency conversion are
explained in the following section.
Vx Fund[23:0] LPF Σ
LPF Offset F LED
Cx Fund[23:0]
CHVx[11:0] LPF
BHPFVx Offset LPF Σ A LED
bsV Vx[23:0] APMx
VIPx Vx Data [23:0]
2nd
Phase Decimation HPF X2
order ΣΔ
VINx
Compens. √¯
modulator
2
X
CHCx [11:0] Reac.
BHPFCx ROCx Offset LPF Σ R LED
Filter AEMx
DS10272 Rev 8
Cx[23:0]
bsC
IIPx CxData [23:0] Σ S LED
2nd
HPF ROCOIL
PLNA Phase Decimation INT
order ΣΔ
INx VxRMS Data [14:0]
modulator
Compens. RMS
Offset
Figure 32. DSP block diagram
RMS
CxRMS Data [16:0]
GIPG1703140842_1LM
STPM32, STPM33, STPM34
STPM32, STPM33, STPM34 Theory of operation
CHVx [11:0]
BHPFVx
Vx[23:0]
bsV
VIPx Vx Data [23:0]
ADC Phase HPF
VINx OFAx[9:0]
Compensation
PHx Active Power[28:0]
GIPG1703140852LM
The active power is calculated simultaneously and independently for primary and secondary
current channels.
Results of the calculated quantities are stored in the registers as follows:
EP1 = primary current channel active energy PH1 ACTIVE Energy[31:0]
P1 = primary current channel active power PH1 Active Power[28:0]
p1(t) = primary current channel instantaneous active power PH1 Momentary Active
Power[28:0]
EP2 = secondary current channel active energy PH2 Active Energy[31:0]
P2 = secondary current channel active power PH2 Active Power[28:0]
p2(t) = secondary current channel instantaneous active power PH2 Momentary Active
Power[28:0]
Active power measurements have a bandwidth of 3.6 kHz and include the effects of any
harmonic within that range.
Figure 34. Fundamental active power and energy calculation block diagram
CHVx [11:0]
BHPFVx
Vx[23:0] Vx Data [23:0]
bsV
VIPx Phase LPF VxFund[23:0]
ADC HPF
VINx OFAFx[9:0]
Compensation
PHx Fundamental Power[28:0]
GIPG1703140903LM
CHVx [11:0]
BHPFVx
Vx Data [23:0]
VIPx bsV Phase
Vx[23:0] Vx Fund[23:0]
ADC Compensat. HPF LPF
VINx OFRx[9:0]
IIPx
DS10272 Rev 8
bsC Cx[23:0]
ADC Phase HPF ROCOIL
PLNA Compensat. LPF CxFund[23:0]
IINx INT
Cx Data [23:0]
Figure 35. Reactive power and energy calculation block diagram
GIPG2603141329LM
45/121
Theory of operation
121
Theory of operation STPM32, STPM33, STPM34
Equation 2
2 2
S vec = P +Q
RMS methodology uses the product of RMS data of voltage and current. This value can
be compensated by the apparent power offset calibration block (OFSx[8:0] in
DSP_CR10 and DSP_CR12).
Equation 3
S RMS = V RMS I RMS
The apparent energy is calculated from vectorial or from RMS apparent power according to
AEMx configuration bit in DSP_CR1 and DSP_CR2.
APMx
PHxFundamental Power[28:0]
0 PHxApparent VectorialPower[28:0]
PHx Active Power[28:0] X2
1
√¯
PHxReactive Power[28:0] AEMx
X2
1
OFSx [9:0] Σ S LED
0
VxRMS Data [14:0]
PHxApparent Energy[31:0]
Offset
Power
GIPG2803141118LM
Gain AV = 2 AI = 16 AI = 2 AI = 16
(1)
Calibrators calV = 0.875 calI = 0.875
R2 R
Sensitivity -------------------
-[V/A] kS = RShunt [ k S = ------b- [V/A] kS = kRoCoil [VA
R1 + R2 N
AV AI AI
ΣΔ bitstream(2) V = V inV ---------
- V = V inC ---------
- V = V inC ------------------------
V ref V ref V ref K int
Active power
Constant pulse
Pulse value
Power register
normalized
2
P pulse V ref 1 + R 1 R 2 W
Power LSB value LSB P = ---------------- DClk = ------------------------------------------------------------------------------------
- ------------
29 28 LSB
2 k int A V A I k S cal V cal I 2
2
P pulse V ref 1 + R 1 R 2 Wh-
Energy LSB value LSB E = ---------------- - -----------
= -------------------------------------------------------------------------------------------------------------------------
18 17 LSB
2 3600 DClk k int A V A I k S cal V cal I 2
1. CHVx and CHCx calibrator bits introduce in the signal processing a correction factor of ±12,5% (with an attenuation from
0,75 to 1). In order to have the maximum available up/down correction range, by default calibrator values are in the middle
of their range (0x800) corresponding to an attenuation factor calV = calI = 0,875.
2. ƩΔ bitstream should be kept lower than 0.5 (50%) to minimize modulator distortions.
3. LED_PWM is the LED frequency divider that can be set through LPWx bits in DSP_CR1 and DSP_CR2 control registers
for primary and secondary current channels respectively. Default value is 1. Please refer to Table 36 on page 81.
For each power register, a configurable offset value (default = 0) can be added to the
instantaneous power p(n) through OFA[9:0], OFAF[9:0], OFR[9:0], OFAS[9:0] bits in this
way:
Equation 4
OFx 9 2
p n = p n + –1 OFx 8:0 2
Equation 5
1 t0 + T 2
V RMS = --- v t dt
T t0
Equation 6
1 t0 + T 2
I RMS = --- i t dt
T t0
/ LPF
-
1/2
LPF
GIPG2803141121LM
If the cut-off frequency of an LP filter is set much below the input signal spectrum, it can be
considered as an average operator. In this case and according to the figure, the first LP filter
averages its input signal which is produced by division and multiplication:
Equation 7
2
X
R = ------
R
By assumption, the feedback signal R is DC type and therefore, it can be extracted from the
average operation and the above equation can be rearranged into:
Equation 8
2 2
R = X
Equation 9
2
R = X
Equation 10
The LP filter cuts the 2nd harmonic component of input signal multiplying it by a dumping
factor α:
Equation 11
1 – cos 2t A
R = A -------------------------------------- ------- 1 – --- cos t
2 2 2
R result is a DC signal plus the 2nd harmonic ripple with the amplitude of α/2.
For dumping factor | α |<<1:
Equation 12
A
R -------
2
RMS updated values are available in DSP_REG14 and DSP_REG15 registers every
128 μs.
Raw ADC samples are also available for post-processing by MCU in registers from
DSP_REG2 to DSP_REG9.
By taking into account the internal parameters in Table 13 and the analog front end
components in Table 14, LSB values of voltage and current registers are the following:
V ref 1 + R 1 R 2
Voltage RMS LSB value LSB VRMS = ----------------------------------------------- V
15
cal V A V 2
V ref
Current RMS LSB value -A
LSB IRMS = --------------------------------------------------------
17
cal I A I 2 k S k int
23
Instantaneous voltage normalized – 1 2 v n 23 + v n 22:0
v n V norm = ---------------------------------------------------------------------------------------
23
2
23
Instantaneous current normalized – 1 2 i n 23 + i n 22:0
i n I norm = ------------------------------------------------------------------------------------
23
2
V ref 1 + R 1 R 2
Instantaneous voltage LSB value LSB VMOM = ----------------------------------------------- V
23
cal V A V 2
V ref
Instantaneous current LSB value -A
LSB IMOM = --------------------------------------------------------
23
cal I A I 2 k S k int
VxFund[23:0] ZRC_V
ZCR detector
CxFund[23:0] ZRC_I
GIPG2803141125LM
Signal
ZRC
GIPG2803141129LM
FClk 125kHz
GIPG2803141133LM
Period measurement
Starting from ZRC signals, line period and voltage/current phase shift are calculated.
Period information for the two phases is located in DSP_REG1 register.
The measurement of the period is from ZRC signal of voltage channel. The period is
calculated like an average of last eight measured periods.
The initial values of period are set on 0x9C4 (2500). LSB of period is 8 s given by FCLK
clock = 125 kHz. Limits to consider the correct period are between 0x600 (1536) and 0x800
(3840) corresponding to a frequency range between 32.55 and 81.38 Hz.
If the voltage signal frequency is out of this range, PER_ERR status bit is set in
DSP_SR1/2.
PER_ERR = 0: period in the range
Equation 13
Resolution at 50 Hz is:
Equation 14
When PER_ERR bit is set, Cx_PHA[11:0] is not updated and keeps the previous correct
value.
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Input signal
V SAG R2
Percentage of FS input V in_SAG_peak FS = -------------- A V 2 cal V -------------------
-
V ref R1 + R2
V SAG R2
Register value SAG = -------------- A V 2 cal V -------------------
- D SAG HEX
V ref R1 + R2
R 1 + R 2 V ref
Register LSB RMS value LSB SAG = ------------------------------------------------------------------ V
A V 2 R 2 cal V D SAG
To calculate the filtering time for the sag event, we consider the time in which the nominal
instantaneous voltage is below the sag threshold, that is:
Equation 15
V SAG 1000
time = 2 arc sin -------------- ------------- ms
V 2f
L L
To correctly distinguish between normal sinusoidal voltage and sag event, the filtering time
should be added to this component, for example half line period (10 ms at 50 Hz). Since
LSB of SAG_TIME_THRx register is 8 s (FCLK = 125 kHz), the value to set is:
Equation 16
V SWELL R2
Register value - A V 2 -------------------
SWELL V = -------------------- - cal V D SWELL HEX
V ref R1 + R2
V ref R 1 + R 2
Register LSB RMS value -V
LSB SWELL = ------------------------------------------------------------------------
A V 2 R 2 cal V D SWELL
I SWELL
Register value - A I 2 k S cal I D SWELL HEX
SWELL C = ------------------
V ref
V ref
Register LSB RMS value -A
LSB SWELL = --------------------------------------------------------------------
A I 2 k S cal I D SWELL
Tamper module monitors active energy registers of the two channels. Tamper condition is
detected when the absolute value of the difference between the two active energy values is
greater than the chosen percentage of the averaged value. This occurs when the following
equation is satisfied:
Equation 17
|EnergyCH1 - EnergyCH2| > TOL * |EnergyCH1 + EnergyCH2|
where TOL is selected according to Table 19.
Detection threshold is much higher than the accuracy difference of the current channels,
which should be less than 0.2%, but, some headroom should be left for possible transition
effect, due to accidental synchronism of load current change at the rate of energy sampling.
Tamper circuit works if energies associated with the two current channels are both positive
or negative, if two energies have different sign, a warning flag “TAMPER OR WRONG” in
DSP_SR1 or DSP_SR2 is set.
The channel with higher energy is signaled by PHx TAMPER status bit in DSP_SR1 or
DSP_SR2.
When internal signals are not good enough to perform the calculations, for example line
period is out or range or sigma-delta signals from analog section are stuck at high or low
logic level, the tamper module is disabled and its state is set to normal.
8.4.12 AH accumulation
In this particular tamper, the neutral wire is disconnected from the meter and the STPM3x
does not sense the voltage anymore, while it keeps sensing the current information. In these
conditions, AH accumulator can be used by the microcontroller to regularly calculate the
billing based on a nominal voltage value due to the following equation:
Equation 18
Energy = AH_ACC[31:0]·LSBAH_ACC·VNOM [Wh]
If voltage is too low (sag event detected) or period is wrong (PER_ERR = 1) and RMS value
of current is high enough, RMS current is accumulated in the register AH_ACC[31:0]. Value
in PHx AH_ACC[31:0] register is increased with a DCLK frequency.
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The accumulation of current values is controlled by AH status bit. AH bit is set when
PER_ERR = 1 and real values of current overcome an upper threshold set in AH_UPx[11:0]
in DSP_CR9 and DSP_CR11. This bit is cleared when RMS current drops below
AH_DOWNx[11:0] threshold in DSP_CR10 and DSP_CR12.
To stabilize the current accumulation, SAG event should be monitored by setting some
thresholds in the related register.
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30 Tamper
Tamper status(1)
31 Tamper or wrong connection
1. Valid for the STPM33 and STPM34 only.
After the selected communication interface is established, the interface is locked to prevent
the communication method from changes, and SCS pin is used as chip-select for the
device.
Pins used by the serial communication peripheral are listed in Table 23.
SYN Synchronization GPIO (optional), VCC at startup GPIO (optional), VCC at startup
-Start-up interface selection at -Start-up interface selection at
SCS Chip-select GND VCC
-Chip-select at GND -Chip-select at VCC
SCL Clock SPI CLK Not used
MOSI/RXD Data in SPI MOSI UART RX
MISO/TXD Data out SPI MISO UART TX
The above information is exchanged between master and slave in the same communication
session, or transaction. SPI master can issue a read-request and a write-request (optional).
The master initiates the communication sending the STPM3x a frame see Table 24 (read
address - write address - LS data byte - MS data byte - optional CRC).
Two command codes are provided:
Dummy read address 0xFF increments by one the internal read pointer
Dummy write address 0xFF specifies that no writing is requested (the two following
incoming data frames are ignored)
Upon the reception of a frame, the STPM3x replies to master data sending the 32-bit
register addressed during the previous communication session; during the first session the
slave sends, by default, the 32-bit data stored into the first (row 0) memory register. Data are
organized in 8-bit packets so that the least significant byte is sent first and the most
significant byte is sent last.
A final 8-bit CRC packet is sent to master to verify no data corruption has occurred during
the transmission from slave to master. The CRC feature, enabled by default, can be
controlled by a configuration bit into US_REG1 memory row (read address 0x24, write
address 0x24).
If CRC bit in US_REG1 is cleared, the communication consists of 4 bytes only.
Write-requests are executed immediately after the transaction has completed, while read-
requests are fulfilled at the end of the next transaction only, because the sent read-address
has just set the internal register pointer to deliver data during the following transaction.
So, while one transaction is enough to write data into memory, at least two transactions are
needed to read selected data from memory.
Data bytes are swapped with respect to the order of the byte, since during transmission, the
3rd byte sent to MOSI line is the least-significant (LS) byte (bits [7:0]) and the 4th byte is the
most-significant (MS) byte of the data to be written (bits [15:8]).
On MISO line, the first data byte received is the least-significant (LS, bits [7:0]) and the last
is the most-significant (MS, bits [31:24]) of the record, as shown below.
026,
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Data and configuration registers are organized into 32-bit rows in the internal memory, but
can only be accessed 16-bit at a time for writing operations.
The address space is 70 rows wide, so there are 70 32-bit addressable elements for reading
operations; since the first 21 configuration registers are writable, there are 42 (= 21 x 2)
16-bit addressable elements for writing operations.
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Two different codes are used for the read address space and write address space, which
can be found in the register map.
6&6
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Latch pulse width and other SPI timings are reported in Table 5 on page 17.
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Software latch
Writing S/W Latchx configuration bits of DSP_CR3 register can latch data into transmission
latches. These two bits latch channel 1 and channel 2 data registers respectively; once set,
they latch data and are automatically reset. By setting S/W Auto Latch bit, latching is
performed automatically at the rate of sampling clock, so data latching, before each reading
request, is no longer necessary.
Software reset
Writing SW Reset configuration bit in DSP_CR3 brings the configuration registers to their
default values. Data registers are not reset. This bit is automatically cleared after this action.
SPI timings
Any single transaction timing follows the scheme in Figure 5 on page 13.
For consecutive writing transactions, a minimum time interval of 4 s has to be taken into
account in order to avoid overrun issues.
For latch and consecutive read transactions a minimum time interval of 4 s has to be taken
into account in order to avoid overrun issues.
Examples
All frames in the following examples do not contain CRC byte, which has to be added just in
case the feature has not been disabled previously. After that CRC has been disabled, the
frame consists of four bytes only.
To write bits from 31 to 16 (most significant bits) in row 1 with data byte 0xABCD and read
row 2 in the following transaction, the first four bytes of the transmission (without CRC) are:
04_03_CD_AB
To receive data from register 04 the master should send the frame:
FF_FF_FF_FF
To write lower (least significant) 16-bits in row 3 with data #AABB and read back from the
same row:
06_06_BB_AA
And then
FF_FF_FF_FF
To receive
The sent frame changes according to LSBfirst setting:
LSBfirst = 1 20_C0_B3_D5
MISO line is valid as well. In this case, there is a full-reverse data transmission when
LSBfirst=1, since data bit reception order changes as shown in Table 27.
LSBfirst can be programmed using the transactions (other configuration bits involved in the
transaction are set to their default states):
LSBfirst = 0 24_24_EO_02
The transaction to write LSBfirst = 0 is byte-reversed, since the system has moved from the
LSBfirst = 1 condition. The read address is set so to read in the following transaction the
content of US_REG1.
CRCenable = 0 24_24_07_00
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As shown in Figure 52, each frame consists of 10 bits. Each bit is sent to a variable rate. All
frame data are sent LSBfirst.
If a BREAK frame is received, a break flag is set and the whole packet reception aborts.
The frame receiver can recognize an IDLE frame, but packet processing is not involved.
Timeout: any communication session should be completed within this configurable time
threshold (ms). If the timeout value is zero this threshold is disabled. If timeout expires,
the reception and the transmission processes stop and, if enabled, a BREAK character
is transmitted to warn the master about the error. Packet processing can resume only
after that BREAK transmission has been completed and an IDLE frame has been
received.
Break on error: if an error occurs (framing/noise/timeout/RX overrun) a BREAK
command is transmitted to the master.
Noise error detection. An oversampling technique is implemented to raise the noise
level immunity: received bit value is accomplished taking in account the value of three
samples, and applying to them the majority rule. This noise immunity algorithm is
automatically enabled: if “noise detection enable” bit is set, all samples must have the
same value to get a valid bit reception. In this case, when noise is detected within a
frame, a noise detection error is issued and the whole packet is discarded.
CRCPolynomial: default polynomial used is 0x07 (x8+x2+x+1).
CRC, in case of UART, has to be calculated on the reversed byte frame, because of the
internal structure of UART blocks.
For example, if the frame to transmit is 04_03_CD_AB, CRC should be calculated on the
frame:
20_C0_B3_D5 -> CRC = 0x16
The frame to send is: 04_03_CD_AB with the reversed CRC = 68
Note: For UART peripheral, CRC byte is sent reversed only.
Frame delay: delay (expressed as bit periods) in transmitted frames. The bit period
depends on the baud rate divider selection (see below).
Baud rate: set to 9600 default value, the communication baud rate can be programmed
in this configuration register. Theoretical values for configuration register can be
calculated according to the following formulas, where a main clock frequency is
16 MHz, BR is the desired baud rate and BRDIV is the theoretical value of fractional
divider:
Equation 19
Equation 20
Equation 21
where BRRI are bits [15:4] and BRRF are bits [3:0] of the register.
According to the chosen baud rate divider the bit period is:
Equation 22
Table 32 summarizes the above calculation of the register value to select some typical baud
rates:
30 SPI RX overrun 0 RW
29 SPI TX underrun 0 RW
28 SPI CRC error 0 RW
27 UART/SPI write address error 0 RW
26 UART/SPI read address error 0 RW
25 SPI TX empty 0 RO
24 SPI RX full 0 RO
SR
22 UART TX overrun 0 RW
21 UART RX overrun 0 RW
20 UART noise error 0 RW
19 UART frame error 0 RW
18 UART timeout error 0 RW
17 UART CRC error 0 RW
16 UART break 0 RW
14 mask for SPI RX overrun error status bit 0 RW
13 mask for SPI TX underrun error status bit 0 RW
12 mask for SPI CRC error status bit 0 RW
11 mask for write address error status bit 0 RW
10 mask for read address error status bit 0 RW
9 mask for SPI TX empty 0 RW
IRQ CR 8 mask for SPI RX full 0 RW
6 mask for UART TX overrun 0 RW
5 mask for UART RX overrun 0 RW
4 mask for UART noise error 0 RW
3 mask for UART frame error 0 RW
2 mask for UART timeout error 0 RW
1 mask for UART CRC error 0 RW
SPI RX overrun: occurs when two consecutive write transactions are too fast and close
to each other
SPI TX underrun: occurs when a read-back operation (= write then read the same
register) or latch/read is too fast
SPI CRC error: CRC error detected
UART/SPI write address error: write address out of range (not write address not
writable)
UART/SPI read address error: read address out of range (not read address not
readable)
SPI TX empty: transmission buffer empty (for SPI diagnostic, not recommended for
normal IRQ operations)
SPI RX full: reception buffer full (for SPI diagnostic, not recommended for normal IRQ
operations)
UART TX overrun: occurs when master and slave have different baud rates and master
transmits before reception has ended
UART RX overrun: active when received data have not been correctly processed
UART noise error: noisy bit detected
UART frame error: missing stop bit detected
UART timeout error: timeout counter expired
UART CRC error: CRC error detected
UART break: break frame (all zeros) received
Read-write status bits are set by the occurrence of the related event and are not reset when
the event ceases, on contrary master can only reset them transmitting a write sequence
addressed to memory location 0x28.
The choice of external components in the transduction section of the application is a crucial
point in the application design, affecting the precision and the resolution of the whole
system. A compromise has to be found among the following needs:
1. Maximizing signal-to-noise ratio in the voltage and current channel
2. Choosing current-to-voltage conversion ratio kS and the voltage divider ratio in a way
that calibration can be achieved for a given constant pulse CP
3. Choosing kS to take advantage of the whole current dynamic range according to
desired maximum current and resolution
In this section, the rules for a good application design are described. After the design phase,
any tolerance of the real components from these values or device internal parameter drift
can be compensated through calibration.
Please refer to Section 8.4.6 on page 48 and Section 8.4.7 on page 50 for device basic
calculations.
Equation 23
Equation 24
Note: The resistor (the former) or the current channel sensor sensitivity (the latter) must be
chosen as closer as possible to the target; small tolerance is compensated by the
calibration, to reach the target constant pulse CP.
With the above external components, the maximum measurable values of RMS voltage and
current are:
Equation 25
Equation 26
These values are calculated leaving some available room for the input range with the peak
value and minimizing modulator distortions.
The current resolution value is equal to 4 times LSBIRMS:
Equation 27
V ref
-A
I MIN = --------------------------------------------------------
15
cal I A I 2 k S k int
The dimension of the voltage channel considers the voltage divider resistor values as
770 k and 470 .
Setting CP = 64000 pulses/kWh (at LPWx = 1 - device default value) and according to
calculation above the following values are:
Current sensor 2
V ref C P 1 + R 1 R 2
sensitivity - = 3.51mV A
k S = -----------------------------------------------------------------------------------
1800 DClk A V A I cal V cal I
LED frequency at CP VN IN
PN - = 20.44Hz
LED f = ----------------------------
3600000
VMAX
IMAX
V ref
IMIN - = 5.97 mA
I MIN = --------------------------------------------------------
15
cal I A I 2 k S k int
2
V ref 1 + R 1 R 2
LSBP - = 0.818mW LSB
LSB P = ------------------------------------------------------------------------------------
28
k int A V A I k S cal V cal I 2
2
V ref 1 + R 1 R 2
LSBE - = 0.214mWs LSB
LSB E = -------------------------------------------------------------------------------------------------------------------------
17
3600 DClk k int A V A I k S cal V cal I 2
To set the desired LED pulse output, division factor LED_PWM can be set through
LPWx[3:0] bits in DSP_CR1 and DSP_CR2 configuration registers.
Referring to Section 9.1 and Section 5 on page 24, having R1 or kS calculated as stated in
the previous section, the target values of voltage and current RMS registers, XV and XI
respectively are calculated as follows:
15
V N A V cal V 2
Voltage register value at VN XV = ------------------------------------------------
V ref 1 + R 1 R 2
17
Current register value at IN I N A I cal I k S 2
X I = -----------------------------------------------------
V ref
Note: For the above calculation, the calculated value of the component kS or R1 (according to the
chosen design method) must be used; the difference of the real component is compensated
by calibration as a tolerance.
To start calibration, the device has to be programmed with the proper gain and current
sensor; moreover, to obtain the greatest correction dynamic, calibrators are initially set in
the middle of their range (0x800), thus obtaining a calibration range of ± 12.5% per voltage
or current channel.
After applying VN and current IN to the meter, a certain number of voltage and current RMS
samples must be read and averaged (please, refer to averaged register values as VAV and
IAV) to calculate voltage and channel calibrators as follows:
XV X
Calibrator value CHV = 14336 ---------- – 12288 CHC = 14336 -------I- – 12288
V AV I AV
Correction factor
phase compensation can be set per each channel, and it is executed delaying the currents
and voltage samples using bits of the phase calibration configurators: PHCx[9:0] and
PHVx[1:0].
These registers act in the same way by delaying the desired waveform by a certain quantity
given from the equations below in degree:
Current shift
Voltage shift
f line 9
Global phase shift = ---------------
- PHCx 9:0 – PHVx 1:0 2 360
SCLK
A capacitive behavior is determined by the current leading the voltage waveform to a certain
angle. In this case, there is the compensation by delaying the current waveform by the same
angle through PHCx register. For a 50 Hz line the current channel waveform maximum
delayed is:
φC ≤ 4.6035° with step φC =0.0045°
An inductive behavior has the opposite effect, so that current lags the voltage waveform. In
this case, PHV register delays the voltage waveform by the minimum angle to invert the
behavior to capacitive and then acting on PHCx register for the fine tuning of the current
waveform.
PHV impacts on the calculation of power and energies related to both current channels. For
a 50 Hz line, the voltage channel waveform maximum delayed is:
φV≤ 6.912 ° with step φV = 2.304 °.
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The θ angle can be measured through the error on active power (from LED) averaged over
a certain number of samples (for example 50) at power factor PF = 0,5.
For example, if the error = e, the phase shift between voltage and current is:
Equation 28
To compensate this error, PHC and PHV bits must be set as below, to introduce a correction
factor φ = -θ.
PHVx = 0x0
φ≥0
PHVx = 0x1
f line 9 PHCx[9] = 0x0
- 2 360 0
– ---------------
SCLK 9 SCLK
PHCx 8:0 = PHVx 2 + ---------------------------
360 f line
PHVx = 0x2
f line 10 f line 9 PHCx[9] = 0
- 2 360 – ---------------
– --------------- - 2 360
SCLK SCLK 10 SCLK
PHCx 8:0 = PHVx 2 + ---------------------------
360 f line
PHVx = 0x3
f line 9 f line 10 PHCx[9] = 0
- 2 3 360 – ---------------
– --------------- - 2 360
SCLK SCLK
9 SCLK
PHCx 8:0 = PHVx 2 + ---------------------------
360 f line
2
V ref 1 + R 1 R 2 w
Power LSB value LSB P = -------------------------------------------------------------------------------------
- ------------
28 LSB
K int A V A I k S cal V cal I 2
2
2 V ref 1 + R 1 R 2 2 w
Power offset LSB value - 2 ------------
LSB PO = LSB P 2 = -------------------------------------------------------------------------------------
K int A V A I k S cal V cal I 2
28 LSB
Power offset can be compensated by measuring the power value when the current I = 0, if
the average value is not null; the value is due to external influences, then an opposite value
should be applied to the power offset register.
Register map
There are three types of data register:
RW: read and written by application (in orange in the picture below)
RWL: the status bits, set from DSP, must be latched to read updated content, and must
be cleared by the application (in orange in the picture below)
RL: read registers only, they contain measured data and are continuously updated by
DSP, so they need to be latched before reading (in blue in the picture below)
The following nomenclature is used in the above registers:
10 Register map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRSS1_TO1[3:0]
DS10272 Rev 8
0 00 RW dsp_cr1 040000A0
LPW1 [3:0]
ENVREF1
LCS1[1:0]
LPS1[1:0]
ClearSS1
BHPFC1
BHPFV1
TC1[2:0]
APM1
AEM1
ROC1
DSP control register #2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRSS2_TO2[3:0]
1 02 RW dsp_cr2 240000A0
LPW2 [3:0]
ENVREF2
LCS2[1:0]
LPS2[1:0]
ClearSS2
BHPFC2
BHPFV2
TC2[2:0]
APM2
AEM2
ROC2
Register map
87/121
Table 42. Register map (continued)
88/121
Register map
Index
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2 04 RW dsp_cr3 000004E0
TMP_TOL[1:0]
ZCR_SEL[1:0]
REF_FREQ
LED_OFF2
LED_OFF1
S/W latch2
S/W latch1
S/W reset
EN_CUM
TMP_EN
ZCR_EN
SAG_TIME_THR[13:0]
DS10272 Rev 8
PHV1[1:0]
PHV2[1:0]
3 06 RW PHC1[9:0] PHC2[9:0] dsp_cr4 00000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
enC1
enV1
DFE Control Register 2 [31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
13 1A RW dfe_cr2 03270327
GAIN1[2:0]
enC2
enV2
Register map
89/121
Table 42. Register map (continued)
90/121
Register map
Index
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
14 1C RW dsp_irq1 00000000
PH1+PH2
C1 IRQ
V1 IRQ CR [7:0] PH1 IRQ CR[7:0] PH2 IRQ CR [7:0] IRQ
CR[3:0]
CR[3:0]
DS10272 Rev 8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 1E RW dsp_irq2 00000000
PH1+PH2
C2 IRQ
V2 IRQ CR [7:0] PH1 IRQ CR [7:0] PH2 IRQ CR [7:0] IRQ
CR[3:0]
CR[3:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Energy Overflow
16 20 RWL dsp_sr1 00000000
DS10272 Rev 8
PH1 TAMPER
Power Sign
Signal Stuck
Signal Stuck
Energy Energy
Swell Start
Swell Start
Swell End
Swell End
Sag Start Power Sign Power Sign
Per ERR
Sag End
Overflow Overflow
Nah
S R F A S R F A S R F A S R F A R A R A
Register map
91/121
Table 42. Register map (continued)
92/121
Register map
Index
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Energy Overflow
17 22 RWL dsp_sr2 00000000
DS10272 Rev 8
PH2 TAMPER
Power Sign
Signal Stuck
Signal Stuck
Energy Energy
Swell Start
Swell Start
Swell End
Swell End
Sag Start Power Sign Power Sign
Per ERR
Sag End
Overflow Overflow
Nah
S R F A S R F A S R F A S R F A R A R A
18 24 RW us_reg1 00004007
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Break on Err
Noise en
lsbfirst
crcen
Time Out [7:0] (ms) CRC Polynomial [7:0]
19 26 RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 us_reg2 00000683
Register map
93/121
Table 42. Register map (continued)
94/121
Register map
Index
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
20 28 RW UART & SPI IRQ Status Register UART & SPI IRQ Control Register us_reg3 00000000
time-out err
time-out err
write error
write error
read error
read error
DS10272 Rev 8
frame err
frame err
underrun
underrun
noise err
noise err
tx empty
tx empty
crc error
crc error
crc error
crcerror
overrun
overrun
Break
rx ovr
rx ovr
tx ovr
tx ovr
rx full
rx full
DSP live events #1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V1 C1 PH1 PH1+PH2
Energy Overflow
Energy Overflow
21 2A RL dsp_ev1 00000000
Power Sign
Power Sign
Per ERR
SWC1_EV[3:0]
SWV1_EV[3:0]
SAG1_EV[3:0]
Signal Stuck
ZCR
ZCR
Nah
S R F A S R F A R A R A
Table 42. Register map (continued)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V2 C2 PH2 PH1+PH2
Energy Overflow
22 2C RL dsp_ev2 00000000
DS10272 Rev 8
Power Sign
SWC2_EV[3:0]
SWV2_EV[3:0]
SAG2_EV[3:0]
Signal Stuck
Signal Stuck
Power Sign Power Sign
Per ERR
ZCR
ZCR
Nah
S R F A S R F A R A R A
Register map
27 36 RL Padding C2 Data [23:0] dsp_reg5 00000000
dsp_reg6 00000000
Table 42. Register map (continued)
96/121
Register map
Index
32 40 RL dsp_reg10 00000000
33 42 RL dsp_reg11 00000000
34 44 RL dsp_reg12 00000000
35 46 RL dsp_reg13 00000000
SAG2_TIME [14:0]
40 50 RL SWV2_TIME [14:0] dsp_reg18 00000000
Table 42. Register map (continued)
Register map
52 68 RL PH1 Momentary Fundamental Power[28:0] ph1_reg11 00000000
97/121
Register map
Index
A F R S
Register map
99/121
Register map STPM32, STPM33, STPM34
[13:0] TIME_VALUE Time counter threshold for voltage sag detection 0x4E0
[11:0] AH_UP1 Primary channel RMS upper threshold (for AH) 0xFFF
[21:12] OFA1 Offset for primary channel active power 0x0
[31:22] OFAF1 Offset for primary channel fundamental active power 0x0
[11:0] AH_DOWN1 Primary channel RMS lower threshold (for AH) 0xFFF
[21:12 OFR1 Offset for primary channel reactive power 0x0
[31:22] OFS1 Offset for primary channel apparent power 0x0
[11:0] AH_UP2 Secondary channel RMS upper threshold (for AH) 0xFFF
[21:12] OFA2 Offset for secondary channel active power 0x0
[31:22] OFAF2 Offset for secondary channel fundamental active power 0x0
[11:0] AH_DOWN2 Secondary channel RMS lower threshold (for AH) 0xFFF
[21:12] OFR2 Offset for secondary channel reactive power 0x0
[31:22] OFS2 Offset for secondary channel apparent power 0x0
Table 56. Row 12, digital front end control register 1 (DFE_CR1)
Bit Internal signal Description Default
Table 57. Row 13, digital front end control register 2 (DFE_CR2)
Bit Internal signal Description Default
Table 58. Row 14, DSP interrupt control mask register 1 (DSP_IRQ1)
Bit Internal signal Description Default
Table 58. Row 14, DSP interrupt control mask register 1 (DSP_IRQ1) (continued)
Bit Internal signal Description Default
Table 59. Row 15, DSP interrupt control mask register 2 (DSP_IRQ2)
Bit Internal signal Description Default
Table 59. Row 15, DSP interrupt control mask register 2 (DSP_IRQ2) (continued)
Bit Internal signal Description Default
0 Reserved 0
1 UART CRC error Activate IRQ on both INT1, INT2 for selected signals 0
2 UART timeout error Activate IRQ on both INT1, INT2 for selected signals 0
3 UART framing error Activate IRQ on both INT1, INT2 for selected signals 0
4 UART noise error Activate IRQ on both INT1, INT2 for selected signals 0
5 UART RX overrun Activate IRQ on both INT1, INT2 for selected signals 0
6 UART TX overrun Activate IRQ on both INT1, INT2 for selected signals 0
7 - Reserved 0
8 SPI RX full Activate IRQ on both INT1, INT2 for selected signals 0
9 SPI TX empty Activate IRQ on both INT1, INT2 for selected signals 0
UART/SPI read
10 Activate IRQ on both INT1, INT2 for selected signals 0
error
UART/SPI write
11 Activate IRQ on both INT1, INT2 for selected signals 0
error
12 SPI CRC error Activate IRQ on both INT1, INT2 for selected signals 0
13 SPI TX underrun Activate IRQ on both INT1, INT2 for selected signals 0
14 SPI RX overrun Activate IRQ on both INT1, INT2 for selected signals 0
15 - Reserved 0
16 UART break Break frame (all zeros) received 0
17 UART CRC error CRC error detected 0
11 Package information
B(
4)1[BIRRWSULQW
B2
8VHUGLUHFWLRQRIIHHG
12 Revision history
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