SYCL: C++ Programming for Heterogeneous Parallel Computing

“ Our users will benefit from features in the SYCL 2020 specification. New features, such as support for unified memory (USM) and reductions, are important capabilities for programming high-performance-computing hardware. In addition, support for C++17 will allow our users to write better C++ code, with both language features (such as deduction guides) and library features (such as std::optional). Other new features (such as softening the requirements on kernel functions and sharing data between host and devices) are an important step for implementing backend support for SYCL in the Kokkos and RAJA performance portability ecosystems. ”

“ At Cineca, based on our experience, we confirm the value that SYCL is bringing to the development of high-performance computing in a hybrid environment. In fact, through SYCL, it is possible to build a common and portable environment for the development of computing-intensive applications to be executed on HPC architectures configured with floating point accelerators, which allows industries and scientific communities to use the common availability of development tools, libraries of algorithms, accumulated experience. Cineca is already running the distributed Celerity runtime on top of several SYCL implementations on the new Marconi100 cluster, ranked no. 11 in the Top500, providing users with a unified API for both about 4000 NVIDIA Volta V100 GPUs and IBM Power9 host processors. SYCL 2020 is a big step towards a much leaner API that unlocks all the potential provided by modern C++ standards for accelerated data-parallel kernels, making the development of large-scale scientific software easier and more sustainable, either for industrial oriented domain applications for industries, either for scientific domain-oriented applications. ”

“ Codeplay has been deeply involved in SYCL from its original definition and we are now enabling the standard on a range of systems with our ComputeCpp product. We strongly believe SYCL is the only software standard to link all the high performance processors to a unified programming solution. Developers will find that SYCL 2020 refines the standard to streamline their development and adds some crucial new enhancements to improve productivity. ”

“ Imagination recognises the benefit of SYCL across multiple markets. Our software stacks have been designed to improve SYCL performance, enabling a straightforward path to exploit the teraflops of compute performance in our latest IP,. The ability to quickly port workloads from other proprietary APIs is a huge benefit, easing the transition from development on desktop to deployment on embedded systems. SYCL 2020 is a positive step forward for this API, enabling higher levels of performance, which will benefit developers and platform creators. ”

“ The SYCL 2020 final specification brings significant features to the industry that enable C++ developers to more productively build high-performance heterogeneous applications with unified programming across XPU architectures,. Several capabilities pioneered in the open source oneAPI C++/DPC++ compiler, such as unified shared memory, group algorithms, and sub-groups, contributed to this community effort. Open, cross-architecture programming is required for accelerated distributed computing; we look forward to continuing our collaboration to address the needs of the developer ecosystem. ”

“ With thousands of users and a wide range of applications using NERSC’s resources, we must support a wide range of programming models. In addition to directive-based approaches, we see modern C++ language-based approaches to accelerator programming, such as SYCL, as an important component of our programming environment offering for users of Perlmutter. Further, this work supports the productivity of scientific application developers and users through performance portability of applications between Aurora and Perlmutter. ”

“ NSITEXE supports the SYCL 2020 technology, which is gaining attention in embedded applications. SYCL is very important to increase productivity by hiding complexities from users. We are considering adopting this technology in our next generation of IP platforms. ”

“ For Renesas, SYCL is a key enabler for automotive ADAS/AD software developers that allows them to easily use the highly-efficient, heterogeneous accelerators of the R-Car SoC Series through the open Khronos standard. ”

“ We are excited about the extensive list of features and improvements released with the new SYCL 2020 specification. The API becomes terser and more developer friendly, while also introducing new ways for expert users to exercise fine-grained control over state-of-the-art hardware features. The move to a generalized backend model opens up new possibilities to integrate with existing legacy solutions, which is especially important in scientific research environments. As co-developers of the Celerity project, together with the University of Salerno, we are welcoming these changes and look forward to applying them within distributed-memory research and industry applications, for example as part of the recently launched EuroHPC LIGATE project. ”

“ Xilinx is excited about the progress achieved with SYCL 2020. This single-source C++ framework unifies host and device code for various kinds of accelerators in the same C++ program. With host-fallback device execution, developers can emulate device code on a CPU, exploring hardware-software co-design for adaptable computing devices. SYCL is now extensible via customizable back-ends, enabling device plug-ins for FPGAs and ACAPs. ”